[linux-2.6-block.git] / include / linux / dmar.h

/*
 * Copyright (c) 2006, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
 * Place - Suite 330, Boston, MA 02111-1307 USA.
 *
 * Copyright (C) Ashok Raj <ashok.raj@intel.com>
 * Copyright (C) Shaohua Li <shaohua.li@intel.com>
 */

#ifndef __DMAR_H__
#define __DMAR_H__

#include <linux/acpi.h>
#include <linux/types.h>
#include <linux/msi.h>
#include <linux/irqreturn.h>

struct intel_iommu;
#if defined(CONFIG_DMAR) || defined(CONFIG_INTR_REMAP)
struct dmar_drhd_unit {
	struct list_head list;		/* list of drhd units	*/
	struct  acpi_dmar_header *hdr;	/* ACPI header		*/
	u64	reg_base_addr;		/* register base address*/
	struct	pci_dev **devices; 	/* target device array	*/
	int	devices_cnt;		/* target device count	*/
	u8	ignored:1; 		/* ignore drhd		*/
	u8	include_all:1;
	struct intel_iommu *iommu;
};

extern struct list_head dmar_drhd_units;

#define for_each_drhd_unit(drhd) \
	list_for_each_entry(drhd, &dmar_drhd_units, list)

extern int dmar_table_init(void);
extern int dmar_dev_scope_init(void);

/* Intel IOMMU detection */
extern void detect_intel_iommu(void);
extern int enable_drhd_fault_handling(void);

extern int parse_ioapics_under_ir(void);
extern int alloc_iommu(struct dmar_drhd_unit *);
#else
static inline void detect_intel_iommu(void)
{
	return;
}

static inline int dmar_table_init(void)
{
	return -ENODEV;
}
static inline int enable_drhd_fault_handling(void)
{
	return -1;
}
#endif /* !CONFIG_DMAR && !CONFIG_INTR_REMAP */

struct irte {
	union {
		struct {
			__u64	present 	: 1,
				fpd		: 1,
				dst_mode	: 1,
				redir_hint	: 1,
				trigger_mode	: 1,
				dlvry_mode	: 3,
				avail		: 4,
				__reserved_1	: 4,
				vector		: 8,
				__reserved_2	: 8,
				dest_id		: 32;
		};
		__u64 low;
	};

	union {
		struct {
			__u64	sid		: 16,
				sq		: 2,
				svt		: 2,
				__reserved_3	: 44;
		};
		__u64 high;
	};
};
#ifdef CONFIG_INTR_REMAP
extern int intr_remapping_enabled;
extern int enable_intr_remapping(int);

extern int get_irte(int irq, struct irte *entry);
extern int modify_irte(int irq, struct irte *irte_modified);
extern int alloc_irte(struct intel_iommu *iommu, int irq, u16 count);
extern int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index,
   			u16 sub_handle);
extern int map_irq_to_irte_handle(int irq, u16 *sub_handle);
extern int clear_irte_irq(int irq, struct intel_iommu *iommu, u16 index);
extern int flush_irte(int irq);
extern int free_irte(int irq);

extern int irq_remapped(int irq);
extern struct intel_iommu *map_dev_to_ir(struct pci_dev *dev);
extern struct intel_iommu *map_ioapic_to_ir(int apic);
#else
static inline int alloc_irte(struct intel_iommu *iommu, int irq, u16 count)
{
	return -1;
}
static inline int modify_irte(int irq, struct irte *irte_modified)
{
	return -1;
}
static inline int free_irte(int irq)
{
	return -1;
}
static inline int map_irq_to_irte_handle(int irq, u16 *sub_handle)
{
	return -1;
}
static inline int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index,
			       u16 sub_handle)
{
	return -1;
}
static inline struct intel_iommu *map_dev_to_ir(struct pci_dev *dev)
{
	return NULL;
}
static inline struct intel_iommu *map_ioapic_to_ir(int apic)
{
	return NULL;
}
#define irq_remapped(irq)		(0)
#define enable_intr_remapping(mode)	(-1)
#define intr_remapping_enabled		(0)
#endif

/* Can't use the common MSI interrupt functions
 * since DMAR is not a pci device
 */
extern void dmar_msi_unmask(unsigned int irq);
extern void dmar_msi_mask(unsigned int irq);
extern void dmar_msi_read(int irq, struct msi_msg *msg);
extern void dmar_msi_write(int irq, struct msi_msg *msg);
extern int dmar_set_interrupt(struct intel_iommu *iommu);
extern irqreturn_t dmar_fault(int irq, void *dev_id);
extern int arch_setup_dmar_msi(unsigned int irq);

#ifdef CONFIG_DMAR
extern int iommu_detected, no_iommu;
extern struct list_head dmar_rmrr_units;
struct dmar_rmrr_unit {
	struct list_head list;		/* list of rmrr units	*/
	struct acpi_dmar_header *hdr;	/* ACPI header		*/
	u64	base_address;		/* reserved base address*/
	u64	end_address;		/* reserved end address */
	struct pci_dev **devices;	/* target devices */
	int	devices_cnt;		/* target device count */
};

#define for_each_rmrr_units(rmrr) \
	list_for_each_entry(rmrr, &dmar_rmrr_units, list)
/* Intel DMAR  initialization functions */
extern int intel_iommu_init(void);
#else
static inline int intel_iommu_init(void)
{
#ifdef CONFIG_INTR_REMAP
	return dmar_dev_scope_init();
#else
	return -ENODEV;
#endif
}
#endif /* !CONFIG_DMAR */
#endif /* __DMAR_H__ */
Commit	Line	Data
10e5247f KA	1	/*
	2	* Copyright (c) 2006, Intel Corporation.
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms and conditions of the GNU General Public License,
	6	* version 2, as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope it will be useful, but WITHOUT
	9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	* more details.
	12	*
	13	* You should have received a copy of the GNU General Public License along with
	14	* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
	15	* Place - Suite 330, Boston, MA 02111-1307 USA.
	16	*
	17	* Copyright (C) Ashok Raj <ashok.raj@intel.com>
	18	* Copyright (C) Shaohua Li <shaohua.li@intel.com>
	19	*/
	20
	21	#ifndef __DMAR_H__
	22	#define __DMAR_H__
	23
	24	#include <linux/acpi.h>
	25	#include <linux/types.h>
ba395927	26	#include <linux/msi.h>
1531a6a6	27	#include <linux/irqreturn.h>
10e5247f	28
ba395927	29	struct intel_iommu;
29b61be6	30	#if defined(CONFIG_DMAR) \|\| defined(CONFIG_INTR_REMAP)
2ae21010 SS	31	struct dmar_drhd_unit {
	32	struct list_head list; /* list of drhd units */
	33	struct acpi_dmar_header hdr; / ACPI header */
	34	u64 reg_base_addr; /* register base address*/
	35	struct pci_dev *devices; / target device array */
	36	int devices_cnt; /* target device count */
	37	u8 ignored:1; /* ignore drhd */
	38	u8 include_all:1;
	39	struct intel_iommu *iommu;
	40	};
	41
	42	extern struct list_head dmar_drhd_units;
	43
	44	#define for_each_drhd_unit(drhd) \
	45	list_for_each_entry(drhd, &dmar_drhd_units, list)
	46
	47	extern int dmar_table_init(void);
2ae21010 SS	48	extern int dmar_dev_scope_init(void);
	49
	50	/* Intel IOMMU detection */
	51	extern void detect_intel_iommu(void);
9d783ba0	52	extern int enable_drhd_fault_handling(void);
2ae21010	53
2ae21010 SS	54	extern int parse_ioapics_under_ir(void);
	55	extern int alloc_iommu(struct dmar_drhd_unit *);
	56	#else
	57	static inline void detect_intel_iommu(void)
	58	{
	59	return;
	60	}
	61
	62	static inline int dmar_table_init(void)
	63	{
	64	return -ENODEV;
	65	}
29b61be6 SS	66	static inline int enable_drhd_fault_handling(void)
	67	{
	68	return -1;
	69	}
2ae21010 SS	70	#endif /* !CONFIG_DMAR && !CONFIG_INTR_REMAP */
2ae21010 SS	71
2ae21010 SS	72	struct irte {
	73	union {
	74	struct {
	75	__u64 present : 1,
	76	fpd : 1,
	77	dst_mode : 1,
	78	redir_hint : 1,
	79	trigger_mode : 1,
	80	dlvry_mode : 3,
	81	avail : 4,
	82	__reserved_1 : 4,
	83	vector : 8,
	84	__reserved_2 : 8,
	85	dest_id : 32;
	86	};
	87	__u64 low;
	88	};
	89
	90	union {
	91	struct {
	92	__u64 sid : 16,
	93	sq : 2,
	94	svt : 2,
	95	__reserved_3 : 44;
	96	};
	97	__u64 high;
	98	};
	99	};
29b61be6 SS	100	#ifdef CONFIG_INTR_REMAP
	101	extern int intr_remapping_enabled;
	102	extern int enable_intr_remapping(int);
	103
b6fcb33a SS	104	extern int get_irte(int irq, struct irte *entry);
	105	extern int modify_irte(int irq, struct irte *irte_modified);
	106	extern int alloc_irte(struct intel_iommu *iommu, int irq, u16 count);
	107	extern int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index,
	108	u16 sub_handle);
	109	extern int map_irq_to_irte_handle(int irq, u16 *sub_handle);
	110	extern int clear_irte_irq(int irq, struct intel_iommu *iommu, u16 index);
	111	extern int flush_irte(int irq);
	112	extern int free_irte(int irq);
	113
	114	extern int irq_remapped(int irq);
75c46fa6	115	extern struct intel_iommu map_dev_to_ir(struct pci_dev dev);
89027d35	116	extern struct intel_iommu *map_ioapic_to_ir(int apic);
2ae21010	117	#else
29b61be6 SS	118	static inline int alloc_irte(struct intel_iommu *iommu, int irq, u16 count)
	119	{
	120	return -1;
	121	}
	122	static inline int modify_irte(int irq, struct irte *irte_modified)
	123	{
	124	return -1;
	125	}
	126	static inline int free_irte(int irq)
	127	{
	128	return -1;
	129	}
	130	static inline int map_irq_to_irte_handle(int irq, u16 *sub_handle)
	131	{
	132	return -1;
	133	}
	134	static inline int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index,
	135	u16 sub_handle)
	136	{
	137	return -1;
	138	}
	139	static inline struct intel_iommu map_dev_to_ir(struct pci_dev dev)
	140	{
	141	return NULL;
	142	}
	143	static inline struct intel_iommu *map_ioapic_to_ir(int apic)
	144	{
	145	return NULL;
	146	}
b6fcb33a	147	#define irq_remapped(irq) (0)
2ae21010 SS	148	#define enable_intr_remapping(mode) (-1)
	149	#define intr_remapping_enabled (0)
	150	#endif
	151
3460a6d9 KA	152	/* Can't use the common MSI interrupt functions
	153	* since DMAR is not a pci device
	154	*/
	155	extern void dmar_msi_unmask(unsigned int irq);
	156	extern void dmar_msi_mask(unsigned int irq);
	157	extern void dmar_msi_read(int irq, struct msi_msg *msg);
	158	extern void dmar_msi_write(int irq, struct msi_msg *msg);
	159	extern int dmar_set_interrupt(struct intel_iommu *iommu);
1531a6a6	160	extern irqreturn_t dmar_fault(int irq, void *dev_id);
3460a6d9 KA	161	extern int arch_setup_dmar_msi(unsigned int irq);
3460a6d9 KA	162
9d783ba0	163	#ifdef CONFIG_DMAR
2ae21010	164	extern int iommu_detected, no_iommu;
10e5247f	165	extern struct list_head dmar_rmrr_units;
10e5247f KA	166	struct dmar_rmrr_unit {
10e5247f KA	167	struct list_head list; /* list of rmrr units */
1886e8a9	168	struct acpi_dmar_header hdr; / ACPI header */
10e5247f KA	169	u64 base_address; /* reserved base address*/
	170	u64 end_address; /* reserved end address */
	171	struct pci_dev *devices; / target devices */
	172	int devices_cnt; /* target device count */
	173	};
	174
ba395927 KA	175	#define for_each_rmrr_units(rmrr) \
ba395927 KA	176	list_for_each_entry(rmrr, &dmar_rmrr_units, list)
2ae21010 SS	177	/* Intel DMAR initialization functions */
2ae21010 SS	178	extern int intel_iommu_init(void);
ba395927	179	#else
ba395927 KA	180	static inline int intel_iommu_init(void)
ba395927 KA	181	{
2ae21010 SS	182	#ifdef CONFIG_INTR_REMAP
	183	return dmar_dev_scope_init();
	184	#else
ba395927	185	return -ENODEV;
2ae21010	186	#endif
1886e8a9	187	}
ba395927	188	#endif /* !CONFIG_DMAR */
10e5247f	189	#endif /* __DMAR_H__ */