[linux-2.6-block.git] / include / linux / dma-mapping.h

#ifndef _ASM_LINUX_DMA_MAPPING_H
#define _ASM_LINUX_DMA_MAPPING_H

#include <linux/device.h>
#include <linux/err.h>

/* These definitions mirror those in pci.h, so they can be used
 * interchangeably with their PCI_ counterparts */
enum dma_data_direction {
	DMA_BIDIRECTIONAL = 0,
	DMA_TO_DEVICE = 1,
	DMA_FROM_DEVICE = 2,
	DMA_NONE = 3,
};

#define DMA_BIT_MASK(n)	(((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))

/*
 * NOTE: do not use the below macros in new code and do not add new definitions
 * here.
 *
 * Instead, just open-code DMA_BIT_MASK(n) within your driver
 */
#define DMA_64BIT_MASK	DMA_BIT_MASK(64)
#define DMA_48BIT_MASK	DMA_BIT_MASK(48)
#define DMA_47BIT_MASK	DMA_BIT_MASK(47)
#define DMA_40BIT_MASK	DMA_BIT_MASK(40)
#define DMA_39BIT_MASK	DMA_BIT_MASK(39)
#define DMA_35BIT_MASK	DMA_BIT_MASK(35)
#define DMA_32BIT_MASK	DMA_BIT_MASK(32)
#define DMA_31BIT_MASK	DMA_BIT_MASK(31)
#define DMA_30BIT_MASK	DMA_BIT_MASK(30)
#define DMA_29BIT_MASK	DMA_BIT_MASK(29)
#define DMA_28BIT_MASK	DMA_BIT_MASK(28)
#define DMA_24BIT_MASK	DMA_BIT_MASK(24)

#define DMA_MASK_NONE	0x0ULL

static inline int valid_dma_direction(int dma_direction)
{
	return ((dma_direction == DMA_BIDIRECTIONAL) ||
		(dma_direction == DMA_TO_DEVICE) ||
		(dma_direction == DMA_FROM_DEVICE));
}

static inline int is_device_dma_capable(struct device *dev)
{
	return dev->dma_mask != NULL && *dev->dma_mask != DMA_MASK_NONE;
}

#ifdef CONFIG_HAS_DMA
#include <asm/dma-mapping.h>
#else
#include <asm-generic/dma-mapping-broken.h>
#endif

/* Backwards compat, remove in 2.7.x */
#define dma_sync_single		dma_sync_single_for_cpu
#define dma_sync_sg		dma_sync_sg_for_cpu

extern u64 dma_get_required_mask(struct device *dev);

/* flags for the coherent memory api */
#define	DMA_MEMORY_MAP			0x01
#define DMA_MEMORY_IO			0x02
#define DMA_MEMORY_INCLUDES_CHILDREN	0x04
#define DMA_MEMORY_EXCLUSIVE		0x08

#ifndef ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
static inline int
dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
			    dma_addr_t device_addr, size_t size, int flags)
{
	return 0;
}

static inline void
dma_release_declared_memory(struct device *dev)
{
}

static inline void *
dma_mark_declared_memory_occupied(struct device *dev,
				  dma_addr_t device_addr, size_t size)
{
	return ERR_PTR(-EBUSY);
}
#endif

/*
 * Managed DMA API
 */
extern void *dmam_alloc_coherent(struct device *dev, size_t size,
				 dma_addr_t *dma_handle, gfp_t gfp);
extern void dmam_free_coherent(struct device *dev, size_t size, void *vaddr,
			       dma_addr_t dma_handle);
extern void *dmam_alloc_noncoherent(struct device *dev, size_t size,
				    dma_addr_t *dma_handle, gfp_t gfp);
extern void dmam_free_noncoherent(struct device *dev, size_t size, void *vaddr,
				  dma_addr_t dma_handle);
#ifdef ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
extern int dmam_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
					dma_addr_t device_addr, size_t size,
					int flags);
extern void dmam_release_declared_memory(struct device *dev);
#else /* ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY */
static inline int dmam_declare_coherent_memory(struct device *dev,
				dma_addr_t bus_addr, dma_addr_t device_addr,
				size_t size, gfp_t gfp)
{
	return 0;
}

static inline void dmam_release_declared_memory(struct device *dev)
{
}
#endif /* ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY */

#endif
Commit	Line	Data
1da177e4 LT	1	#ifndef _ASM_LINUX_DMA_MAPPING_H
	2	#define _ASM_LINUX_DMA_MAPPING_H
	3
	4	#include <linux/device.h>
	5	#include <linux/err.h>
	6
	7	/* These definitions mirror those in pci.h, so they can be used
	8	* interchangeably with their PCI_ counterparts */
	9	enum dma_data_direction {
	10	DMA_BIDIRECTIONAL = 0,
	11	DMA_TO_DEVICE = 1,
	12	DMA_FROM_DEVICE = 2,
	13	DMA_NONE = 3,
	14	};
	15
8f286c33	16	#define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))
34c65384	17
8f286c33 AM	18	/*
	19	* NOTE: do not use the below macros in new code and do not add new definitions
	20	* here.
	21	*
	22	* Instead, just open-code DMA_BIT_MASK(n) within your driver
	23	*/
	24	#define DMA_64BIT_MASK DMA_BIT_MASK(64)
34c65384 BP	25	#define DMA_48BIT_MASK DMA_BIT_MASK(48)
	26	#define DMA_47BIT_MASK DMA_BIT_MASK(47)
	27	#define DMA_40BIT_MASK DMA_BIT_MASK(40)
	28	#define DMA_39BIT_MASK DMA_BIT_MASK(39)
	29	#define DMA_35BIT_MASK DMA_BIT_MASK(35)
	30	#define DMA_32BIT_MASK DMA_BIT_MASK(32)
	31	#define DMA_31BIT_MASK DMA_BIT_MASK(31)
	32	#define DMA_30BIT_MASK DMA_BIT_MASK(30)
	33	#define DMA_29BIT_MASK DMA_BIT_MASK(29)
	34	#define DMA_28BIT_MASK DMA_BIT_MASK(28)
	35	#define DMA_24BIT_MASK DMA_BIT_MASK(24)
1da177e4	36
32e8f702 JB	37	#define DMA_MASK_NONE 0x0ULL
32e8f702 JB	38
d6bd3a39 REB	39	static inline int valid_dma_direction(int dma_direction)
	40	{
	41	return ((dma_direction == DMA_BIDIRECTIONAL) \|\|
	42	(dma_direction == DMA_TO_DEVICE) \|\|
	43	(dma_direction == DMA_FROM_DEVICE));
	44	}
	45
32e8f702 JB	46	static inline int is_device_dma_capable(struct device *dev)
	47	{
	48	return dev->dma_mask != NULL && *dev->dma_mask != DMA_MASK_NONE;
	49	}
	50
1b0fac45	51	#ifdef CONFIG_HAS_DMA
1da177e4	52	#include <asm/dma-mapping.h>
1b0fac45 DW	53	#else
	54	#include <asm-generic/dma-mapping-broken.h>
	55	#endif
1da177e4 LT	56
	57	/* Backwards compat, remove in 2.7.x */
	58	#define dma_sync_single dma_sync_single_for_cpu
	59	#define dma_sync_sg dma_sync_sg_for_cpu
	60
	61	extern u64 dma_get_required_mask(struct device *dev);
	62
	63	/* flags for the coherent memory api */
	64	#define DMA_MEMORY_MAP 0x01
	65	#define DMA_MEMORY_IO 0x02
	66	#define DMA_MEMORY_INCLUDES_CHILDREN 0x04
	67	#define DMA_MEMORY_EXCLUSIVE 0x08
	68
	69	#ifndef ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
	70	static inline int
	71	dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
	72	dma_addr_t device_addr, size_t size, int flags)
	73	{
	74	return 0;
	75	}
	76
	77	static inline void
	78	dma_release_declared_memory(struct device *dev)
	79	{
	80	}
	81
	82	static inline void *
	83	dma_mark_declared_memory_occupied(struct device *dev,
	84	dma_addr_t device_addr, size_t size)
	85	{
	86	return ERR_PTR(-EBUSY);
	87	}
	88	#endif
	89
9ac7849e TH	90	/*
	91	* Managed DMA API
	92	*/
	93	extern void dmam_alloc_coherent(struct device dev, size_t size,
	94	dma_addr_t *dma_handle, gfp_t gfp);
	95	extern void dmam_free_coherent(struct device dev, size_t size, void vaddr,
	96	dma_addr_t dma_handle);
	97	extern void dmam_alloc_noncoherent(struct device dev, size_t size,
	98	dma_addr_t *dma_handle, gfp_t gfp);
	99	extern void dmam_free_noncoherent(struct device dev, size_t size, void vaddr,
	100	dma_addr_t dma_handle);
	101	#ifdef ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
	102	extern int dmam_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
	103	dma_addr_t device_addr, size_t size,
	104	int flags);
	105	extern void dmam_release_declared_memory(struct device *dev);
	106	#else /* ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY */
	107	static inline int dmam_declare_coherent_memory(struct device *dev,
	108	dma_addr_t bus_addr, dma_addr_t device_addr,
	109	size_t size, gfp_t gfp)
	110	{
	111	return 0;
	112	}
1da177e4	113
9ac7849e TH	114	static inline void dmam_release_declared_memory(struct device *dev)
	115	{
	116	}
	117	#endif /* ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY */
1da177e4	118
9ac7849e	119	#endif