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caab277b | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
0db2e5d1 RM |
2 | /* |
3 | * Copyright (C) 2014-2015 ARM Ltd. | |
0db2e5d1 RM |
4 | */ |
5 | #ifndef __DMA_IOMMU_H | |
6 | #define __DMA_IOMMU_H | |
7 | ||
185da893 | 8 | #include <linux/errno.h> |
8a22a3e1 | 9 | #include <linux/types.h> |
0db2e5d1 RM |
10 | |
11 | #ifdef CONFIG_IOMMU_DMA | |
461a6946 | 12 | #include <linux/dma-mapping.h> |
0db2e5d1 | 13 | #include <linux/iommu.h> |
44bb7e24 | 14 | #include <linux/msi.h> |
0db2e5d1 | 15 | |
0db2e5d1 RM |
16 | /* Domain management interface for IOMMU drivers */ |
17 | int iommu_get_dma_cookie(struct iommu_domain *domain); | |
fdbe574e | 18 | int iommu_get_msi_cookie(struct iommu_domain *domain, dma_addr_t base); |
0db2e5d1 RM |
19 | void iommu_put_dma_cookie(struct iommu_domain *domain); |
20 | ||
21 | /* Setup call for arch DMA mapping code */ | |
ac6d7046 | 22 | void iommu_setup_dma_ops(struct device *dev, u64 dma_base, u64 dma_limit); |
0db2e5d1 | 23 | |
44bb7e24 | 24 | /* The DMA API isn't _quite_ the whole story, though... */ |
ece6e6f0 JG |
25 | /* |
26 | * iommu_dma_prepare_msi() - Map the MSI page in the IOMMU device | |
27 | * | |
28 | * The MSI page will be stored in @desc. | |
29 | * | |
30 | * Return: 0 on success otherwise an error describing the failure. | |
31 | */ | |
32 | int iommu_dma_prepare_msi(struct msi_desc *desc, phys_addr_t msi_addr); | |
33 | ||
34 | /* Update the MSI message if required. */ | |
35 | void iommu_dma_compose_msi_msg(struct msi_desc *desc, | |
36 | struct msi_msg *msg); | |
37 | ||
273df963 | 38 | void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list); |
44bb7e24 | 39 | |
230309d0 TM |
40 | void iommu_dma_free_cpu_cached_iovas(unsigned int cpu, |
41 | struct iommu_domain *domain); | |
42 | ||
3542dcb1 RM |
43 | extern bool iommu_dma_forcedac; |
44 | ||
185da893 | 45 | #else /* CONFIG_IOMMU_DMA */ |
0db2e5d1 RM |
46 | |
47 | struct iommu_domain; | |
ece6e6f0 | 48 | struct msi_desc; |
44bb7e24 | 49 | struct msi_msg; |
4b1c8898 | 50 | struct device; |
0db2e5d1 | 51 | |
06d60728 | 52 | static inline void iommu_setup_dma_ops(struct device *dev, u64 dma_base, |
ac6d7046 | 53 | u64 dma_limit) |
0db2e5d1 | 54 | { |
0db2e5d1 RM |
55 | } |
56 | ||
57 | static inline int iommu_get_dma_cookie(struct iommu_domain *domain) | |
58 | { | |
59 | return -ENODEV; | |
60 | } | |
61 | ||
fdbe574e RM |
62 | static inline int iommu_get_msi_cookie(struct iommu_domain *domain, dma_addr_t base) |
63 | { | |
64 | return -ENODEV; | |
65 | } | |
66 | ||
0db2e5d1 RM |
67 | static inline void iommu_put_dma_cookie(struct iommu_domain *domain) |
68 | { | |
69 | } | |
70 | ||
ece6e6f0 JG |
71 | static inline int iommu_dma_prepare_msi(struct msi_desc *desc, |
72 | phys_addr_t msi_addr) | |
73 | { | |
74 | return 0; | |
75 | } | |
76 | ||
77 | static inline void iommu_dma_compose_msi_msg(struct msi_desc *desc, | |
78 | struct msi_msg *msg) | |
79 | { | |
80 | } | |
81 | ||
273df963 RM |
82 | static inline void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list) |
83 | { | |
84 | } | |
85 | ||
0db2e5d1 | 86 | #endif /* CONFIG_IOMMU_DMA */ |
0db2e5d1 | 87 | #endif /* __DMA_IOMMU_H */ |