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1802d0be | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
e941759c ML |
2 | /* |
3 | * Fence mechanism for dma-buf to allow for asynchronous dma access | |
4 | * | |
5 | * Copyright (C) 2012 Canonical Ltd | |
6 | * Copyright (C) 2012 Texas Instruments | |
7 | * | |
8 | * Authors: | |
9 | * Rob Clark <robdclark@gmail.com> | |
10 | * Maarten Lankhorst <maarten.lankhorst@canonical.com> | |
e941759c ML |
11 | */ |
12 | ||
f54d1867 CW |
13 | #ifndef __LINUX_DMA_FENCE_H |
14 | #define __LINUX_DMA_FENCE_H | |
e941759c ML |
15 | |
16 | #include <linux/err.h> | |
17 | #include <linux/wait.h> | |
18 | #include <linux/list.h> | |
19 | #include <linux/bitops.h> | |
20 | #include <linux/kref.h> | |
21 | #include <linux/sched.h> | |
22 | #include <linux/printk.h> | |
3c3b177a | 23 | #include <linux/rcupdate.h> |
e941759c | 24 | |
f54d1867 CW |
25 | struct dma_fence; |
26 | struct dma_fence_ops; | |
27 | struct dma_fence_cb; | |
e941759c ML |
28 | |
29 | /** | |
f54d1867 | 30 | * struct dma_fence - software synchronization primitive |
e941759c | 31 | * @refcount: refcount for this fence |
f54d1867 | 32 | * @ops: dma_fence_ops associated with this fence |
3c3b177a | 33 | * @rcu: used for releasing fence with kfree_rcu |
e941759c ML |
34 | * @cb_list: list of all callbacks to call |
35 | * @lock: spin_lock_irqsave used for locking | |
36 | * @context: execution context this fence belongs to, returned by | |
f54d1867 | 37 | * dma_fence_context_alloc() |
e941759c ML |
38 | * @seqno: the sequence number of this fence inside the execution context, |
39 | * can be compared to decide which fence would be signaled later. | |
f54d1867 | 40 | * @flags: A mask of DMA_FENCE_FLAG_* defined below |
e941759c | 41 | * @timestamp: Timestamp when the fence was signaled. |
a009e975 | 42 | * @error: Optional, only valid if < 0, must be set before calling |
f54d1867 | 43 | * dma_fence_signal, indicates that the fence has completed with an error. |
e941759c ML |
44 | * |
45 | * the flags member must be manipulated and read using the appropriate | |
46 | * atomic ops (bit_*), so taking the spinlock will not be needed most | |
47 | * of the time. | |
48 | * | |
f54d1867 | 49 | * DMA_FENCE_FLAG_SIGNALED_BIT - fence is already signaled |
76250f2b | 50 | * DMA_FENCE_FLAG_TIMESTAMP_BIT - timestamp recorded for fence signaling |
f54d1867 CW |
51 | * DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT - enable_signaling might have been called |
52 | * DMA_FENCE_FLAG_USER_BITS - start of the unused bits, can be used by the | |
e941759c ML |
53 | * implementer of the fence for its own purposes. Can be used in different |
54 | * ways by different fence implementers, so do not rely on this. | |
55 | * | |
3590d50e | 56 | * Since atomic bitops are used, this is not guaranteed to be the case. |
f54d1867 | 57 | * Particularly, if the bit was set, but dma_fence_signal was called right |
e941759c | 58 | * before this bit was set, it would have been able to set the |
f54d1867 CW |
59 | * DMA_FENCE_FLAG_SIGNALED_BIT, before enable_signaling was called. |
60 | * Adding a check for DMA_FENCE_FLAG_SIGNALED_BIT after setting | |
61 | * DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT closes this race, and makes sure that | |
62 | * after dma_fence_signal was called, any enable_signaling call will have either | |
e941759c ML |
63 | * been completed, or never called at all. |
64 | */ | |
f54d1867 | 65 | struct dma_fence { |
4fe3997a | 66 | spinlock_t *lock; |
f54d1867 | 67 | const struct dma_fence_ops *ops; |
f2cb60e9 CW |
68 | /* |
69 | * We clear the callback list on kref_put so that by the time we | |
70 | * release the fence it is unused. No one should be adding to the | |
71 | * cb_list that they don't themselves hold a reference for. | |
72 | * | |
73 | * The lifetime of the timestamp is similarly tied to both the | |
74 | * rcu freelist and the cb_list. The timestamp is only set upon | |
75 | * signaling while simultaneously notifying the cb_list. Ergo, we | |
76 | * only use either the cb_list of timestamp. Upon destruction, | |
77 | * neither are accessible, and so we can use the rcu. This means | |
78 | * that the cb_list is *only* valid until the signal bit is set, | |
79 | * and to read either you *must* hold a reference to the fence, | |
80 | * and not just the rcu_read_lock. | |
81 | * | |
82 | * Listed in chronological order. | |
0e2f733a CK |
83 | */ |
84 | union { | |
0e2f733a | 85 | struct list_head cb_list; |
f2cb60e9 CW |
86 | /* @cb_list replaced by @timestamp on dma_fence_signal() */ |
87 | ktime_t timestamp; | |
88 | /* @timestamp replaced by @rcu on dma_fence_release() */ | |
89 | struct rcu_head rcu; | |
0e2f733a | 90 | }; |
76bf0db5 | 91 | u64 context; |
b312d8ca | 92 | u64 seqno; |
4fe3997a CW |
93 | unsigned long flags; |
94 | struct kref refcount; | |
a009e975 | 95 | int error; |
e941759c ML |
96 | }; |
97 | ||
f54d1867 CW |
98 | enum dma_fence_flag_bits { |
99 | DMA_FENCE_FLAG_SIGNALED_BIT, | |
76250f2b | 100 | DMA_FENCE_FLAG_TIMESTAMP_BIT, |
f54d1867 CW |
101 | DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, |
102 | DMA_FENCE_FLAG_USER_BITS, /* must always be last member */ | |
e941759c ML |
103 | }; |
104 | ||
f54d1867 CW |
105 | typedef void (*dma_fence_func_t)(struct dma_fence *fence, |
106 | struct dma_fence_cb *cb); | |
e941759c ML |
107 | |
108 | /** | |
2c269b09 DV |
109 | * struct dma_fence_cb - callback for dma_fence_add_callback() |
110 | * @node: used by dma_fence_add_callback() to append this struct to fence::cb_list | |
f54d1867 | 111 | * @func: dma_fence_func_t to call |
e941759c | 112 | * |
2c269b09 | 113 | * This struct will be initialized by dma_fence_add_callback(), additional |
f54d1867 | 114 | * data can be passed along by embedding dma_fence_cb in another struct. |
e941759c | 115 | */ |
f54d1867 | 116 | struct dma_fence_cb { |
e941759c | 117 | struct list_head node; |
f54d1867 | 118 | dma_fence_func_t func; |
e941759c ML |
119 | }; |
120 | ||
121 | /** | |
f54d1867 | 122 | * struct dma_fence_ops - operations implemented for fence |
e941759c | 123 | * |
e941759c | 124 | */ |
f54d1867 | 125 | struct dma_fence_ops { |
5e498abf CK |
126 | /** |
127 | * @use_64bit_seqno: | |
128 | * | |
129 | * True if this dma_fence implementation uses 64bit seqno, false | |
130 | * otherwise. | |
131 | */ | |
132 | bool use_64bit_seqno; | |
133 | ||
2c269b09 DV |
134 | /** |
135 | * @get_driver_name: | |
136 | * | |
137 | * Returns the driver name. This is a callback to allow drivers to | |
138 | * compute the name at runtime, without having it to store permanently | |
139 | * for each fence, or build a cache of some sort. | |
140 | * | |
141 | * This callback is mandatory. | |
142 | */ | |
f54d1867 | 143 | const char * (*get_driver_name)(struct dma_fence *fence); |
2c269b09 DV |
144 | |
145 | /** | |
146 | * @get_timeline_name: | |
147 | * | |
148 | * Return the name of the context this fence belongs to. This is a | |
149 | * callback to allow drivers to compute the name at runtime, without | |
150 | * having it to store permanently for each fence, or build a cache of | |
151 | * some sort. | |
152 | * | |
153 | * This callback is mandatory. | |
154 | */ | |
f54d1867 | 155 | const char * (*get_timeline_name)(struct dma_fence *fence); |
2c269b09 DV |
156 | |
157 | /** | |
158 | * @enable_signaling: | |
159 | * | |
160 | * Enable software signaling of fence. | |
161 | * | |
162 | * For fence implementations that have the capability for hw->hw | |
163 | * signaling, they can implement this op to enable the necessary | |
164 | * interrupts, or insert commands into cmdstream, etc, to avoid these | |
165 | * costly operations for the common case where only hw->hw | |
166 | * synchronization is required. This is called in the first | |
167 | * dma_fence_wait() or dma_fence_add_callback() path to let the fence | |
168 | * implementation know that there is another driver waiting on the | |
169 | * signal (ie. hw->sw case). | |
170 | * | |
171 | * This function can be called from atomic context, but not | |
172 | * from irq context, so normal spinlocks can be used. | |
173 | * | |
174 | * A return value of false indicates the fence already passed, | |
175 | * or some failure occurred that made it impossible to enable | |
176 | * signaling. True indicates successful enabling. | |
177 | * | |
178 | * &dma_fence.error may be set in enable_signaling, but only when false | |
179 | * is returned. | |
180 | * | |
181 | * Since many implementations can call dma_fence_signal() even when before | |
182 | * @enable_signaling has been called there's a race window, where the | |
183 | * dma_fence_signal() might result in the final fence reference being | |
184 | * released and its memory freed. To avoid this, implementations of this | |
185 | * callback should grab their own reference using dma_fence_get(), to be | |
186 | * released when the fence is signalled (through e.g. the interrupt | |
187 | * handler). | |
188 | * | |
c701317a DV |
189 | * This callback is optional. If this callback is not present, then the |
190 | * driver must always have signaling enabled. | |
2c269b09 | 191 | */ |
f54d1867 | 192 | bool (*enable_signaling)(struct dma_fence *fence); |
2c269b09 DV |
193 | |
194 | /** | |
195 | * @signaled: | |
196 | * | |
197 | * Peek whether the fence is signaled, as a fastpath optimization for | |
198 | * e.g. dma_fence_wait() or dma_fence_add_callback(). Note that this | |
199 | * callback does not need to make any guarantees beyond that a fence | |
200 | * once indicates as signalled must always return true from this | |
201 | * callback. This callback may return false even if the fence has | |
202 | * completed already, in this case information hasn't propogated throug | |
203 | * the system yet. See also dma_fence_is_signaled(). | |
204 | * | |
205 | * May set &dma_fence.error if returning true. | |
206 | * | |
207 | * This callback is optional. | |
208 | */ | |
f54d1867 | 209 | bool (*signaled)(struct dma_fence *fence); |
2c269b09 DV |
210 | |
211 | /** | |
212 | * @wait: | |
213 | * | |
418cc6ca DV |
214 | * Custom wait implementation, defaults to dma_fence_default_wait() if |
215 | * not set. | |
2c269b09 | 216 | * |
b83dcd75 CK |
217 | * Deprecated and should not be used by new implementations. Only used |
218 | * by existing implementations which need special handling for their | |
219 | * hardware reset procedure. | |
2c269b09 DV |
220 | * |
221 | * Must return -ERESTARTSYS if the wait is intr = true and the wait was | |
222 | * interrupted, and remaining jiffies if fence has signaled, or 0 if wait | |
223 | * timed out. Can also return other error values on custom implementations, | |
224 | * which should be treated as if the fence is signaled. For example a hardware | |
225 | * lockup could be reported like that. | |
2c269b09 | 226 | */ |
f54d1867 CW |
227 | signed long (*wait)(struct dma_fence *fence, |
228 | bool intr, signed long timeout); | |
2c269b09 DV |
229 | |
230 | /** | |
231 | * @release: | |
232 | * | |
233 | * Called on destruction of fence to release additional resources. | |
234 | * Can be called from irq context. This callback is optional. If it is | |
235 | * NULL, then dma_fence_free() is instead called as the default | |
236 | * implementation. | |
237 | */ | |
f54d1867 CW |
238 | void (*release)(struct dma_fence *fence); |
239 | ||
2c269b09 DV |
240 | /** |
241 | * @fence_value_str: | |
242 | * | |
243 | * Callback to fill in free-form debug info specific to this fence, like | |
244 | * the sequence number. | |
245 | * | |
246 | * This callback is optional. | |
247 | */ | |
f54d1867 | 248 | void (*fence_value_str)(struct dma_fence *fence, char *str, int size); |
2c269b09 DV |
249 | |
250 | /** | |
251 | * @timeline_value_str: | |
252 | * | |
253 | * Fills in the current value of the timeline as a string, like the | |
1b48b720 DV |
254 | * sequence number. Note that the specific fence passed to this function |
255 | * should not matter, drivers should only use it to look up the | |
256 | * corresponding timeline structures. | |
2c269b09 | 257 | */ |
f54d1867 CW |
258 | void (*timeline_value_str)(struct dma_fence *fence, |
259 | char *str, int size); | |
aec11c8d RC |
260 | |
261 | /** | |
262 | * @set_deadline: | |
263 | * | |
264 | * Callback to allow a fence waiter to inform the fence signaler of | |
265 | * an upcoming deadline, such as vblank, by which point the waiter | |
266 | * would prefer the fence to be signaled by. This is intended to | |
267 | * give feedback to the fence signaler to aid in power management | |
268 | * decisions, such as boosting GPU frequency. | |
269 | * | |
270 | * This is called without &dma_fence.lock held, it can be called | |
271 | * multiple times and from any context. Locking is up to the callee | |
272 | * if it has some state to manage. If multiple deadlines are set, | |
273 | * the expectation is to track the soonest one. If the deadline is | |
274 | * before the current time, it should be interpreted as an immediate | |
275 | * deadline. | |
276 | * | |
277 | * This callback is optional. | |
278 | */ | |
279 | void (*set_deadline)(struct dma_fence *fence, ktime_t deadline); | |
e941759c ML |
280 | }; |
281 | ||
f54d1867 | 282 | void dma_fence_init(struct dma_fence *fence, const struct dma_fence_ops *ops, |
b312d8ca | 283 | spinlock_t *lock, u64 context, u64 seqno); |
e941759c | 284 | |
f54d1867 CW |
285 | void dma_fence_release(struct kref *kref); |
286 | void dma_fence_free(struct dma_fence *fence); | |
a25efb38 | 287 | void dma_fence_describe(struct dma_fence *fence, struct seq_file *seq); |
e941759c | 288 | |
4be05420 | 289 | /** |
f54d1867 | 290 | * dma_fence_put - decreases refcount of the fence |
2c269b09 | 291 | * @fence: fence to reduce refcount of |
4be05420 | 292 | */ |
f54d1867 | 293 | static inline void dma_fence_put(struct dma_fence *fence) |
4be05420 CW |
294 | { |
295 | if (fence) | |
f54d1867 | 296 | kref_put(&fence->refcount, dma_fence_release); |
4be05420 CW |
297 | } |
298 | ||
e941759c | 299 | /** |
f54d1867 | 300 | * dma_fence_get - increases refcount of the fence |
2c269b09 | 301 | * @fence: fence to increase refcount of |
e941759c ML |
302 | * |
303 | * Returns the same fence, with refcount increased by 1. | |
304 | */ | |
f54d1867 | 305 | static inline struct dma_fence *dma_fence_get(struct dma_fence *fence) |
e941759c ML |
306 | { |
307 | if (fence) | |
308 | kref_get(&fence->refcount); | |
309 | return fence; | |
310 | } | |
311 | ||
3c3b177a | 312 | /** |
52791eee | 313 | * dma_fence_get_rcu - get a fence from a dma_resv_list with |
f54d1867 | 314 | * rcu read lock |
2c269b09 | 315 | * @fence: fence to increase refcount of |
3c3b177a ML |
316 | * |
317 | * Function returns NULL if no refcount could be obtained, or the fence. | |
318 | */ | |
f54d1867 | 319 | static inline struct dma_fence *dma_fence_get_rcu(struct dma_fence *fence) |
3c3b177a ML |
320 | { |
321 | if (kref_get_unless_zero(&fence->refcount)) | |
322 | return fence; | |
323 | else | |
324 | return NULL; | |
325 | } | |
326 | ||
e941759c | 327 | /** |
f54d1867 | 328 | * dma_fence_get_rcu_safe - acquire a reference to an RCU tracked fence |
2c269b09 | 329 | * @fencep: pointer to fence to increase refcount of |
4be05420 CW |
330 | * |
331 | * Function returns NULL if no refcount could be obtained, or the fence. | |
332 | * This function handles acquiring a reference to a fence that may be | |
5f0d5a3a | 333 | * reallocated within the RCU grace period (such as with SLAB_TYPESAFE_BY_RCU), |
4be05420 CW |
334 | * so long as the caller is using RCU on the pointer to the fence. |
335 | * | |
336 | * An alternative mechanism is to employ a seqlock to protect a bunch of | |
52791eee | 337 | * fences, such as used by struct dma_resv. When using a seqlock, |
4be05420 CW |
338 | * the seqlock must be taken before and checked after a reference to the |
339 | * fence is acquired (as shown here). | |
340 | * | |
341 | * The caller is required to hold the RCU read lock. | |
e941759c | 342 | */ |
f54d1867 | 343 | static inline struct dma_fence * |
5f72db59 | 344 | dma_fence_get_rcu_safe(struct dma_fence __rcu **fencep) |
e941759c | 345 | { |
4be05420 | 346 | do { |
f54d1867 | 347 | struct dma_fence *fence; |
4be05420 CW |
348 | |
349 | fence = rcu_dereference(*fencep); | |
f8e0731d | 350 | if (!fence) |
4be05420 CW |
351 | return NULL; |
352 | ||
f8e0731d CK |
353 | if (!dma_fence_get_rcu(fence)) |
354 | continue; | |
355 | ||
f54d1867 | 356 | /* The atomic_inc_not_zero() inside dma_fence_get_rcu() |
4be05420 CW |
357 | * provides a full memory barrier upon success (such as now). |
358 | * This is paired with the write barrier from assigning | |
359 | * to the __rcu protected fence pointer so that if that | |
360 | * pointer still matches the current fence, we know we | |
361 | * have successfully acquire a reference to it. If it no | |
362 | * longer matches, we are holding a reference to some other | |
363 | * reallocated pointer. This is possible if the allocator | |
5f0d5a3a | 364 | * is using a freelist like SLAB_TYPESAFE_BY_RCU where the |
4be05420 CW |
365 | * fence remains valid for the RCU grace period, but it |
366 | * may be reallocated. When using such allocators, we are | |
367 | * responsible for ensuring the reference we get is to | |
368 | * the right fence, as below. | |
369 | */ | |
370 | if (fence == rcu_access_pointer(*fencep)) | |
371 | return rcu_pointer_handoff(fence); | |
372 | ||
f54d1867 | 373 | dma_fence_put(fence); |
4be05420 | 374 | } while (1); |
e941759c ML |
375 | } |
376 | ||
5fbff813 DV |
377 | #ifdef CONFIG_LOCKDEP |
378 | bool dma_fence_begin_signalling(void); | |
379 | void dma_fence_end_signalling(bool cookie); | |
d0b9a9ae | 380 | void __dma_fence_might_wait(void); |
5fbff813 DV |
381 | #else |
382 | static inline bool dma_fence_begin_signalling(void) | |
383 | { | |
384 | return true; | |
385 | } | |
386 | static inline void dma_fence_end_signalling(bool cookie) {} | |
387 | static inline void __dma_fence_might_wait(void) {} | |
388 | #endif | |
389 | ||
f54d1867 CW |
390 | int dma_fence_signal(struct dma_fence *fence); |
391 | int dma_fence_signal_locked(struct dma_fence *fence); | |
5a164ac4 VSS |
392 | int dma_fence_signal_timestamp(struct dma_fence *fence, ktime_t timestamp); |
393 | int dma_fence_signal_timestamp_locked(struct dma_fence *fence, | |
394 | ktime_t timestamp); | |
f54d1867 CW |
395 | signed long dma_fence_default_wait(struct dma_fence *fence, |
396 | bool intr, signed long timeout); | |
397 | int dma_fence_add_callback(struct dma_fence *fence, | |
398 | struct dma_fence_cb *cb, | |
399 | dma_fence_func_t func); | |
400 | bool dma_fence_remove_callback(struct dma_fence *fence, | |
401 | struct dma_fence_cb *cb); | |
402 | void dma_fence_enable_sw_signaling(struct dma_fence *fence); | |
e941759c ML |
403 | |
404 | /** | |
f54d1867 CW |
405 | * dma_fence_is_signaled_locked - Return an indication if the fence |
406 | * is signaled yet. | |
2c269b09 | 407 | * @fence: the fence to check |
e941759c ML |
408 | * |
409 | * Returns true if the fence was already signaled, false if not. Since this | |
410 | * function doesn't enable signaling, it is not guaranteed to ever return | |
2c269b09 DV |
411 | * true if dma_fence_add_callback(), dma_fence_wait() or |
412 | * dma_fence_enable_sw_signaling() haven't been called before. | |
e941759c | 413 | * |
2c269b09 DV |
414 | * This function requires &dma_fence.lock to be held. |
415 | * | |
416 | * See also dma_fence_is_signaled(). | |
e941759c ML |
417 | */ |
418 | static inline bool | |
f54d1867 | 419 | dma_fence_is_signaled_locked(struct dma_fence *fence) |
e941759c | 420 | { |
f54d1867 | 421 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) |
e941759c ML |
422 | return true; |
423 | ||
424 | if (fence->ops->signaled && fence->ops->signaled(fence)) { | |
f54d1867 | 425 | dma_fence_signal_locked(fence); |
e941759c ML |
426 | return true; |
427 | } | |
428 | ||
429 | return false; | |
430 | } | |
431 | ||
432 | /** | |
f54d1867 | 433 | * dma_fence_is_signaled - Return an indication if the fence is signaled yet. |
2c269b09 | 434 | * @fence: the fence to check |
e941759c ML |
435 | * |
436 | * Returns true if the fence was already signaled, false if not. Since this | |
437 | * function doesn't enable signaling, it is not guaranteed to ever return | |
2c269b09 DV |
438 | * true if dma_fence_add_callback(), dma_fence_wait() or |
439 | * dma_fence_enable_sw_signaling() haven't been called before. | |
e941759c | 440 | * |
f54d1867 | 441 | * It's recommended for seqno fences to call dma_fence_signal when the |
e941759c ML |
442 | * operation is complete, it makes it possible to prevent issues from |
443 | * wraparound between time of issue and time of use by checking the return | |
444 | * value of this function before calling hardware-specific wait instructions. | |
2c269b09 DV |
445 | * |
446 | * See also dma_fence_is_signaled_locked(). | |
e941759c ML |
447 | */ |
448 | static inline bool | |
f54d1867 | 449 | dma_fence_is_signaled(struct dma_fence *fence) |
e941759c | 450 | { |
f54d1867 | 451 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) |
e941759c ML |
452 | return true; |
453 | ||
454 | if (fence->ops->signaled && fence->ops->signaled(fence)) { | |
f54d1867 | 455 | dma_fence_signal(fence); |
e941759c ML |
456 | return true; |
457 | } | |
458 | ||
459 | return false; | |
460 | } | |
461 | ||
81114776 CW |
462 | /** |
463 | * __dma_fence_is_later - return if f1 is chronologically later than f2 | |
2c269b09 DV |
464 | * @f1: the first fence's seqno |
465 | * @f2: the second fence's seqno from the same context | |
5e498abf | 466 | * @ops: dma_fence_ops associated with the seqno |
81114776 CW |
467 | * |
468 | * Returns true if f1 is chronologically later than f2. Both fences must be | |
469 | * from the same context, since a seqno is not common across contexts. | |
470 | */ | |
5e498abf CK |
471 | static inline bool __dma_fence_is_later(u64 f1, u64 f2, |
472 | const struct dma_fence_ops *ops) | |
81114776 | 473 | { |
b312d8ca | 474 | /* This is for backward compatibility with drivers which can only handle |
5e498abf CK |
475 | * 32bit sequence numbers. Use a 64bit compare when the driver says to |
476 | * do so. | |
b312d8ca | 477 | */ |
5e498abf | 478 | if (ops->use_64bit_seqno) |
b312d8ca CK |
479 | return f1 > f2; |
480 | ||
481 | return (int)(lower_32_bits(f1) - lower_32_bits(f2)) > 0; | |
81114776 CW |
482 | } |
483 | ||
6c455ac1 | 484 | /** |
f54d1867 | 485 | * dma_fence_is_later - return if f1 is chronologically later than f2 |
2c269b09 DV |
486 | * @f1: the first fence from the same context |
487 | * @f2: the second fence from the same context | |
6c455ac1 CK |
488 | * |
489 | * Returns true if f1 is chronologically later than f2. Both fences must be | |
490 | * from the same context, since a seqno is not re-used across contexts. | |
491 | */ | |
f54d1867 CW |
492 | static inline bool dma_fence_is_later(struct dma_fence *f1, |
493 | struct dma_fence *f2) | |
6c455ac1 CK |
494 | { |
495 | if (WARN_ON(f1->context != f2->context)) | |
496 | return false; | |
497 | ||
5e498abf | 498 | return __dma_fence_is_later(f1->seqno, f2->seqno, f1->ops); |
6c455ac1 CK |
499 | } |
500 | ||
e941759c | 501 | /** |
f54d1867 | 502 | * dma_fence_later - return the chronologically later fence |
2c269b09 DV |
503 | * @f1: the first fence from the same context |
504 | * @f2: the second fence from the same context | |
e941759c ML |
505 | * |
506 | * Returns NULL if both fences are signaled, otherwise the fence that would be | |
507 | * signaled last. Both fences must be from the same context, since a seqno is | |
508 | * not re-used across contexts. | |
509 | */ | |
f54d1867 CW |
510 | static inline struct dma_fence *dma_fence_later(struct dma_fence *f1, |
511 | struct dma_fence *f2) | |
e941759c ML |
512 | { |
513 | if (WARN_ON(f1->context != f2->context)) | |
514 | return NULL; | |
515 | ||
516 | /* | |
f54d1867 CW |
517 | * Can't check just DMA_FENCE_FLAG_SIGNALED_BIT here, it may never |
518 | * have been set if enable_signaling wasn't called, and enabling that | |
519 | * here is overkill. | |
e941759c | 520 | */ |
f54d1867 CW |
521 | if (dma_fence_is_later(f1, f2)) |
522 | return dma_fence_is_signaled(f1) ? NULL : f1; | |
6c455ac1 | 523 | else |
f54d1867 | 524 | return dma_fence_is_signaled(f2) ? NULL : f2; |
e941759c ML |
525 | } |
526 | ||
d6c99f4b CW |
527 | /** |
528 | * dma_fence_get_status_locked - returns the status upon completion | |
2c269b09 | 529 | * @fence: the dma_fence to query |
d6c99f4b CW |
530 | * |
531 | * Drivers can supply an optional error status condition before they signal | |
532 | * the fence (to indicate whether the fence was completed due to an error | |
533 | * rather than success). The value of the status condition is only valid | |
534 | * if the fence has been signaled, dma_fence_get_status_locked() first checks | |
535 | * the signal state before reporting the error status. | |
536 | * | |
537 | * Returns 0 if the fence has not yet been signaled, 1 if the fence has | |
538 | * been signaled without an error condition, or a negative error code | |
539 | * if the fence has been completed in err. | |
540 | */ | |
541 | static inline int dma_fence_get_status_locked(struct dma_fence *fence) | |
542 | { | |
543 | if (dma_fence_is_signaled_locked(fence)) | |
a009e975 | 544 | return fence->error ?: 1; |
d6c99f4b CW |
545 | else |
546 | return 0; | |
547 | } | |
548 | ||
549 | int dma_fence_get_status(struct dma_fence *fence); | |
550 | ||
a009e975 CW |
551 | /** |
552 | * dma_fence_set_error - flag an error condition on the fence | |
2c269b09 DV |
553 | * @fence: the dma_fence |
554 | * @error: the error to store | |
a009e975 CW |
555 | * |
556 | * Drivers can supply an optional error status condition before they signal | |
557 | * the fence, to indicate that the fence was completed due to an error | |
558 | * rather than success. This must be set before signaling (so that the value | |
559 | * is visible before any waiters on the signal callback are woken). This | |
560 | * helper exists to help catching erroneous setting of #dma_fence.error. | |
561 | */ | |
562 | static inline void dma_fence_set_error(struct dma_fence *fence, | |
563 | int error) | |
564 | { | |
6ce31263 DV |
565 | WARN_ON(test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)); |
566 | WARN_ON(error >= 0 || error < -MAX_ERRNO); | |
a009e975 CW |
567 | |
568 | fence->error = error; | |
569 | } | |
570 | ||
f54d1867 | 571 | signed long dma_fence_wait_timeout(struct dma_fence *, |
a519435a | 572 | bool intr, signed long timeout); |
f54d1867 CW |
573 | signed long dma_fence_wait_any_timeout(struct dma_fence **fences, |
574 | uint32_t count, | |
7392b4bb | 575 | bool intr, signed long timeout, |
576 | uint32_t *idx); | |
e941759c ML |
577 | |
578 | /** | |
f54d1867 | 579 | * dma_fence_wait - sleep until the fence gets signaled |
2c269b09 DV |
580 | * @fence: the fence to wait on |
581 | * @intr: if true, do an interruptible wait | |
e941759c ML |
582 | * |
583 | * This function will return -ERESTARTSYS if interrupted by a signal, | |
584 | * or 0 if the fence was signaled. Other error values may be | |
585 | * returned on custom implementations. | |
586 | * | |
587 | * Performs a synchronous wait on this fence. It is assumed the caller | |
588 | * directly or indirectly holds a reference to the fence, otherwise the | |
589 | * fence might be freed before return, resulting in undefined behavior. | |
2c269b09 DV |
590 | * |
591 | * See also dma_fence_wait_timeout() and dma_fence_wait_any_timeout(). | |
e941759c | 592 | */ |
f54d1867 | 593 | static inline signed long dma_fence_wait(struct dma_fence *fence, bool intr) |
e941759c ML |
594 | { |
595 | signed long ret; | |
596 | ||
f54d1867 | 597 | /* Since dma_fence_wait_timeout cannot timeout with |
e941759c ML |
598 | * MAX_SCHEDULE_TIMEOUT, only valid return values are |
599 | * -ERESTARTSYS and MAX_SCHEDULE_TIMEOUT. | |
600 | */ | |
f54d1867 | 601 | ret = dma_fence_wait_timeout(fence, intr, MAX_SCHEDULE_TIMEOUT); |
e941759c ML |
602 | |
603 | return ret < 0 ? ret : 0; | |
604 | } | |
605 | ||
aec11c8d RC |
606 | void dma_fence_set_deadline(struct dma_fence *fence, ktime_t deadline); |
607 | ||
078dec33 | 608 | struct dma_fence *dma_fence_get_stub(void); |
f781f661 | 609 | struct dma_fence *dma_fence_allocate_private_stub(ktime_t timestamp); |
f54d1867 | 610 | u64 dma_fence_context_alloc(unsigned num); |
e941759c | 611 | |
976b6d97 CK |
612 | extern const struct dma_fence_ops dma_fence_array_ops; |
613 | extern const struct dma_fence_ops dma_fence_chain_ops; | |
614 | ||
615 | /** | |
616 | * dma_fence_is_array - check if a fence is from the array subclass | |
617 | * @fence: the fence to test | |
618 | * | |
619 | * Return true if it is a dma_fence_array and false otherwise. | |
620 | */ | |
621 | static inline bool dma_fence_is_array(struct dma_fence *fence) | |
622 | { | |
623 | return fence->ops == &dma_fence_array_ops; | |
624 | } | |
625 | ||
626 | /** | |
627 | * dma_fence_is_chain - check if a fence is from the chain subclass | |
628 | * @fence: the fence to test | |
629 | * | |
630 | * Return true if it is a dma_fence_chain and false otherwise. | |
631 | */ | |
632 | static inline bool dma_fence_is_chain(struct dma_fence *fence) | |
633 | { | |
634 | return fence->ops == &dma_fence_chain_ops; | |
635 | } | |
636 | ||
637 | /** | |
638 | * dma_fence_is_container - check if a fence is a container for other fences | |
639 | * @fence: the fence to test | |
640 | * | |
641 | * Return true if this fence is a container for other fences, false otherwise. | |
642 | * This is important since we can't build up large fence structure or otherwise | |
643 | * we run into recursion during operation on those fences. | |
644 | */ | |
645 | static inline bool dma_fence_is_container(struct dma_fence *fence) | |
646 | { | |
647 | return dma_fence_is_array(fence) || dma_fence_is_chain(fence); | |
648 | } | |
649 | ||
f54d1867 | 650 | #endif /* __LINUX_DMA_FENCE_H */ |