[linux-2.6-block.git] / include / linux / cxl-event.h

/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright(c) 2023 Intel Corporation. */
#ifndef _LINUX_CXL_EVENT_H
#define _LINUX_CXL_EVENT_H

/*
 * Common Event Record Format
 * CXL rev 3.0 section 8.2.9.2.1; Table 8-42
 */
struct cxl_event_record_hdr {
	u8 length;
	u8 flags[3];
	__le16 handle;
	__le16 related_handle;
	__le64 timestamp;
	u8 maint_op_class;
	u8 reserved[15];
} __packed;

#define CXL_EVENT_RECORD_DATA_LENGTH 0x50
struct cxl_event_generic {
	struct cxl_event_record_hdr hdr;
	u8 data[CXL_EVENT_RECORD_DATA_LENGTH];
} __packed;

/*
 * General Media Event Record
 * CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43
 */
#define CXL_EVENT_GEN_MED_COMP_ID_SIZE	0x10
struct cxl_event_gen_media {
	struct cxl_event_record_hdr hdr;
	__le64 phys_addr;
	u8 descriptor;
	u8 type;
	u8 transaction_type;
	u8 validity_flags[2];
	u8 channel;
	u8 rank;
	u8 device[3];
	u8 component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE];
	u8 reserved[46];
} __packed;

/*
 * DRAM Event Record - DER
 * CXL rev 3.0 section 8.2.9.2.1.2; Table 3-44
 */
#define CXL_EVENT_DER_CORRECTION_MASK_SIZE	0x20
struct cxl_event_dram {
	struct cxl_event_record_hdr hdr;
	__le64 phys_addr;
	u8 descriptor;
	u8 type;
	u8 transaction_type;
	u8 validity_flags[2];
	u8 channel;
	u8 rank;
	u8 nibble_mask[3];
	u8 bank_group;
	u8 bank;
	u8 row[3];
	u8 column[2];
	u8 correction_mask[CXL_EVENT_DER_CORRECTION_MASK_SIZE];
	u8 reserved[0x17];
} __packed;

/*
 * Get Health Info Record
 * CXL rev 3.0 section 8.2.9.8.3.1; Table 8-100
 */
struct cxl_get_health_info {
	u8 health_status;
	u8 media_status;
	u8 add_status;
	u8 life_used;
	u8 device_temp[2];
	u8 dirty_shutdown_cnt[4];
	u8 cor_vol_err_cnt[4];
	u8 cor_per_err_cnt[4];
} __packed;

/*
 * Memory Module Event Record
 * CXL rev 3.0 section 8.2.9.2.1.3; Table 8-45
 */
struct cxl_event_mem_module {
	struct cxl_event_record_hdr hdr;
	u8 event_type;
	struct cxl_get_health_info info;
	u8 reserved[0x3d];
} __packed;

union cxl_event {
	struct cxl_event_generic generic;
	struct cxl_event_gen_media gen_media;
	struct cxl_event_dram dram;
	struct cxl_event_mem_module mem_module;
} __packed;

/*
 * Common Event Record Format; in event logs
 * CXL rev 3.0 section 8.2.9.2.1; Table 8-42
 */
struct cxl_event_record_raw {
	uuid_t id;
	union cxl_event event;
} __packed;

enum cxl_event_type {
	CXL_CPER_EVENT_GENERIC,
	CXL_CPER_EVENT_GEN_MEDIA,
	CXL_CPER_EVENT_DRAM,
	CXL_CPER_EVENT_MEM_MODULE,
};

#define CPER_CXL_DEVICE_ID_VALID		BIT(0)
#define CPER_CXL_DEVICE_SN_VALID		BIT(1)
#define CPER_CXL_COMP_EVENT_LOG_VALID		BIT(2)
struct cxl_cper_event_rec {
	struct {
		u32 length;
		u64 validation_bits;
		struct cper_cxl_event_devid {
			u16 vendor_id;
			u16 device_id;
			u8 func_num;
			u8 device_num;
			u8 bus_num;
			u16 segment_num;
			u16 slot_num; /* bits 2:0 reserved */
			u8 reserved;
		} __packed device_id;
		struct cper_cxl_event_sn {
			u32 lower_dw;
			u32 upper_dw;
		} __packed dev_serial_num;
	} __packed hdr;

	union cxl_event event;
} __packed;

typedef void (*cxl_cper_callback)(enum cxl_event_type type,
				  struct cxl_cper_event_rec *rec);

#ifdef CONFIG_ACPI_APEI_GHES
int cxl_cper_register_callback(cxl_cper_callback callback);
int cxl_cper_unregister_callback(cxl_cper_callback callback);
#else
static inline int cxl_cper_register_callback(cxl_cper_callback callback)
{
	return 0;
}

static inline int cxl_cper_unregister_callback(cxl_cper_callback callback)
{
	return 0;
}
#endif

#endif /* _LINUX_CXL_EVENT_H */
Commit	Line	Data
26a1a86d IW	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	/* Copyright(c) 2023 Intel Corporation. */
	3	#ifndef _LINUX_CXL_EVENT_H
	4	#define _LINUX_CXL_EVENT_H
	5
	6	/*
	7	* Common Event Record Format
	8	* CXL rev 3.0 section 8.2.9.2.1; Table 8-42
	9	*/
	10	struct cxl_event_record_hdr {
26a1a86d IW	11	u8 length;
	12	u8 flags[3];
	13	__le16 handle;
	14	__le16 related_handle;
	15	__le64 timestamp;
	16	u8 maint_op_class;
	17	u8 reserved[15];
	18	} __packed;
	19
	20	#define CXL_EVENT_RECORD_DATA_LENGTH 0x50
f9c68338	21	struct cxl_event_generic {
26a1a86d IW	22	struct cxl_event_record_hdr hdr;
	23	u8 data[CXL_EVENT_RECORD_DATA_LENGTH];
	24	} __packed;
	25
	26	/*
	27	* General Media Event Record
	28	* CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43
	29	*/
	30	#define CXL_EVENT_GEN_MED_COMP_ID_SIZE 0x10
	31	struct cxl_event_gen_media {
	32	struct cxl_event_record_hdr hdr;
	33	__le64 phys_addr;
	34	u8 descriptor;
	35	u8 type;
	36	u8 transaction_type;
	37	u8 validity_flags[2];
	38	u8 channel;
	39	u8 rank;
	40	u8 device[3];
	41	u8 component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE];
	42	u8 reserved[46];
	43	} __packed;
	44
	45	/*
	46	* DRAM Event Record - DER
	47	* CXL rev 3.0 section 8.2.9.2.1.2; Table 3-44
	48	*/
	49	#define CXL_EVENT_DER_CORRECTION_MASK_SIZE 0x20
	50	struct cxl_event_dram {
	51	struct cxl_event_record_hdr hdr;
	52	__le64 phys_addr;
	53	u8 descriptor;
	54	u8 type;
	55	u8 transaction_type;
	56	u8 validity_flags[2];
	57	u8 channel;
	58	u8 rank;
	59	u8 nibble_mask[3];
	60	u8 bank_group;
	61	u8 bank;
	62	u8 row[3];
	63	u8 column[2];
	64	u8 correction_mask[CXL_EVENT_DER_CORRECTION_MASK_SIZE];
	65	u8 reserved[0x17];
	66	} __packed;
	67
	68	/*
	69	* Get Health Info Record
	70	* CXL rev 3.0 section 8.2.9.8.3.1; Table 8-100
	71	*/
	72	struct cxl_get_health_info {
	73	u8 health_status;
	74	u8 media_status;
	75	u8 add_status;
	76	u8 life_used;
	77	u8 device_temp[2];
	78	u8 dirty_shutdown_cnt[4];
	79	u8 cor_vol_err_cnt[4];
	80	u8 cor_per_err_cnt[4];
	81	} __packed;
	82
	83	/*
	84	* Memory Module Event Record
	85	* CXL rev 3.0 section 8.2.9.2.1.3; Table 8-45
86	*/
87	struct cxl_event_mem_module {
88	struct cxl_event_record_hdr hdr;
89	u8 event_type;
90	struct cxl_get_health_info info;
91	u8 reserved[0x3d];
92	} __packed;
93
f9c68338 IW	94	union cxl_event {
	95	struct cxl_event_generic generic;
	96	struct cxl_event_gen_media gen_media;
	97	struct cxl_event_dram dram;
	98	struct cxl_event_mem_module mem_module;
	99	} __packed;
	100
	101	/*
	102	* Common Event Record Format; in event logs
	103	* CXL rev 3.0 section 8.2.9.2.1; Table 8-42
	104	*/
	105	struct cxl_event_record_raw {
	106	uuid_t id;
	107	union cxl_event event;
	108	} __packed;
	109
671a794c	110	enum cxl_event_type {
dc97f634	111	CXL_CPER_EVENT_GENERIC,
671a794c IW	112	CXL_CPER_EVENT_GEN_MEDIA,
	113	CXL_CPER_EVENT_DRAM,
	114	CXL_CPER_EVENT_MEM_MODULE,
	115	};
	116
	117	#define CPER_CXL_DEVICE_ID_VALID BIT(0)
	118	#define CPER_CXL_DEVICE_SN_VALID BIT(1)
	119	#define CPER_CXL_COMP_EVENT_LOG_VALID BIT(2)
	120	struct cxl_cper_event_rec {
	121	struct {
	122	u32 length;
	123	u64 validation_bits;
	124	struct cper_cxl_event_devid {
	125	u16 vendor_id;
	126	u16 device_id;
	127	u8 func_num;
	128	u8 device_num;
	129	u8 bus_num;
	130	u16 segment_num;
	131	u16 slot_num; /* bits 2:0 reserved */
	132	u8 reserved;
	133	} __packed device_id;
	134	struct cper_cxl_event_sn {
	135	u32 lower_dw;
	136	u32 upper_dw;
	137	} __packed dev_serial_num;
	138	} __packed hdr;
	139
	140	union cxl_event event;
	141	} __packed;
	142
	143	typedef void (*cxl_cper_callback)(enum cxl_event_type type,
	144	struct cxl_cper_event_rec *rec);
	145
	146	#ifdef CONFIG_ACPI_APEI_GHES
	147	int cxl_cper_register_callback(cxl_cper_callback callback);
	148	int cxl_cper_unregister_callback(cxl_cper_callback callback);
	149	#else
	150	static inline int cxl_cper_register_callback(cxl_cper_callback callback)
	151	{
	152	return 0;
	153	}
	154
	155	static inline int cxl_cper_unregister_callback(cxl_cper_callback callback)
	156	{
	157	return 0;
	158	}
	159	#endif
	160
26a1a86d	161	#endif /* _LINUX_CXL_EVENT_H */