Commit | Line | Data |
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06d65dea HY |
1 | /* |
2 | * UEFI Common Platform Error Record | |
3 | * | |
4 | * Copyright (C) 2010, Intel Corp. | |
5 | * Author: Huang Ying <ying.huang@intel.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License version | |
9 | * 2 as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
20 | ||
21 | #ifndef LINUX_CPER_H | |
22 | #define LINUX_CPER_H | |
23 | ||
24 | #include <linux/uuid.h> | |
2dfb7d51 | 25 | #include <linux/trace_seq.h> |
06d65dea HY |
26 | |
27 | /* CPER record signature and the size */ | |
28 | #define CPER_SIG_RECORD "CPER" | |
29 | #define CPER_SIG_SIZE 4 | |
30 | /* Used in signature_end field in struct cper_record_header */ | |
31 | #define CPER_SIG_END 0xffffffff | |
32 | ||
33 | /* | |
34 | * CPER record header revision, used in revision field in struct | |
35 | * cper_record_header | |
36 | */ | |
37 | #define CPER_RECORD_REV 0x0100 | |
38 | ||
3760cd20 CG |
39 | /* |
40 | * CPER record length contains the CPER fields which are relevant for further | |
41 | * handling of a memory error in userspace (we don't carry all the fields | |
42 | * defined in the UEFI spec because some of them don't make any sense.) | |
43 | * Currently, a length of 256 should be more than enough. | |
44 | */ | |
45 | #define CPER_REC_LEN 256 | |
06d65dea HY |
46 | /* |
47 | * Severity difinition for error_severity in struct cper_record_header | |
48 | * and section_severity in struct cper_section_descriptor | |
49 | */ | |
c9aa308f HY |
50 | enum { |
51 | CPER_SEV_RECOVERABLE, | |
52 | CPER_SEV_FATAL, | |
53 | CPER_SEV_CORRECTED, | |
54 | CPER_SEV_INFORMATIONAL, | |
55 | }; | |
06d65dea HY |
56 | |
57 | /* | |
58 | * Validation bits difinition for validation_bits in struct | |
59 | * cper_record_header. If set, corresponding fields in struct | |
60 | * cper_record_header contain valid information. | |
61 | * | |
62 | * corresponds platform_id | |
63 | */ | |
64 | #define CPER_VALID_PLATFORM_ID 0x0001 | |
65 | /* corresponds timestamp */ | |
66 | #define CPER_VALID_TIMESTAMP 0x0002 | |
67 | /* corresponds partition_id */ | |
68 | #define CPER_VALID_PARTITION_ID 0x0004 | |
69 | ||
70 | /* | |
71 | * Notification type used to generate error record, used in | |
72 | * notification_type in struct cper_record_header | |
73 | * | |
74 | * Corrected Machine Check | |
75 | */ | |
76 | #define CPER_NOTIFY_CMC \ | |
c0020756 AS |
77 | GUID_INIT(0x2DCE8BB1, 0xBDD7, 0x450e, 0xB9, 0xAD, 0x9C, 0xF4, \ |
78 | 0xEB, 0xD4, 0xF8, 0x90) | |
06d65dea HY |
79 | /* Corrected Platform Error */ |
80 | #define CPER_NOTIFY_CPE \ | |
c0020756 AS |
81 | GUID_INIT(0x4E292F96, 0xD843, 0x4a55, 0xA8, 0xC2, 0xD4, 0x81, \ |
82 | 0xF2, 0x7E, 0xBE, 0xEE) | |
06d65dea HY |
83 | /* Machine Check Exception */ |
84 | #define CPER_NOTIFY_MCE \ | |
c0020756 AS |
85 | GUID_INIT(0xE8F56FFE, 0x919C, 0x4cc5, 0xBA, 0x88, 0x65, 0xAB, \ |
86 | 0xE1, 0x49, 0x13, 0xBB) | |
06d65dea HY |
87 | /* PCI Express Error */ |
88 | #define CPER_NOTIFY_PCIE \ | |
c0020756 AS |
89 | GUID_INIT(0xCF93C01F, 0x1A16, 0x4dfc, 0xB8, 0xBC, 0x9C, 0x4D, \ |
90 | 0xAF, 0x67, 0xC1, 0x04) | |
06d65dea HY |
91 | /* INIT Record (for IPF) */ |
92 | #define CPER_NOTIFY_INIT \ | |
c0020756 AS |
93 | GUID_INIT(0xCC5263E8, 0x9308, 0x454a, 0x89, 0xD0, 0x34, 0x0B, \ |
94 | 0xD3, 0x9B, 0xC9, 0x8E) | |
06d65dea HY |
95 | /* Non-Maskable Interrupt */ |
96 | #define CPER_NOTIFY_NMI \ | |
c0020756 AS |
97 | GUID_INIT(0x5BAD89FF, 0xB7E6, 0x42c9, 0x81, 0x4A, 0xCF, 0x24, \ |
98 | 0x85, 0xD6, 0xE9, 0x8A) | |
06d65dea HY |
99 | /* BOOT Error Record */ |
100 | #define CPER_NOTIFY_BOOT \ | |
c0020756 AS |
101 | GUID_INIT(0x3D61A466, 0xAB40, 0x409a, 0xA6, 0x98, 0xF3, 0x62, \ |
102 | 0xD4, 0x64, 0xB3, 0x8F) | |
06d65dea HY |
103 | /* DMA Remapping Error */ |
104 | #define CPER_NOTIFY_DMAR \ | |
c0020756 AS |
105 | GUID_INIT(0x667DD791, 0xC6B3, 0x4c27, 0x8A, 0x6B, 0x0F, 0x8E, \ |
106 | 0x72, 0x2D, 0xEB, 0x41) | |
06d65dea HY |
107 | |
108 | /* | |
109 | * Flags bits definitions for flags in struct cper_record_header | |
110 | * If set, the error has been recovered | |
111 | */ | |
112 | #define CPER_HW_ERROR_FLAGS_RECOVERED 0x1 | |
113 | /* If set, the error is for previous boot */ | |
114 | #define CPER_HW_ERROR_FLAGS_PREVERR 0x2 | |
115 | /* If set, the error is injected for testing */ | |
116 | #define CPER_HW_ERROR_FLAGS_SIMULATED 0x4 | |
117 | ||
118 | /* | |
119 | * CPER section header revision, used in revision field in struct | |
120 | * cper_section_descriptor | |
121 | */ | |
122 | #define CPER_SEC_REV 0x0100 | |
123 | ||
124 | /* | |
125 | * Validation bits difinition for validation_bits in struct | |
126 | * cper_section_descriptor. If set, corresponding fields in struct | |
127 | * cper_section_descriptor contain valid information. | |
128 | * | |
129 | * corresponds fru_id | |
130 | */ | |
131 | #define CPER_SEC_VALID_FRU_ID 0x1 | |
132 | /* corresponds fru_text */ | |
133 | #define CPER_SEC_VALID_FRU_TEXT 0x2 | |
134 | ||
135 | /* | |
136 | * Flags bits definitions for flags in struct cper_section_descriptor | |
137 | * | |
138 | * If set, the section is associated with the error condition | |
139 | * directly, and should be focused on | |
140 | */ | |
141 | #define CPER_SEC_PRIMARY 0x0001 | |
142 | /* | |
143 | * If set, the error was not contained within the processor or memory | |
144 | * hierarchy and the error may have propagated to persistent storage | |
145 | * or network | |
146 | */ | |
147 | #define CPER_SEC_CONTAINMENT_WARNING 0x0002 | |
148 | /* If set, the component must be re-initialized or re-enabled prior to use */ | |
149 | #define CPER_SEC_RESET 0x0004 | |
150 | /* If set, Linux may choose to discontinue use of the resource */ | |
151 | #define CPER_SEC_ERROR_THRESHOLD_EXCEEDED 0x0008 | |
152 | /* | |
153 | * If set, resource could not be queried for error information due to | |
154 | * conflicts with other system software or resources. Some fields of | |
155 | * the section will be invalid | |
156 | */ | |
157 | #define CPER_SEC_RESOURCE_NOT_ACCESSIBLE 0x0010 | |
158 | /* | |
159 | * If set, action has been taken to ensure error containment (such as | |
160 | * poisoning data), but the error has not been fully corrected and the | |
161 | * data has not been consumed. Linux may choose to take further | |
162 | * corrective action before the data is consumed | |
163 | */ | |
164 | #define CPER_SEC_LATENT_ERROR 0x0020 | |
165 | ||
166 | /* | |
167 | * Section type definitions, used in section_type field in struct | |
168 | * cper_section_descriptor | |
169 | * | |
170 | * Processor Generic | |
171 | */ | |
172 | #define CPER_SEC_PROC_GENERIC \ | |
c0020756 AS |
173 | GUID_INIT(0x9876CCAD, 0x47B4, 0x4bdb, 0xB6, 0x5E, 0x16, 0xF1, \ |
174 | 0x93, 0xC4, 0xF3, 0xDB) | |
06d65dea HY |
175 | /* Processor Specific: X86/X86_64 */ |
176 | #define CPER_SEC_PROC_IA \ | |
c0020756 AS |
177 | GUID_INIT(0xDC3EA0B0, 0xA144, 0x4797, 0xB9, 0x5B, 0x53, 0xFA, \ |
178 | 0x24, 0x2B, 0x6E, 0x1D) | |
06d65dea HY |
179 | /* Processor Specific: IA64 */ |
180 | #define CPER_SEC_PROC_IPF \ | |
c0020756 AS |
181 | GUID_INIT(0xE429FAF1, 0x3CB7, 0x11D4, 0x0B, 0xCA, 0x07, 0x00, \ |
182 | 0x80, 0xC7, 0x3C, 0x88, 0x81) | |
2f74f09b TB |
183 | /* Processor Specific: ARM */ |
184 | #define CPER_SEC_PROC_ARM \ | |
c0020756 AS |
185 | GUID_INIT(0xE19E3D16, 0xBC11, 0x11E4, 0x9C, 0xAA, 0xC2, 0x05, \ |
186 | 0x1D, 0x5D, 0x46, 0xB0) | |
06d65dea HY |
187 | /* Platform Memory */ |
188 | #define CPER_SEC_PLATFORM_MEM \ | |
c0020756 AS |
189 | GUID_INIT(0xA5BC1114, 0x6F64, 0x4EDE, 0xB8, 0x63, 0x3E, 0x83, \ |
190 | 0xED, 0x7C, 0x83, 0xB1) | |
06d65dea | 191 | #define CPER_SEC_PCIE \ |
c0020756 AS |
192 | GUID_INIT(0xD995E954, 0xBBC1, 0x430F, 0xAD, 0x91, 0xB4, 0x4D, \ |
193 | 0xCB, 0x3C, 0x6F, 0x35) | |
06d65dea HY |
194 | /* Firmware Error Record Reference */ |
195 | #define CPER_SEC_FW_ERR_REC_REF \ | |
c0020756 AS |
196 | GUID_INIT(0x81212A96, 0x09ED, 0x4996, 0x94, 0x71, 0x8D, 0x72, \ |
197 | 0x9C, 0x8E, 0x69, 0xED) | |
06d65dea HY |
198 | /* PCI/PCI-X Bus */ |
199 | #define CPER_SEC_PCI_X_BUS \ | |
c0020756 AS |
200 | GUID_INIT(0xC5753963, 0x3B84, 0x4095, 0xBF, 0x78, 0xED, 0xDA, \ |
201 | 0xD3, 0xF9, 0xC9, 0xDD) | |
06d65dea HY |
202 | /* PCI Component/Device */ |
203 | #define CPER_SEC_PCI_DEV \ | |
c0020756 AS |
204 | GUID_INIT(0xEB5E4685, 0xCA66, 0x4769, 0xB6, 0xA2, 0x26, 0x06, \ |
205 | 0x8B, 0x00, 0x13, 0x26) | |
06d65dea | 206 | #define CPER_SEC_DMAR_GENERIC \ |
c0020756 AS |
207 | GUID_INIT(0x5B51FEF7, 0xC79D, 0x4434, 0x8F, 0x1B, 0xAA, 0x62, \ |
208 | 0xDE, 0x3E, 0x2C, 0x64) | |
06d65dea HY |
209 | /* Intel VT for Directed I/O specific DMAr */ |
210 | #define CPER_SEC_DMAR_VT \ | |
c0020756 AS |
211 | GUID_INIT(0x71761D37, 0x32B2, 0x45cd, 0xA7, 0xD0, 0xB0, 0xFE, \ |
212 | 0xDD, 0x93, 0xE8, 0xCF) | |
06d65dea HY |
213 | /* IOMMU specific DMAr */ |
214 | #define CPER_SEC_DMAR_IOMMU \ | |
c0020756 AS |
215 | GUID_INIT(0x036F84E1, 0x7F37, 0x428c, 0xA7, 0x9E, 0x57, 0x5F, \ |
216 | 0xDF, 0xAA, 0x84, 0xEC) | |
06d65dea | 217 | |
c9aa308f HY |
218 | #define CPER_PROC_VALID_TYPE 0x0001 |
219 | #define CPER_PROC_VALID_ISA 0x0002 | |
220 | #define CPER_PROC_VALID_ERROR_TYPE 0x0004 | |
221 | #define CPER_PROC_VALID_OPERATION 0x0008 | |
222 | #define CPER_PROC_VALID_FLAGS 0x0010 | |
223 | #define CPER_PROC_VALID_LEVEL 0x0020 | |
224 | #define CPER_PROC_VALID_VERSION 0x0040 | |
225 | #define CPER_PROC_VALID_BRAND_INFO 0x0080 | |
226 | #define CPER_PROC_VALID_ID 0x0100 | |
227 | #define CPER_PROC_VALID_TARGET_ADDRESS 0x0200 | |
228 | #define CPER_PROC_VALID_REQUESTOR_ID 0x0400 | |
229 | #define CPER_PROC_VALID_RESPONDER_ID 0x0800 | |
230 | #define CPER_PROC_VALID_IP 0x1000 | |
231 | ||
232 | #define CPER_MEM_VALID_ERROR_STATUS 0x0001 | |
147de147 CG |
233 | #define CPER_MEM_VALID_PA 0x0002 |
234 | #define CPER_MEM_VALID_PA_MASK 0x0004 | |
c9aa308f HY |
235 | #define CPER_MEM_VALID_NODE 0x0008 |
236 | #define CPER_MEM_VALID_CARD 0x0010 | |
237 | #define CPER_MEM_VALID_MODULE 0x0020 | |
238 | #define CPER_MEM_VALID_BANK 0x0040 | |
239 | #define CPER_MEM_VALID_DEVICE 0x0080 | |
240 | #define CPER_MEM_VALID_ROW 0x0100 | |
241 | #define CPER_MEM_VALID_COLUMN 0x0200 | |
242 | #define CPER_MEM_VALID_BIT_POSITION 0x0400 | |
243 | #define CPER_MEM_VALID_REQUESTOR_ID 0x0800 | |
244 | #define CPER_MEM_VALID_RESPONDER_ID 0x1000 | |
245 | #define CPER_MEM_VALID_TARGET_ID 0x2000 | |
246 | #define CPER_MEM_VALID_ERROR_TYPE 0x4000 | |
147de147 CG |
247 | #define CPER_MEM_VALID_RANK_NUMBER 0x8000 |
248 | #define CPER_MEM_VALID_CARD_HANDLE 0x10000 | |
249 | #define CPER_MEM_VALID_MODULE_HANDLE 0x20000 | |
c9aa308f HY |
250 | |
251 | #define CPER_PCIE_VALID_PORT_TYPE 0x0001 | |
252 | #define CPER_PCIE_VALID_VERSION 0x0002 | |
253 | #define CPER_PCIE_VALID_COMMAND_STATUS 0x0004 | |
254 | #define CPER_PCIE_VALID_DEVICE_ID 0x0008 | |
255 | #define CPER_PCIE_VALID_SERIAL_NUMBER 0x0010 | |
256 | #define CPER_PCIE_VALID_BRIDGE_CONTROL_STATUS 0x0020 | |
257 | #define CPER_PCIE_VALID_CAPABILITY 0x0040 | |
258 | #define CPER_PCIE_VALID_AER_INFO 0x0080 | |
259 | ||
260 | #define CPER_PCIE_SLOT_SHIFT 3 | |
261 | ||
2f74f09b TB |
262 | #define CPER_ARM_VALID_MPIDR BIT(0) |
263 | #define CPER_ARM_VALID_AFFINITY_LEVEL BIT(1) | |
264 | #define CPER_ARM_VALID_RUNNING_STATE BIT(2) | |
265 | #define CPER_ARM_VALID_VENDOR_INFO BIT(3) | |
266 | ||
267 | #define CPER_ARM_INFO_VALID_MULTI_ERR BIT(0) | |
268 | #define CPER_ARM_INFO_VALID_FLAGS BIT(1) | |
269 | #define CPER_ARM_INFO_VALID_ERR_INFO BIT(2) | |
270 | #define CPER_ARM_INFO_VALID_VIRT_ADDR BIT(3) | |
271 | #define CPER_ARM_INFO_VALID_PHYSICAL_ADDR BIT(4) | |
272 | ||
273 | #define CPER_ARM_INFO_FLAGS_FIRST BIT(0) | |
274 | #define CPER_ARM_INFO_FLAGS_LAST BIT(1) | |
275 | #define CPER_ARM_INFO_FLAGS_PROPAGATED BIT(2) | |
276 | #define CPER_ARM_INFO_FLAGS_OVERFLOW BIT(3) | |
277 | ||
06d65dea HY |
278 | /* |
279 | * All tables and structs must be byte-packed to match CPER | |
280 | * specification, since the tables are provided by the system BIOS | |
281 | */ | |
282 | #pragma pack(1) | |
283 | ||
284 | struct cper_record_header { | |
285 | char signature[CPER_SIG_SIZE]; /* must be CPER_SIG_RECORD */ | |
286 | __u16 revision; /* must be CPER_RECORD_REV */ | |
287 | __u32 signature_end; /* must be CPER_SIG_END */ | |
288 | __u16 section_count; | |
289 | __u32 error_severity; | |
290 | __u32 validation_bits; | |
291 | __u32 record_length; | |
292 | __u64 timestamp; | |
c0020756 AS |
293 | guid_t platform_id; |
294 | guid_t partition_id; | |
295 | guid_t creator_id; | |
296 | guid_t notification_type; | |
06d65dea HY |
297 | __u64 record_id; |
298 | __u32 flags; | |
299 | __u64 persistence_information; | |
300 | __u8 reserved[12]; /* must be zero */ | |
301 | }; | |
302 | ||
303 | struct cper_section_descriptor { | |
304 | __u32 section_offset; /* Offset in bytes of the | |
305 | * section body from the base | |
306 | * of the record header */ | |
307 | __u32 section_length; | |
308 | __u16 revision; /* must be CPER_RECORD_REV */ | |
309 | __u8 validation_bits; | |
310 | __u8 reserved; /* must be zero */ | |
311 | __u32 flags; | |
c0020756 AS |
312 | guid_t section_type; |
313 | guid_t fru_id; | |
06d65dea HY |
314 | __u32 section_severity; |
315 | __u8 fru_text[20]; | |
316 | }; | |
317 | ||
318 | /* Generic Processor Error Section */ | |
319 | struct cper_sec_proc_generic { | |
320 | __u64 validation_bits; | |
321 | __u8 proc_type; | |
322 | __u8 proc_isa; | |
323 | __u8 proc_error_type; | |
324 | __u8 operation; | |
325 | __u8 flags; | |
326 | __u8 level; | |
327 | __u16 reserved; | |
328 | __u64 cpu_version; | |
329 | char cpu_brand[128]; | |
330 | __u64 proc_id; | |
331 | __u64 target_addr; | |
332 | __u64 requestor_id; | |
333 | __u64 responder_id; | |
334 | __u64 ip; | |
335 | }; | |
336 | ||
337 | /* IA32/X64 Processor Error Section */ | |
338 | struct cper_sec_proc_ia { | |
339 | __u64 validation_bits; | |
340 | __u8 lapic_id; | |
341 | __u8 cpuid[48]; | |
342 | }; | |
343 | ||
25985edc | 344 | /* IA32/X64 Processor Error Information Structure */ |
06d65dea | 345 | struct cper_ia_err_info { |
c0020756 | 346 | guid_t err_type; |
06d65dea HY |
347 | __u64 validation_bits; |
348 | __u64 check_info; | |
349 | __u64 target_id; | |
350 | __u64 requestor_id; | |
351 | __u64 responder_id; | |
352 | __u64 ip; | |
353 | }; | |
354 | ||
355 | /* IA32/X64 Processor Context Information Structure */ | |
356 | struct cper_ia_proc_ctx { | |
357 | __u16 reg_ctx_type; | |
358 | __u16 reg_arr_size; | |
359 | __u32 msr_addr; | |
360 | __u64 mm_reg_addr; | |
361 | }; | |
362 | ||
2f74f09b TB |
363 | /* ARM Processor Error Section */ |
364 | struct cper_sec_proc_arm { | |
365 | __u32 validation_bits; | |
366 | __u16 err_info_num; /* Number of Processor Error Info */ | |
367 | __u16 context_info_num; /* Number of Processor Context Info Records*/ | |
368 | __u32 section_length; | |
369 | __u8 affinity_level; | |
370 | __u8 reserved[3]; /* must be zero */ | |
371 | __u64 mpidr; | |
372 | __u64 midr; | |
373 | __u32 running_state; /* Bit 0 set - Processor running. PSCI = 0 */ | |
374 | __u32 psci_state; | |
375 | }; | |
376 | ||
377 | /* ARM Processor Error Information Structure */ | |
378 | struct cper_arm_err_info { | |
379 | __u8 version; | |
380 | __u8 length; | |
381 | __u16 validation_bits; | |
382 | __u8 type; | |
383 | __u16 multiple_error; | |
384 | __u8 flags; | |
385 | __u64 error_info; | |
386 | __u64 virt_fault_addr; | |
387 | __u64 physical_fault_addr; | |
388 | }; | |
389 | ||
390 | /* ARM Processor Context Information Structure */ | |
391 | struct cper_arm_ctx_info { | |
392 | __u16 version; | |
393 | __u16 type; | |
394 | __u32 size; | |
395 | }; | |
396 | ||
4c62360d LT |
397 | /* Old Memory Error Section UEFI 2.1, 2.2 */ |
398 | struct cper_sec_mem_err_old { | |
399 | __u64 validation_bits; | |
400 | __u64 error_status; | |
401 | __u64 physical_addr; | |
402 | __u64 physical_addr_mask; | |
403 | __u16 node; | |
404 | __u16 card; | |
405 | __u16 module; | |
406 | __u16 bank; | |
407 | __u16 device; | |
408 | __u16 row; | |
409 | __u16 column; | |
410 | __u16 bit_pos; | |
411 | __u64 requestor_id; | |
412 | __u64 responder_id; | |
413 | __u64 target_id; | |
414 | __u8 error_type; | |
415 | }; | |
416 | ||
417 | /* Memory Error Section UEFI >= 2.3 */ | |
06d65dea HY |
418 | struct cper_sec_mem_err { |
419 | __u64 validation_bits; | |
420 | __u64 error_status; | |
421 | __u64 physical_addr; | |
422 | __u64 physical_addr_mask; | |
423 | __u16 node; | |
424 | __u16 card; | |
425 | __u16 module; | |
426 | __u16 bank; | |
427 | __u16 device; | |
428 | __u16 row; | |
429 | __u16 column; | |
430 | __u16 bit_pos; | |
431 | __u64 requestor_id; | |
432 | __u64 responder_id; | |
433 | __u64 target_id; | |
434 | __u8 error_type; | |
147de147 CG |
435 | __u8 reserved; |
436 | __u16 rank; | |
437 | __u16 mem_array_handle; /* card handle in UEFI 2.4 */ | |
438 | __u16 mem_dev_handle; /* module handle in UEFI 2.4 */ | |
06d65dea HY |
439 | }; |
440 | ||
2dfb7d51 CG |
441 | struct cper_mem_err_compact { |
442 | __u64 validation_bits; | |
443 | __u16 node; | |
444 | __u16 card; | |
445 | __u16 module; | |
446 | __u16 bank; | |
447 | __u16 device; | |
448 | __u16 row; | |
449 | __u16 column; | |
450 | __u16 bit_pos; | |
451 | __u64 requestor_id; | |
452 | __u64 responder_id; | |
453 | __u64 target_id; | |
454 | __u16 rank; | |
455 | __u16 mem_array_handle; | |
456 | __u16 mem_dev_handle; | |
457 | }; | |
458 | ||
c9aa308f HY |
459 | struct cper_sec_pcie { |
460 | __u64 validation_bits; | |
461 | __u32 port_type; | |
462 | struct { | |
463 | __u8 minor; | |
464 | __u8 major; | |
465 | __u8 reserved[2]; | |
466 | } version; | |
467 | __u16 command; | |
468 | __u16 status; | |
469 | __u32 reserved; | |
470 | struct { | |
471 | __u16 vendor_id; | |
472 | __u16 device_id; | |
473 | __u8 class_code[3]; | |
474 | __u8 function; | |
475 | __u8 device; | |
476 | __u16 segment; | |
477 | __u8 bus; | |
478 | __u8 secondary_bus; | |
479 | __u16 slot; | |
480 | __u8 reserved; | |
481 | } device_id; | |
482 | struct { | |
483 | __u32 lower; | |
484 | __u32 upper; | |
485 | } serial_number; | |
486 | struct { | |
487 | __u16 secondary_status; | |
488 | __u16 control; | |
489 | } bridge; | |
490 | __u8 capability[60]; | |
491 | __u8 aer_info[96]; | |
492 | }; | |
493 | ||
06d65dea HY |
494 | /* Reset to default packing */ |
495 | #pragma pack() | |
496 | ||
497 | u64 cper_next_record_id(void); | |
3760cd20 CG |
498 | const char *cper_severity_str(unsigned int); |
499 | const char *cper_mem_err_type_str(unsigned int); | |
c413d768 | 500 | void cper_print_bits(const char *prefix, unsigned int bits, |
88f074f4 | 501 | const char * const strs[], unsigned int strs_size); |
2dfb7d51 CG |
502 | void cper_mem_err_pack(const struct cper_sec_mem_err *, |
503 | struct cper_mem_err_compact *); | |
504 | const char *cper_mem_err_unpack(struct trace_seq *, | |
505 | struct cper_mem_err_compact *); | |
06d65dea HY |
506 | |
507 | #endif |