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ad0dfdfd MP |
1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* | |
3 | * Copyright (c) 2012, The Linux Foundation. All rights reserved. | |
a06ae860 PP |
4 | */ |
5 | ||
6 | #ifndef _LINUX_CORESIGHT_H | |
7 | #define _LINUX_CORESIGHT_H | |
8 | ||
9 | #include <linux/device.h> | |
6e736c60 | 10 | #include <linux/io.h> |
882d5e11 | 11 | #include <linux/perf_event.h> |
ff63ec13 | 12 | #include <linux/sched.h> |
a06ae860 PP |
13 | |
14 | /* Peripheral id registers (0xFD0-0xFEC) */ | |
15 | #define CORESIGHT_PERIPHIDR4 0xfd0 | |
16 | #define CORESIGHT_PERIPHIDR5 0xfd4 | |
17 | #define CORESIGHT_PERIPHIDR6 0xfd8 | |
18 | #define CORESIGHT_PERIPHIDR7 0xfdC | |
19 | #define CORESIGHT_PERIPHIDR0 0xfe0 | |
20 | #define CORESIGHT_PERIPHIDR1 0xfe4 | |
21 | #define CORESIGHT_PERIPHIDR2 0xfe8 | |
22 | #define CORESIGHT_PERIPHIDR3 0xfeC | |
23 | /* Component id registers (0xFF0-0xFFC) */ | |
24 | #define CORESIGHT_COMPIDR0 0xff0 | |
25 | #define CORESIGHT_COMPIDR1 0xff4 | |
26 | #define CORESIGHT_COMPIDR2 0xff8 | |
27 | #define CORESIGHT_COMPIDR3 0xffC | |
28 | ||
29 | #define ETM_ARCH_V3_3 0x23 | |
30 | #define ETM_ARCH_V3_5 0x25 | |
31 | #define PFT_ARCH_V1_0 0x30 | |
32 | #define PFT_ARCH_V1_1 0x31 | |
33 | ||
34 | #define CORESIGHT_UNLOCK 0xc5acce55 | |
35 | ||
36 | extern struct bus_type coresight_bustype; | |
37 | ||
38 | enum coresight_dev_type { | |
a06ae860 PP |
39 | CORESIGHT_DEV_TYPE_SINK, |
40 | CORESIGHT_DEV_TYPE_LINK, | |
41 | CORESIGHT_DEV_TYPE_LINKSINK, | |
42 | CORESIGHT_DEV_TYPE_SOURCE, | |
8a091d84 | 43 | CORESIGHT_DEV_TYPE_HELPER, |
1b5b1646 | 44 | CORESIGHT_DEV_TYPE_MAX |
a06ae860 PP |
45 | }; |
46 | ||
47 | enum coresight_dev_subtype_sink { | |
a06ae860 PP |
48 | CORESIGHT_DEV_SUBTYPE_SINK_PORT, |
49 | CORESIGHT_DEV_SUBTYPE_SINK_BUFFER, | |
0336bdfd | 50 | CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM, |
2cd87a7b | 51 | CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM, |
a06ae860 PP |
52 | }; |
53 | ||
54 | enum coresight_dev_subtype_link { | |
a06ae860 PP |
55 | CORESIGHT_DEV_SUBTYPE_LINK_MERG, |
56 | CORESIGHT_DEV_SUBTYPE_LINK_SPLIT, | |
57 | CORESIGHT_DEV_SUBTYPE_LINK_FIFO, | |
58 | }; | |
59 | ||
60 | enum coresight_dev_subtype_source { | |
a06ae860 PP |
61 | CORESIGHT_DEV_SUBTYPE_SOURCE_PROC, |
62 | CORESIGHT_DEV_SUBTYPE_SOURCE_BUS, | |
63 | CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE, | |
b3c71626 | 64 | CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS, |
a06ae860 PP |
65 | }; |
66 | ||
8a091d84 | 67 | enum coresight_dev_subtype_helper { |
fcacb5c1 | 68 | CORESIGHT_DEV_SUBTYPE_HELPER_CATU, |
1b5b1646 | 69 | CORESIGHT_DEV_SUBTYPE_HELPER_ECT_CTI |
835d722b ML |
70 | }; |
71 | ||
a06ae860 | 72 | /** |
00b78e8b | 73 | * union coresight_dev_subtype - further characterisation of a type |
a06ae860 | 74 | * @sink_subtype: type of sink this component is, as defined |
00b78e8b | 75 | * by @coresight_dev_subtype_sink. |
a06ae860 | 76 | * @link_subtype: type of link this component is, as defined |
00b78e8b | 77 | * by @coresight_dev_subtype_link. |
a06ae860 | 78 | * @source_subtype: type of source this component is, as defined |
00b78e8b | 79 | * by @coresight_dev_subtype_source. |
8a091d84 SP |
80 | * @helper_subtype: type of helper this component is, as defined |
81 | * by @coresight_dev_subtype_helper. | |
a06ae860 | 82 | */ |
00b78e8b SP |
83 | union coresight_dev_subtype { |
84 | /* We have some devices which acts as LINK and SINK */ | |
85 | struct { | |
86 | enum coresight_dev_subtype_sink sink_subtype; | |
87 | enum coresight_dev_subtype_link link_subtype; | |
88 | }; | |
a06ae860 | 89 | enum coresight_dev_subtype_source source_subtype; |
8a091d84 | 90 | enum coresight_dev_subtype_helper helper_subtype; |
a06ae860 PP |
91 | }; |
92 | ||
93 | /** | |
d375b356 SP |
94 | * struct coresight_platform_data - data harvested from the firmware |
95 | * specification. | |
96 | * | |
81d0ea76 JC |
97 | * @nr_inconns: Number of elements for the input connections. |
98 | * @nr_outconns: Number of elements for the output connections. | |
4e8fe7e5 JC |
99 | * @out_conns: Array of nr_outconns pointers to connections from this |
100 | * component. | |
e3f4e687 JC |
101 | * @in_conns: Sparse array of pointers to input connections. Sparse |
102 | * because the source device owns the connection so when it's | |
103 | * unloaded the connection leaves an empty slot. | |
a06ae860 PP |
104 | */ |
105 | struct coresight_platform_data { | |
81d0ea76 JC |
106 | int nr_inconns; |
107 | int nr_outconns; | |
4e8fe7e5 | 108 | struct coresight_connection **out_conns; |
e3f4e687 | 109 | struct coresight_connection **in_conns; |
a06ae860 PP |
110 | }; |
111 | ||
6e736c60 SP |
112 | /** |
113 | * struct csdev_access - Abstraction of a CoreSight device access. | |
114 | * | |
115 | * @io_mem : True if the device has memory mapped I/O | |
116 | * @base : When io_mem == true, base address of the component | |
117 | * @read : Read from the given "offset" of the given instance. | |
118 | * @write : Write "val" to the given "offset". | |
119 | */ | |
120 | struct csdev_access { | |
121 | bool io_mem; | |
122 | union { | |
123 | void __iomem *base; | |
124 | struct { | |
125 | u64 (*read)(u32 offset, bool relaxed, bool _64bit); | |
126 | void (*write)(u64 val, u32 offset, bool relaxed, | |
127 | bool _64bit); | |
128 | }; | |
129 | }; | |
130 | }; | |
131 | ||
132 | #define CSDEV_ACCESS_IOMEM(_addr) \ | |
133 | ((struct csdev_access) { \ | |
134 | .io_mem = true, \ | |
135 | .base = (_addr), \ | |
136 | }) | |
137 | ||
a06ae860 PP |
138 | /** |
139 | * struct coresight_desc - description of a component required from drivers | |
140 | * @type: as defined by @coresight_dev_type. | |
141 | * @subtype: as defined by @coresight_dev_subtype. | |
142 | * @ops: generic operations for this component, as defined | |
2ede79a6 | 143 | * by @coresight_ops. |
a06ae860 PP |
144 | * @pdata: platform data collected from DT. |
145 | * @dev: The device entity associated to this component. | |
8ee885a9 | 146 | * @groups: operations specific to this component. These will end up |
2ede79a6 SP |
147 | * in the component's sysfs sub-directory. |
148 | * @name: name for the coresight device, also shown under sysfs. | |
6e736c60 | 149 | * @access: Describe access to the device |
a06ae860 PP |
150 | */ |
151 | struct coresight_desc { | |
152 | enum coresight_dev_type type; | |
00b78e8b | 153 | union coresight_dev_subtype subtype; |
a06ae860 PP |
154 | const struct coresight_ops *ops; |
155 | struct coresight_platform_data *pdata; | |
156 | struct device *dev; | |
157 | const struct attribute_group **groups; | |
2ede79a6 | 158 | const char *name; |
6e736c60 | 159 | struct csdev_access access; |
a06ae860 PP |
160 | }; |
161 | ||
162 | /** | |
163 | * struct coresight_connection - representation of a single connection | |
d49c9cf1 JC |
164 | * @src_port: a connection's output port number. |
165 | * @dest_port: destination's input port number @src_port is connected to. | |
166 | * @dest_fwnode: destination component's fwnode handle. | |
167 | * @dest_dev: a @coresight_device representation of the component | |
168 | connected to @src_port. NULL until the device is created | |
8a7365c2 | 169 | * @link: Representation of the connection as a sysfs link. |
e3f4e687 JC |
170 | * |
171 | * The full connection structure looks like this, where in_conns store | |
172 | * references to same connection as the source device's out_conns. | |
173 | * | |
174 | * +-----------------------------+ +-----------------------------+ | |
175 | * |coresight_device | |coresight_connection | | |
176 | * |-----------------------------| |-----------------------------| | |
177 | * | | | | | |
178 | * | | | dest_dev*|<-- | |
179 | * |pdata->out_conns[nr_outconns]|<->|src_dev* | | | |
180 | * | | | | | | |
181 | * +-----------------------------+ +-----------------------------+ | | |
182 | * | | |
183 | * +-----------------------------+ | | |
184 | * |coresight_device | | | |
185 | * |------------------------------ | | |
186 | * | | | | |
187 | * | pdata->in_conns[nr_inconns]|<-- | |
188 | * | | | |
189 | * +-----------------------------+ | |
a06ae860 PP |
190 | */ |
191 | struct coresight_connection { | |
d49c9cf1 JC |
192 | int src_port; |
193 | int dest_port; | |
194 | struct fwnode_handle *dest_fwnode; | |
195 | struct coresight_device *dest_dev; | |
8a7365c2 | 196 | struct coresight_sysfs_link *link; |
e3f4e687 | 197 | struct coresight_device *src_dev; |
ae7f2b5a JC |
198 | atomic_t src_refcnt; |
199 | atomic_t dest_refcnt; | |
a06ae860 PP |
200 | }; |
201 | ||
80961525 ML |
202 | /** |
203 | * struct coresight_sysfs_link - representation of a connection in sysfs. | |
204 | * @orig: Originating (master) coresight device for the link. | |
205 | * @orig_name: Name to use for the link orig->target. | |
206 | * @target: Target (slave) coresight device for the link. | |
207 | * @target_name: Name to use for the link target->orig. | |
208 | */ | |
209 | struct coresight_sysfs_link { | |
210 | struct coresight_device *orig; | |
211 | const char *orig_name; | |
212 | struct coresight_device *target; | |
213 | const char *target_name; | |
214 | }; | |
215 | ||
a06ae860 PP |
216 | /** |
217 | * struct coresight_device - representation of a device as used by the framework | |
b77e3ed0 | 218 | * @pdata: Platform data with device connections associated to this device. |
a06ae860 PP |
219 | * @type: as defined by @coresight_dev_type. |
220 | * @subtype: as defined by @coresight_dev_subtype. | |
221 | * @ops: generic operations for this component, as defined | |
6e736c60 SP |
222 | * by @coresight_ops. |
223 | * @access: Device i/o access abstraction for this device. | |
a06ae860 PP |
224 | * @dev: The device entity associated to this component. |
225 | * @refcnt: keep track of what is in use. | |
a06ae860 PP |
226 | * @orphan: true if the component has connections that haven't been linked. |
227 | * @enable: 'true' if component is currently part of an active path. | |
228 | * @activated: 'true' only if a _sink_ has been activated. A sink can be | |
bb8e370b | 229 | * activated but not yet enabled. Enabling for a _sink_ |
d061cd73 ML |
230 | * happens when a source has been selected and a path is enabled |
231 | * from source to that sink. | |
bb8e370b | 232 | * @ea: Device attribute for sink representation under PMU directory. |
0336bdfd | 233 | * @def_sink: cached reference to default sink found for this device. |
80961525 ML |
234 | * @nr_links: number of sysfs links created to other components from this |
235 | * device. These will appear in the "connections" group. | |
236 | * @has_conns_grp: Have added a "connections" group for sysfs links. | |
42ff700f ML |
237 | * @feature_csdev_list: List of complex feature programming added to the device. |
238 | * @config_csdev_list: List of system configurations added to the device. | |
239 | * @cscfg_csdev_lock: Protect the lists of configurations and features. | |
f8cce2ff | 240 | * @active_cscfg_ctxt: Context information for current active system configuration. |
a06ae860 PP |
241 | */ |
242 | struct coresight_device { | |
b77e3ed0 | 243 | struct coresight_platform_data *pdata; |
a06ae860 | 244 | enum coresight_dev_type type; |
00b78e8b | 245 | union coresight_dev_subtype subtype; |
a06ae860 | 246 | const struct coresight_ops *ops; |
6e736c60 | 247 | struct csdev_access access; |
a06ae860 | 248 | struct device dev; |
ae7f2b5a | 249 | atomic_t refcnt; |
a06ae860 PP |
250 | bool orphan; |
251 | bool enable; /* true only if configured as part of a path */ | |
bb8e370b | 252 | /* sink specific fields */ |
a06ae860 | 253 | bool activated; /* true only if a sink is part of a path */ |
bb8e370b | 254 | struct dev_ext_attribute *ea; |
0336bdfd | 255 | struct coresight_device *def_sink; |
80961525 ML |
256 | /* sysfs links between components */ |
257 | int nr_links; | |
258 | bool has_conns_grp; | |
42ff700f ML |
259 | /* system configuration and feature lists */ |
260 | struct list_head feature_csdev_list; | |
261 | struct list_head config_csdev_list; | |
262 | spinlock_t cscfg_csdev_lock; | |
f8cce2ff | 263 | void *active_cscfg_ctxt; |
a06ae860 PP |
264 | }; |
265 | ||
0f5f9b6b SP |
266 | /* |
267 | * coresight_dev_list - Mapping for devices to "name" index for device | |
268 | * names. | |
269 | * | |
270 | * @nr_idx: Number of entries already allocated. | |
271 | * @pfx: Prefix pattern for device name. | |
272 | * @fwnode_list: Array of fwnode_handles associated with each allocated | |
273 | * index, upto nr_idx entries. | |
274 | */ | |
275 | struct coresight_dev_list { | |
276 | int nr_idx; | |
277 | const char *pfx; | |
278 | struct fwnode_handle **fwnode_list; | |
279 | }; | |
280 | ||
281 | #define DEFINE_CORESIGHT_DEVLIST(var, dev_pfx) \ | |
282 | static struct coresight_dev_list (var) = { \ | |
283 | .pfx = dev_pfx, \ | |
284 | .nr_idx = 0, \ | |
285 | .fwnode_list = NULL, \ | |
286 | } | |
287 | ||
a06ae860 PP |
288 | #define to_coresight_device(d) container_of(d, struct coresight_device, dev) |
289 | ||
9fa36828 JC |
290 | enum cs_mode { |
291 | CS_MODE_DISABLED, | |
292 | CS_MODE_SYSFS, | |
293 | CS_MODE_PERF, | |
294 | }; | |
295 | ||
a06ae860 PP |
296 | #define source_ops(csdev) csdev->ops->source_ops |
297 | #define sink_ops(csdev) csdev->ops->sink_ops | |
298 | #define link_ops(csdev) csdev->ops->link_ops | |
8a091d84 | 299 | #define helper_ops(csdev) csdev->ops->helper_ops |
835d722b | 300 | #define ect_ops(csdev) csdev->ops->ect_ops |
a06ae860 | 301 | |
a06ae860 PP |
302 | /** |
303 | * struct coresight_ops_sink - basic operations for a sink | |
304 | * Operations available for sinks | |
2997aa40 MP |
305 | * @enable: enables the sink. |
306 | * @disable: disables the sink. | |
307 | * @alloc_buffer: initialises perf's ring buffer for trace collection. | |
308 | * @free_buffer: release memory allocated in @get_config. | |
2997aa40 | 309 | * @update_buffer: update buffer pointers after a trace session. |
a06ae860 PP |
310 | */ |
311 | struct coresight_ops_sink { | |
9fa36828 JC |
312 | int (*enable)(struct coresight_device *csdev, enum cs_mode mode, |
313 | void *data); | |
6c817a95 | 314 | int (*disable)(struct coresight_device *csdev); |
a0f08a6a MP |
315 | void *(*alloc_buffer)(struct coresight_device *csdev, |
316 | struct perf_event *event, void **pages, | |
317 | int nr_pages, bool overwrite); | |
2997aa40 | 318 | void (*free_buffer)(void *config); |
7ec786ad | 319 | unsigned long (*update_buffer)(struct coresight_device *csdev, |
2997aa40 MP |
320 | struct perf_output_handle *handle, |
321 | void *sink_config); | |
a06ae860 PP |
322 | }; |
323 | ||
324 | /** | |
325 | * struct coresight_ops_link - basic operations for a link | |
326 | * Operations available for links. | |
327 | * @enable: enables flow between iport and oport. | |
328 | * @disable: disables flow between iport and oport. | |
329 | */ | |
330 | struct coresight_ops_link { | |
ae7f2b5a JC |
331 | int (*enable)(struct coresight_device *csdev, |
332 | struct coresight_connection *in, | |
333 | struct coresight_connection *out); | |
334 | void (*disable)(struct coresight_device *csdev, | |
335 | struct coresight_connection *in, | |
336 | struct coresight_connection *out); | |
a06ae860 PP |
337 | }; |
338 | ||
339 | /** | |
340 | * struct coresight_ops_source - basic operations for a source | |
341 | * Operations available for sources. | |
52210c87 MP |
342 | * @cpu_id: returns the value of the CPU number this component |
343 | * is associated to. | |
1d27ff5a | 344 | * @enable: enables tracing for a source. |
a06ae860 PP |
345 | * @disable: disables tracing for a source. |
346 | */ | |
347 | struct coresight_ops_source { | |
52210c87 | 348 | int (*cpu_id)(struct coresight_device *csdev); |
9fa36828 JC |
349 | int (*enable)(struct coresight_device *csdev, struct perf_event *event, |
350 | enum cs_mode mode); | |
68905d73 MP |
351 | void (*disable)(struct coresight_device *csdev, |
352 | struct perf_event *event); | |
a06ae860 PP |
353 | }; |
354 | ||
8a091d84 SP |
355 | /** |
356 | * struct coresight_ops_helper - Operations for a helper device. | |
357 | * | |
358 | * All operations could pass in a device specific data, which could | |
359 | * help the helper device to determine what to do. | |
360 | * | |
361 | * @enable : Enable the device | |
362 | * @disable : Disable the device | |
363 | */ | |
364 | struct coresight_ops_helper { | |
61486528 JC |
365 | int (*enable)(struct coresight_device *csdev, enum cs_mode mode, |
366 | void *data); | |
8a091d84 SP |
367 | int (*disable)(struct coresight_device *csdev, void *data); |
368 | }; | |
369 | ||
a06ae860 PP |
370 | struct coresight_ops { |
371 | const struct coresight_ops_sink *sink_ops; | |
372 | const struct coresight_ops_link *link_ops; | |
373 | const struct coresight_ops_source *source_ops; | |
8a091d84 | 374 | const struct coresight_ops_helper *helper_ops; |
a06ae860 PP |
375 | }; |
376 | ||
b8127113 | 377 | #if IS_ENABLED(CONFIG_CORESIGHT) |
6e736c60 SP |
378 | |
379 | static inline u32 csdev_access_relaxed_read32(struct csdev_access *csa, | |
380 | u32 offset) | |
381 | { | |
382 | if (likely(csa->io_mem)) | |
383 | return readl_relaxed(csa->base + offset); | |
384 | ||
385 | return csa->read(offset, true, false); | |
386 | } | |
387 | ||
b6df1cbb | 388 | static inline u64 csdev_access_relaxed_read_pair(struct csdev_access *csa, |
0a98181f | 389 | u32 lo_offset, u32 hi_offset) |
b6df1cbb | 390 | { |
b6df1cbb | 391 | if (likely(csa->io_mem)) { |
0a98181f JC |
392 | return readl_relaxed(csa->base + lo_offset) | |
393 | ((u64)readl_relaxed(csa->base + hi_offset) << 32); | |
b6df1cbb JC |
394 | } |
395 | ||
0a98181f JC |
396 | return csa->read(lo_offset, true, false) | (csa->read(hi_offset, true, false) << 32); |
397 | } | |
398 | ||
399 | static inline void csdev_access_relaxed_write_pair(struct csdev_access *csa, u64 val, | |
400 | u32 lo_offset, u32 hi_offset) | |
401 | { | |
402 | if (likely(csa->io_mem)) { | |
403 | writel_relaxed((u32)val, csa->base + lo_offset); | |
404 | writel_relaxed((u32)(val >> 32), csa->base + hi_offset); | |
405 | } else { | |
406 | csa->write((u32)val, lo_offset, true, false); | |
407 | csa->write((u32)(val >> 32), hi_offset, true, false); | |
408 | } | |
b6df1cbb JC |
409 | } |
410 | ||
6e736c60 SP |
411 | static inline u32 csdev_access_read32(struct csdev_access *csa, u32 offset) |
412 | { | |
413 | if (likely(csa->io_mem)) | |
414 | return readl(csa->base + offset); | |
415 | ||
416 | return csa->read(offset, false, false); | |
417 | } | |
418 | ||
419 | static inline void csdev_access_relaxed_write32(struct csdev_access *csa, | |
420 | u32 val, u32 offset) | |
421 | { | |
422 | if (likely(csa->io_mem)) | |
423 | writel_relaxed(val, csa->base + offset); | |
424 | else | |
425 | csa->write(val, offset, true, false); | |
426 | } | |
427 | ||
428 | static inline void csdev_access_write32(struct csdev_access *csa, u32 val, u32 offset) | |
429 | { | |
430 | if (likely(csa->io_mem)) | |
431 | writel(val, csa->base + offset); | |
432 | else | |
433 | csa->write(val, offset, false, false); | |
434 | } | |
435 | ||
436 | #ifdef CONFIG_64BIT | |
437 | ||
438 | static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa, | |
439 | u32 offset) | |
440 | { | |
441 | if (likely(csa->io_mem)) | |
442 | return readq_relaxed(csa->base + offset); | |
443 | ||
444 | return csa->read(offset, true, true); | |
445 | } | |
446 | ||
447 | static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset) | |
448 | { | |
449 | if (likely(csa->io_mem)) | |
450 | return readq(csa->base + offset); | |
451 | ||
452 | return csa->read(offset, false, true); | |
453 | } | |
454 | ||
455 | static inline void csdev_access_relaxed_write64(struct csdev_access *csa, | |
456 | u64 val, u32 offset) | |
457 | { | |
458 | if (likely(csa->io_mem)) | |
459 | writeq_relaxed(val, csa->base + offset); | |
460 | else | |
461 | csa->write(val, offset, true, true); | |
462 | } | |
463 | ||
464 | static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset) | |
465 | { | |
466 | if (likely(csa->io_mem)) | |
467 | writeq(val, csa->base + offset); | |
468 | else | |
469 | csa->write(val, offset, false, true); | |
470 | } | |
471 | ||
472 | #else /* !CONFIG_64BIT */ | |
473 | ||
474 | static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa, | |
475 | u32 offset) | |
476 | { | |
477 | WARN_ON(1); | |
478 | return 0; | |
479 | } | |
480 | ||
481 | static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset) | |
482 | { | |
483 | WARN_ON(1); | |
484 | return 0; | |
485 | } | |
486 | ||
487 | static inline void csdev_access_relaxed_write64(struct csdev_access *csa, | |
488 | u64 val, u32 offset) | |
489 | { | |
490 | WARN_ON(1); | |
491 | } | |
492 | ||
493 | static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset) | |
494 | { | |
495 | WARN_ON(1); | |
496 | } | |
497 | #endif /* CONFIG_64BIT */ | |
498 | ||
2cd87a7b AK |
499 | static inline bool coresight_is_percpu_source(struct coresight_device *csdev) |
500 | { | |
501 | return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SOURCE) && | |
502 | (csdev->subtype.source_subtype == CORESIGHT_DEV_SUBTYPE_SOURCE_PROC); | |
503 | } | |
504 | ||
505 | static inline bool coresight_is_percpu_sink(struct coresight_device *csdev) | |
506 | { | |
507 | return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SINK) && | |
508 | (csdev->subtype.sink_subtype == CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM); | |
509 | } | |
510 | ||
a06ae860 PP |
511 | extern struct coresight_device * |
512 | coresight_register(struct coresight_desc *desc); | |
513 | extern void coresight_unregister(struct coresight_device *csdev); | |
514 | extern int coresight_enable(struct coresight_device *csdev); | |
515 | extern void coresight_disable(struct coresight_device *csdev); | |
02005282 | 516 | extern int coresight_timeout(struct csdev_access *csa, u32 offset, |
a06ae860 | 517 | int position, int value); |
2478a6ae | 518 | |
8ce00296 SP |
519 | extern int coresight_claim_device(struct coresight_device *csdev); |
520 | extern int coresight_claim_device_unlocked(struct coresight_device *csdev); | |
2478a6ae | 521 | |
8ce00296 SP |
522 | extern void coresight_disclaim_device(struct coresight_device *csdev); |
523 | extern void coresight_disclaim_device_unlocked(struct coresight_device *csdev); | |
0f5f9b6b SP |
524 | extern char *coresight_alloc_device_name(struct coresight_dev_list *devs, |
525 | struct device *dev); | |
f188b5e7 AM |
526 | |
527 | extern bool coresight_loses_context_with_cpu(struct device *dev); | |
6e736c60 SP |
528 | |
529 | u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset); | |
530 | u32 coresight_read32(struct coresight_device *csdev, u32 offset); | |
531 | void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset); | |
532 | void coresight_relaxed_write32(struct coresight_device *csdev, | |
533 | u32 val, u32 offset); | |
534 | u64 coresight_relaxed_read64(struct coresight_device *csdev, u32 offset); | |
535 | u64 coresight_read64(struct coresight_device *csdev, u32 offset); | |
536 | void coresight_relaxed_write64(struct coresight_device *csdev, | |
537 | u64 val, u32 offset); | |
538 | void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset); | |
539 | ||
a06ae860 PP |
540 | #else |
541 | static inline struct coresight_device * | |
542 | coresight_register(struct coresight_desc *desc) { return NULL; } | |
543 | static inline void coresight_unregister(struct coresight_device *csdev) {} | |
544 | static inline int | |
545 | coresight_enable(struct coresight_device *csdev) { return -ENOSYS; } | |
546 | static inline void coresight_disable(struct coresight_device *csdev) {} | |
02005282 SP |
547 | |
548 | static inline int coresight_timeout(struct csdev_access *csa, u32 offset, | |
549 | int position, int value) | |
550 | { | |
551 | return 1; | |
552 | } | |
553 | ||
8ce00296 | 554 | static inline int coresight_claim_device_unlocked(struct coresight_device *csdev) |
2478a6ae SP |
555 | { |
556 | return -EINVAL; | |
557 | } | |
558 | ||
8ce00296 | 559 | static inline int coresight_claim_device(struct coresight_device *csdev) |
2478a6ae SP |
560 | { |
561 | return -EINVAL; | |
562 | } | |
563 | ||
8ce00296 SP |
564 | static inline void coresight_disclaim_device(struct coresight_device *csdev) {} |
565 | static inline void coresight_disclaim_device_unlocked(struct coresight_device *csdev) {} | |
2478a6ae | 566 | |
f188b5e7 AM |
567 | static inline bool coresight_loses_context_with_cpu(struct device *dev) |
568 | { | |
569 | return false; | |
570 | } | |
6e736c60 SP |
571 | |
572 | static inline u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset) | |
573 | { | |
574 | WARN_ON_ONCE(1); | |
575 | return 0; | |
576 | } | |
577 | ||
578 | static inline u32 coresight_read32(struct coresight_device *csdev, u32 offset) | |
579 | { | |
580 | WARN_ON_ONCE(1); | |
581 | return 0; | |
582 | } | |
583 | ||
584 | static inline void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset) | |
585 | { | |
586 | } | |
587 | ||
588 | static inline void coresight_relaxed_write32(struct coresight_device *csdev, | |
589 | u32 val, u32 offset) | |
590 | { | |
591 | } | |
592 | ||
593 | static inline u64 coresight_relaxed_read64(struct coresight_device *csdev, | |
594 | u32 offset) | |
595 | { | |
596 | WARN_ON_ONCE(1); | |
597 | return 0; | |
598 | } | |
599 | ||
600 | static inline u64 coresight_read64(struct coresight_device *csdev, u32 offset) | |
601 | { | |
602 | WARN_ON_ONCE(1); | |
603 | return 0; | |
604 | } | |
605 | ||
606 | static inline void coresight_relaxed_write64(struct coresight_device *csdev, | |
607 | u64 val, u32 offset) | |
608 | { | |
609 | } | |
610 | ||
611 | static inline void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset) | |
612 | { | |
613 | } | |
614 | ||
615 | #endif /* IS_ENABLED(CONFIG_CORESIGHT) */ | |
c61c4b5d | 616 | |
91824db2 | 617 | extern int coresight_get_cpu(struct device *dev); |
a06ae860 | 618 | |
f03631da | 619 | struct coresight_platform_data *coresight_get_platform_data(struct device *dev); |
3d4ff657 JC |
620 | struct coresight_connection * |
621 | coresight_add_out_conn(struct device *dev, | |
622 | struct coresight_platform_data *pdata, | |
623 | const struct coresight_connection *new_conn); | |
e3f4e687 | 624 | int coresight_add_in_conn(struct coresight_connection *conn); |
61486528 JC |
625 | struct coresight_device * |
626 | coresight_find_input_type(struct coresight_platform_data *pdata, | |
627 | enum coresight_dev_type type, | |
628 | union coresight_dev_subtype subtype); | |
629 | struct coresight_device * | |
630 | coresight_find_output_type(struct coresight_platform_data *pdata, | |
631 | enum coresight_dev_type type, | |
632 | union coresight_dev_subtype subtype); | |
f03631da | 633 | |
6e736c60 | 634 | #endif /* _LINUX_COREISGHT_H */ |