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ad0dfdfd MP |
1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* | |
3 | * Copyright (c) 2012, The Linux Foundation. All rights reserved. | |
a06ae860 PP |
4 | */ |
5 | ||
6 | #ifndef _LINUX_CORESIGHT_H | |
7 | #define _LINUX_CORESIGHT_H | |
8 | ||
9 | #include <linux/device.h> | |
6e736c60 | 10 | #include <linux/io.h> |
882d5e11 | 11 | #include <linux/perf_event.h> |
ff63ec13 | 12 | #include <linux/sched.h> |
a06ae860 PP |
13 | |
14 | /* Peripheral id registers (0xFD0-0xFEC) */ | |
15 | #define CORESIGHT_PERIPHIDR4 0xfd0 | |
16 | #define CORESIGHT_PERIPHIDR5 0xfd4 | |
17 | #define CORESIGHT_PERIPHIDR6 0xfd8 | |
18 | #define CORESIGHT_PERIPHIDR7 0xfdC | |
19 | #define CORESIGHT_PERIPHIDR0 0xfe0 | |
20 | #define CORESIGHT_PERIPHIDR1 0xfe4 | |
21 | #define CORESIGHT_PERIPHIDR2 0xfe8 | |
22 | #define CORESIGHT_PERIPHIDR3 0xfeC | |
23 | /* Component id registers (0xFF0-0xFFC) */ | |
24 | #define CORESIGHT_COMPIDR0 0xff0 | |
25 | #define CORESIGHT_COMPIDR1 0xff4 | |
26 | #define CORESIGHT_COMPIDR2 0xff8 | |
27 | #define CORESIGHT_COMPIDR3 0xffC | |
28 | ||
29 | #define ETM_ARCH_V3_3 0x23 | |
30 | #define ETM_ARCH_V3_5 0x25 | |
31 | #define PFT_ARCH_V1_0 0x30 | |
32 | #define PFT_ARCH_V1_1 0x31 | |
33 | ||
34 | #define CORESIGHT_UNLOCK 0xc5acce55 | |
35 | ||
36 | extern struct bus_type coresight_bustype; | |
37 | ||
38 | enum coresight_dev_type { | |
a06ae860 PP |
39 | CORESIGHT_DEV_TYPE_SINK, |
40 | CORESIGHT_DEV_TYPE_LINK, | |
41 | CORESIGHT_DEV_TYPE_LINKSINK, | |
42 | CORESIGHT_DEV_TYPE_SOURCE, | |
8a091d84 | 43 | CORESIGHT_DEV_TYPE_HELPER, |
835d722b | 44 | CORESIGHT_DEV_TYPE_ECT, |
a06ae860 PP |
45 | }; |
46 | ||
47 | enum coresight_dev_subtype_sink { | |
a06ae860 PP |
48 | CORESIGHT_DEV_SUBTYPE_SINK_PORT, |
49 | CORESIGHT_DEV_SUBTYPE_SINK_BUFFER, | |
0336bdfd | 50 | CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM, |
2cd87a7b | 51 | CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM, |
a06ae860 PP |
52 | }; |
53 | ||
54 | enum coresight_dev_subtype_link { | |
a06ae860 PP |
55 | CORESIGHT_DEV_SUBTYPE_LINK_MERG, |
56 | CORESIGHT_DEV_SUBTYPE_LINK_SPLIT, | |
57 | CORESIGHT_DEV_SUBTYPE_LINK_FIFO, | |
58 | }; | |
59 | ||
60 | enum coresight_dev_subtype_source { | |
a06ae860 PP |
61 | CORESIGHT_DEV_SUBTYPE_SOURCE_PROC, |
62 | CORESIGHT_DEV_SUBTYPE_SOURCE_BUS, | |
63 | CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE, | |
b3c71626 | 64 | CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS, |
a06ae860 PP |
65 | }; |
66 | ||
8a091d84 | 67 | enum coresight_dev_subtype_helper { |
fcacb5c1 | 68 | CORESIGHT_DEV_SUBTYPE_HELPER_CATU, |
8a091d84 SP |
69 | }; |
70 | ||
835d722b ML |
71 | /* Embedded Cross Trigger (ECT) sub-types */ |
72 | enum coresight_dev_subtype_ect { | |
73 | CORESIGHT_DEV_SUBTYPE_ECT_NONE, | |
74 | CORESIGHT_DEV_SUBTYPE_ECT_CTI, | |
75 | }; | |
76 | ||
a06ae860 | 77 | /** |
00b78e8b | 78 | * union coresight_dev_subtype - further characterisation of a type |
a06ae860 | 79 | * @sink_subtype: type of sink this component is, as defined |
00b78e8b | 80 | * by @coresight_dev_subtype_sink. |
a06ae860 | 81 | * @link_subtype: type of link this component is, as defined |
00b78e8b | 82 | * by @coresight_dev_subtype_link. |
a06ae860 | 83 | * @source_subtype: type of source this component is, as defined |
00b78e8b | 84 | * by @coresight_dev_subtype_source. |
8a091d84 SP |
85 | * @helper_subtype: type of helper this component is, as defined |
86 | * by @coresight_dev_subtype_helper. | |
835d722b ML |
87 | * @ect_subtype: type of cross trigger this component is, as |
88 | * defined by @coresight_dev_subtype_ect | |
a06ae860 | 89 | */ |
00b78e8b SP |
90 | union coresight_dev_subtype { |
91 | /* We have some devices which acts as LINK and SINK */ | |
92 | struct { | |
93 | enum coresight_dev_subtype_sink sink_subtype; | |
94 | enum coresight_dev_subtype_link link_subtype; | |
95 | }; | |
a06ae860 | 96 | enum coresight_dev_subtype_source source_subtype; |
8a091d84 | 97 | enum coresight_dev_subtype_helper helper_subtype; |
835d722b | 98 | enum coresight_dev_subtype_ect ect_subtype; |
a06ae860 PP |
99 | }; |
100 | ||
101 | /** | |
d375b356 SP |
102 | * struct coresight_platform_data - data harvested from the firmware |
103 | * specification. | |
104 | * | |
81d0ea76 JC |
105 | * @nr_inconns: Number of elements for the input connections. |
106 | * @nr_outconns: Number of elements for the output connections. | |
3d4ff657 | 107 | * @out_conns: Array of nr_outconns connections from this component. |
a06ae860 PP |
108 | */ |
109 | struct coresight_platform_data { | |
3d4ff657 JC |
110 | int high_inport; |
111 | int high_outport; | |
81d0ea76 JC |
112 | int nr_inconns; |
113 | int nr_outconns; | |
704faaf4 | 114 | struct coresight_connection *out_conns; |
a06ae860 PP |
115 | }; |
116 | ||
6e736c60 SP |
117 | /** |
118 | * struct csdev_access - Abstraction of a CoreSight device access. | |
119 | * | |
120 | * @io_mem : True if the device has memory mapped I/O | |
121 | * @base : When io_mem == true, base address of the component | |
122 | * @read : Read from the given "offset" of the given instance. | |
123 | * @write : Write "val" to the given "offset". | |
124 | */ | |
125 | struct csdev_access { | |
126 | bool io_mem; | |
127 | union { | |
128 | void __iomem *base; | |
129 | struct { | |
130 | u64 (*read)(u32 offset, bool relaxed, bool _64bit); | |
131 | void (*write)(u64 val, u32 offset, bool relaxed, | |
132 | bool _64bit); | |
133 | }; | |
134 | }; | |
135 | }; | |
136 | ||
137 | #define CSDEV_ACCESS_IOMEM(_addr) \ | |
138 | ((struct csdev_access) { \ | |
139 | .io_mem = true, \ | |
140 | .base = (_addr), \ | |
141 | }) | |
142 | ||
a06ae860 PP |
143 | /** |
144 | * struct coresight_desc - description of a component required from drivers | |
145 | * @type: as defined by @coresight_dev_type. | |
146 | * @subtype: as defined by @coresight_dev_subtype. | |
147 | * @ops: generic operations for this component, as defined | |
2ede79a6 | 148 | * by @coresight_ops. |
a06ae860 PP |
149 | * @pdata: platform data collected from DT. |
150 | * @dev: The device entity associated to this component. | |
8ee885a9 | 151 | * @groups: operations specific to this component. These will end up |
2ede79a6 SP |
152 | * in the component's sysfs sub-directory. |
153 | * @name: name for the coresight device, also shown under sysfs. | |
6e736c60 | 154 | * @access: Describe access to the device |
a06ae860 PP |
155 | */ |
156 | struct coresight_desc { | |
157 | enum coresight_dev_type type; | |
00b78e8b | 158 | union coresight_dev_subtype subtype; |
a06ae860 PP |
159 | const struct coresight_ops *ops; |
160 | struct coresight_platform_data *pdata; | |
161 | struct device *dev; | |
162 | const struct attribute_group **groups; | |
2ede79a6 | 163 | const char *name; |
6e736c60 | 164 | struct csdev_access access; |
a06ae860 PP |
165 | }; |
166 | ||
167 | /** | |
168 | * struct coresight_connection - representation of a single connection | |
d49c9cf1 JC |
169 | * @src_port: a connection's output port number. |
170 | * @dest_port: destination's input port number @src_port is connected to. | |
171 | * @dest_fwnode: destination component's fwnode handle. | |
172 | * @dest_dev: a @coresight_device representation of the component | |
173 | connected to @src_port. NULL until the device is created | |
8a7365c2 | 174 | * @link: Representation of the connection as a sysfs link. |
a06ae860 PP |
175 | */ |
176 | struct coresight_connection { | |
d49c9cf1 JC |
177 | int src_port; |
178 | int dest_port; | |
179 | struct fwnode_handle *dest_fwnode; | |
180 | struct coresight_device *dest_dev; | |
8a7365c2 | 181 | struct coresight_sysfs_link *link; |
a06ae860 PP |
182 | }; |
183 | ||
80961525 ML |
184 | /** |
185 | * struct coresight_sysfs_link - representation of a connection in sysfs. | |
186 | * @orig: Originating (master) coresight device for the link. | |
187 | * @orig_name: Name to use for the link orig->target. | |
188 | * @target: Target (slave) coresight device for the link. | |
189 | * @target_name: Name to use for the link target->orig. | |
190 | */ | |
191 | struct coresight_sysfs_link { | |
192 | struct coresight_device *orig; | |
193 | const char *orig_name; | |
194 | struct coresight_device *target; | |
195 | const char *target_name; | |
196 | }; | |
197 | ||
a06ae860 PP |
198 | /** |
199 | * struct coresight_device - representation of a device as used by the framework | |
b77e3ed0 | 200 | * @pdata: Platform data with device connections associated to this device. |
a06ae860 PP |
201 | * @type: as defined by @coresight_dev_type. |
202 | * @subtype: as defined by @coresight_dev_subtype. | |
203 | * @ops: generic operations for this component, as defined | |
6e736c60 SP |
204 | * by @coresight_ops. |
205 | * @access: Device i/o access abstraction for this device. | |
a06ae860 PP |
206 | * @dev: The device entity associated to this component. |
207 | * @refcnt: keep track of what is in use. | |
a06ae860 PP |
208 | * @orphan: true if the component has connections that haven't been linked. |
209 | * @enable: 'true' if component is currently part of an active path. | |
210 | * @activated: 'true' only if a _sink_ has been activated. A sink can be | |
bb8e370b | 211 | * activated but not yet enabled. Enabling for a _sink_ |
d061cd73 ML |
212 | * happens when a source has been selected and a path is enabled |
213 | * from source to that sink. | |
bb8e370b | 214 | * @ea: Device attribute for sink representation under PMU directory. |
0336bdfd | 215 | * @def_sink: cached reference to default sink found for this device. |
177af828 ML |
216 | * @ect_dev: Associated cross trigger device. Not part of the trace data |
217 | * path or connections. | |
80961525 ML |
218 | * @nr_links: number of sysfs links created to other components from this |
219 | * device. These will appear in the "connections" group. | |
220 | * @has_conns_grp: Have added a "connections" group for sysfs links. | |
42ff700f ML |
221 | * @feature_csdev_list: List of complex feature programming added to the device. |
222 | * @config_csdev_list: List of system configurations added to the device. | |
223 | * @cscfg_csdev_lock: Protect the lists of configurations and features. | |
f8cce2ff | 224 | * @active_cscfg_ctxt: Context information for current active system configuration. |
a06ae860 PP |
225 | */ |
226 | struct coresight_device { | |
b77e3ed0 | 227 | struct coresight_platform_data *pdata; |
a06ae860 | 228 | enum coresight_dev_type type; |
00b78e8b | 229 | union coresight_dev_subtype subtype; |
a06ae860 | 230 | const struct coresight_ops *ops; |
6e736c60 | 231 | struct csdev_access access; |
a06ae860 PP |
232 | struct device dev; |
233 | atomic_t *refcnt; | |
a06ae860 PP |
234 | bool orphan; |
235 | bool enable; /* true only if configured as part of a path */ | |
bb8e370b | 236 | /* sink specific fields */ |
a06ae860 | 237 | bool activated; /* true only if a sink is part of a path */ |
bb8e370b | 238 | struct dev_ext_attribute *ea; |
0336bdfd | 239 | struct coresight_device *def_sink; |
177af828 ML |
240 | /* cross trigger handling */ |
241 | struct coresight_device *ect_dev; | |
80961525 ML |
242 | /* sysfs links between components */ |
243 | int nr_links; | |
244 | bool has_conns_grp; | |
f2ccc7b7 | 245 | bool ect_enabled; /* true only if associated ect device is enabled */ |
42ff700f ML |
246 | /* system configuration and feature lists */ |
247 | struct list_head feature_csdev_list; | |
248 | struct list_head config_csdev_list; | |
249 | spinlock_t cscfg_csdev_lock; | |
f8cce2ff | 250 | void *active_cscfg_ctxt; |
a06ae860 PP |
251 | }; |
252 | ||
0f5f9b6b SP |
253 | /* |
254 | * coresight_dev_list - Mapping for devices to "name" index for device | |
255 | * names. | |
256 | * | |
257 | * @nr_idx: Number of entries already allocated. | |
258 | * @pfx: Prefix pattern for device name. | |
259 | * @fwnode_list: Array of fwnode_handles associated with each allocated | |
260 | * index, upto nr_idx entries. | |
261 | */ | |
262 | struct coresight_dev_list { | |
263 | int nr_idx; | |
264 | const char *pfx; | |
265 | struct fwnode_handle **fwnode_list; | |
266 | }; | |
267 | ||
268 | #define DEFINE_CORESIGHT_DEVLIST(var, dev_pfx) \ | |
269 | static struct coresight_dev_list (var) = { \ | |
270 | .pfx = dev_pfx, \ | |
271 | .nr_idx = 0, \ | |
272 | .fwnode_list = NULL, \ | |
273 | } | |
274 | ||
a06ae860 PP |
275 | #define to_coresight_device(d) container_of(d, struct coresight_device, dev) |
276 | ||
9fa36828 JC |
277 | enum cs_mode { |
278 | CS_MODE_DISABLED, | |
279 | CS_MODE_SYSFS, | |
280 | CS_MODE_PERF, | |
281 | }; | |
282 | ||
a06ae860 PP |
283 | #define source_ops(csdev) csdev->ops->source_ops |
284 | #define sink_ops(csdev) csdev->ops->sink_ops | |
285 | #define link_ops(csdev) csdev->ops->link_ops | |
8a091d84 | 286 | #define helper_ops(csdev) csdev->ops->helper_ops |
835d722b | 287 | #define ect_ops(csdev) csdev->ops->ect_ops |
a06ae860 | 288 | |
a06ae860 PP |
289 | /** |
290 | * struct coresight_ops_sink - basic operations for a sink | |
291 | * Operations available for sinks | |
2997aa40 MP |
292 | * @enable: enables the sink. |
293 | * @disable: disables the sink. | |
294 | * @alloc_buffer: initialises perf's ring buffer for trace collection. | |
295 | * @free_buffer: release memory allocated in @get_config. | |
2997aa40 | 296 | * @update_buffer: update buffer pointers after a trace session. |
a06ae860 PP |
297 | */ |
298 | struct coresight_ops_sink { | |
9fa36828 JC |
299 | int (*enable)(struct coresight_device *csdev, enum cs_mode mode, |
300 | void *data); | |
6c817a95 | 301 | int (*disable)(struct coresight_device *csdev); |
a0f08a6a MP |
302 | void *(*alloc_buffer)(struct coresight_device *csdev, |
303 | struct perf_event *event, void **pages, | |
304 | int nr_pages, bool overwrite); | |
2997aa40 | 305 | void (*free_buffer)(void *config); |
7ec786ad | 306 | unsigned long (*update_buffer)(struct coresight_device *csdev, |
2997aa40 MP |
307 | struct perf_output_handle *handle, |
308 | void *sink_config); | |
a06ae860 PP |
309 | }; |
310 | ||
311 | /** | |
312 | * struct coresight_ops_link - basic operations for a link | |
313 | * Operations available for links. | |
314 | * @enable: enables flow between iport and oport. | |
315 | * @disable: disables flow between iport and oport. | |
316 | */ | |
317 | struct coresight_ops_link { | |
318 | int (*enable)(struct coresight_device *csdev, int iport, int oport); | |
319 | void (*disable)(struct coresight_device *csdev, int iport, int oport); | |
320 | }; | |
321 | ||
322 | /** | |
323 | * struct coresight_ops_source - basic operations for a source | |
324 | * Operations available for sources. | |
52210c87 MP |
325 | * @cpu_id: returns the value of the CPU number this component |
326 | * is associated to. | |
1d27ff5a | 327 | * @enable: enables tracing for a source. |
a06ae860 PP |
328 | * @disable: disables tracing for a source. |
329 | */ | |
330 | struct coresight_ops_source { | |
52210c87 | 331 | int (*cpu_id)(struct coresight_device *csdev); |
9fa36828 JC |
332 | int (*enable)(struct coresight_device *csdev, struct perf_event *event, |
333 | enum cs_mode mode); | |
68905d73 MP |
334 | void (*disable)(struct coresight_device *csdev, |
335 | struct perf_event *event); | |
a06ae860 PP |
336 | }; |
337 | ||
8a091d84 SP |
338 | /** |
339 | * struct coresight_ops_helper - Operations for a helper device. | |
340 | * | |
341 | * All operations could pass in a device specific data, which could | |
342 | * help the helper device to determine what to do. | |
343 | * | |
344 | * @enable : Enable the device | |
345 | * @disable : Disable the device | |
346 | */ | |
347 | struct coresight_ops_helper { | |
348 | int (*enable)(struct coresight_device *csdev, void *data); | |
349 | int (*disable)(struct coresight_device *csdev, void *data); | |
350 | }; | |
351 | ||
835d722b ML |
352 | /** |
353 | * struct coresight_ops_ect - Ops for an embedded cross trigger device | |
354 | * | |
355 | * @enable : Enable the device | |
356 | * @disable : Disable the device | |
357 | */ | |
358 | struct coresight_ops_ect { | |
359 | int (*enable)(struct coresight_device *csdev); | |
360 | int (*disable)(struct coresight_device *csdev); | |
361 | }; | |
362 | ||
a06ae860 PP |
363 | struct coresight_ops { |
364 | const struct coresight_ops_sink *sink_ops; | |
365 | const struct coresight_ops_link *link_ops; | |
366 | const struct coresight_ops_source *source_ops; | |
8a091d84 | 367 | const struct coresight_ops_helper *helper_ops; |
835d722b | 368 | const struct coresight_ops_ect *ect_ops; |
a06ae860 PP |
369 | }; |
370 | ||
b8127113 | 371 | #if IS_ENABLED(CONFIG_CORESIGHT) |
6e736c60 SP |
372 | |
373 | static inline u32 csdev_access_relaxed_read32(struct csdev_access *csa, | |
374 | u32 offset) | |
375 | { | |
376 | if (likely(csa->io_mem)) | |
377 | return readl_relaxed(csa->base + offset); | |
378 | ||
379 | return csa->read(offset, true, false); | |
380 | } | |
381 | ||
b6df1cbb | 382 | static inline u64 csdev_access_relaxed_read_pair(struct csdev_access *csa, |
0a98181f | 383 | u32 lo_offset, u32 hi_offset) |
b6df1cbb | 384 | { |
b6df1cbb | 385 | if (likely(csa->io_mem)) { |
0a98181f JC |
386 | return readl_relaxed(csa->base + lo_offset) | |
387 | ((u64)readl_relaxed(csa->base + hi_offset) << 32); | |
b6df1cbb JC |
388 | } |
389 | ||
0a98181f JC |
390 | return csa->read(lo_offset, true, false) | (csa->read(hi_offset, true, false) << 32); |
391 | } | |
392 | ||
393 | static inline void csdev_access_relaxed_write_pair(struct csdev_access *csa, u64 val, | |
394 | u32 lo_offset, u32 hi_offset) | |
395 | { | |
396 | if (likely(csa->io_mem)) { | |
397 | writel_relaxed((u32)val, csa->base + lo_offset); | |
398 | writel_relaxed((u32)(val >> 32), csa->base + hi_offset); | |
399 | } else { | |
400 | csa->write((u32)val, lo_offset, true, false); | |
401 | csa->write((u32)(val >> 32), hi_offset, true, false); | |
402 | } | |
b6df1cbb JC |
403 | } |
404 | ||
6e736c60 SP |
405 | static inline u32 csdev_access_read32(struct csdev_access *csa, u32 offset) |
406 | { | |
407 | if (likely(csa->io_mem)) | |
408 | return readl(csa->base + offset); | |
409 | ||
410 | return csa->read(offset, false, false); | |
411 | } | |
412 | ||
413 | static inline void csdev_access_relaxed_write32(struct csdev_access *csa, | |
414 | u32 val, u32 offset) | |
415 | { | |
416 | if (likely(csa->io_mem)) | |
417 | writel_relaxed(val, csa->base + offset); | |
418 | else | |
419 | csa->write(val, offset, true, false); | |
420 | } | |
421 | ||
422 | static inline void csdev_access_write32(struct csdev_access *csa, u32 val, u32 offset) | |
423 | { | |
424 | if (likely(csa->io_mem)) | |
425 | writel(val, csa->base + offset); | |
426 | else | |
427 | csa->write(val, offset, false, false); | |
428 | } | |
429 | ||
430 | #ifdef CONFIG_64BIT | |
431 | ||
432 | static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa, | |
433 | u32 offset) | |
434 | { | |
435 | if (likely(csa->io_mem)) | |
436 | return readq_relaxed(csa->base + offset); | |
437 | ||
438 | return csa->read(offset, true, true); | |
439 | } | |
440 | ||
441 | static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset) | |
442 | { | |
443 | if (likely(csa->io_mem)) | |
444 | return readq(csa->base + offset); | |
445 | ||
446 | return csa->read(offset, false, true); | |
447 | } | |
448 | ||
449 | static inline void csdev_access_relaxed_write64(struct csdev_access *csa, | |
450 | u64 val, u32 offset) | |
451 | { | |
452 | if (likely(csa->io_mem)) | |
453 | writeq_relaxed(val, csa->base + offset); | |
454 | else | |
455 | csa->write(val, offset, true, true); | |
456 | } | |
457 | ||
458 | static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset) | |
459 | { | |
460 | if (likely(csa->io_mem)) | |
461 | writeq(val, csa->base + offset); | |
462 | else | |
463 | csa->write(val, offset, false, true); | |
464 | } | |
465 | ||
466 | #else /* !CONFIG_64BIT */ | |
467 | ||
468 | static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa, | |
469 | u32 offset) | |
470 | { | |
471 | WARN_ON(1); | |
472 | return 0; | |
473 | } | |
474 | ||
475 | static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset) | |
476 | { | |
477 | WARN_ON(1); | |
478 | return 0; | |
479 | } | |
480 | ||
481 | static inline void csdev_access_relaxed_write64(struct csdev_access *csa, | |
482 | u64 val, u32 offset) | |
483 | { | |
484 | WARN_ON(1); | |
485 | } | |
486 | ||
487 | static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset) | |
488 | { | |
489 | WARN_ON(1); | |
490 | } | |
491 | #endif /* CONFIG_64BIT */ | |
492 | ||
2cd87a7b AK |
493 | static inline bool coresight_is_percpu_source(struct coresight_device *csdev) |
494 | { | |
495 | return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SOURCE) && | |
496 | (csdev->subtype.source_subtype == CORESIGHT_DEV_SUBTYPE_SOURCE_PROC); | |
497 | } | |
498 | ||
499 | static inline bool coresight_is_percpu_sink(struct coresight_device *csdev) | |
500 | { | |
501 | return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SINK) && | |
502 | (csdev->subtype.sink_subtype == CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM); | |
503 | } | |
504 | ||
a06ae860 PP |
505 | extern struct coresight_device * |
506 | coresight_register(struct coresight_desc *desc); | |
507 | extern void coresight_unregister(struct coresight_device *csdev); | |
508 | extern int coresight_enable(struct coresight_device *csdev); | |
509 | extern void coresight_disable(struct coresight_device *csdev); | |
02005282 | 510 | extern int coresight_timeout(struct csdev_access *csa, u32 offset, |
a06ae860 | 511 | int position, int value); |
2478a6ae | 512 | |
8ce00296 SP |
513 | extern int coresight_claim_device(struct coresight_device *csdev); |
514 | extern int coresight_claim_device_unlocked(struct coresight_device *csdev); | |
2478a6ae | 515 | |
8ce00296 SP |
516 | extern void coresight_disclaim_device(struct coresight_device *csdev); |
517 | extern void coresight_disclaim_device_unlocked(struct coresight_device *csdev); | |
0f5f9b6b SP |
518 | extern char *coresight_alloc_device_name(struct coresight_dev_list *devs, |
519 | struct device *dev); | |
f188b5e7 AM |
520 | |
521 | extern bool coresight_loses_context_with_cpu(struct device *dev); | |
6e736c60 SP |
522 | |
523 | u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset); | |
524 | u32 coresight_read32(struct coresight_device *csdev, u32 offset); | |
525 | void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset); | |
526 | void coresight_relaxed_write32(struct coresight_device *csdev, | |
527 | u32 val, u32 offset); | |
528 | u64 coresight_relaxed_read64(struct coresight_device *csdev, u32 offset); | |
529 | u64 coresight_read64(struct coresight_device *csdev, u32 offset); | |
530 | void coresight_relaxed_write64(struct coresight_device *csdev, | |
531 | u64 val, u32 offset); | |
532 | void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset); | |
533 | ||
a06ae860 PP |
534 | #else |
535 | static inline struct coresight_device * | |
536 | coresight_register(struct coresight_desc *desc) { return NULL; } | |
537 | static inline void coresight_unregister(struct coresight_device *csdev) {} | |
538 | static inline int | |
539 | coresight_enable(struct coresight_device *csdev) { return -ENOSYS; } | |
540 | static inline void coresight_disable(struct coresight_device *csdev) {} | |
02005282 SP |
541 | |
542 | static inline int coresight_timeout(struct csdev_access *csa, u32 offset, | |
543 | int position, int value) | |
544 | { | |
545 | return 1; | |
546 | } | |
547 | ||
8ce00296 | 548 | static inline int coresight_claim_device_unlocked(struct coresight_device *csdev) |
2478a6ae SP |
549 | { |
550 | return -EINVAL; | |
551 | } | |
552 | ||
8ce00296 | 553 | static inline int coresight_claim_device(struct coresight_device *csdev) |
2478a6ae SP |
554 | { |
555 | return -EINVAL; | |
556 | } | |
557 | ||
8ce00296 SP |
558 | static inline void coresight_disclaim_device(struct coresight_device *csdev) {} |
559 | static inline void coresight_disclaim_device_unlocked(struct coresight_device *csdev) {} | |
2478a6ae | 560 | |
f188b5e7 AM |
561 | static inline bool coresight_loses_context_with_cpu(struct device *dev) |
562 | { | |
563 | return false; | |
564 | } | |
6e736c60 SP |
565 | |
566 | static inline u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset) | |
567 | { | |
568 | WARN_ON_ONCE(1); | |
569 | return 0; | |
570 | } | |
571 | ||
572 | static inline u32 coresight_read32(struct coresight_device *csdev, u32 offset) | |
573 | { | |
574 | WARN_ON_ONCE(1); | |
575 | return 0; | |
576 | } | |
577 | ||
578 | static inline void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset) | |
579 | { | |
580 | } | |
581 | ||
582 | static inline void coresight_relaxed_write32(struct coresight_device *csdev, | |
583 | u32 val, u32 offset) | |
584 | { | |
585 | } | |
586 | ||
587 | static inline u64 coresight_relaxed_read64(struct coresight_device *csdev, | |
588 | u32 offset) | |
589 | { | |
590 | WARN_ON_ONCE(1); | |
591 | return 0; | |
592 | } | |
593 | ||
594 | static inline u64 coresight_read64(struct coresight_device *csdev, u32 offset) | |
595 | { | |
596 | WARN_ON_ONCE(1); | |
597 | return 0; | |
598 | } | |
599 | ||
600 | static inline void coresight_relaxed_write64(struct coresight_device *csdev, | |
601 | u64 val, u32 offset) | |
602 | { | |
603 | } | |
604 | ||
605 | static inline void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset) | |
606 | { | |
607 | } | |
608 | ||
609 | #endif /* IS_ENABLED(CONFIG_CORESIGHT) */ | |
c61c4b5d | 610 | |
91824db2 | 611 | extern int coresight_get_cpu(struct device *dev); |
a06ae860 | 612 | |
f03631da | 613 | struct coresight_platform_data *coresight_get_platform_data(struct device *dev); |
3d4ff657 JC |
614 | struct coresight_connection * |
615 | coresight_add_out_conn(struct device *dev, | |
616 | struct coresight_platform_data *pdata, | |
617 | const struct coresight_connection *new_conn); | |
f03631da | 618 | |
6e736c60 | 619 | #endif /* _LINUX_COREISGHT_H */ |