[linux-2.6-block.git] / include / linux / coresight.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2012, The Linux Foundation. All rights reserved.
 */

#ifndef _LINUX_CORESIGHT_H
#define _LINUX_CORESIGHT_H

#include <linux/device.h>
#include <linux/perf_event.h>
#include <linux/sched.h>

/* Peripheral id registers (0xFD0-0xFEC) */
#define CORESIGHT_PERIPHIDR4	0xfd0
#define CORESIGHT_PERIPHIDR5	0xfd4
#define CORESIGHT_PERIPHIDR6	0xfd8
#define CORESIGHT_PERIPHIDR7	0xfdC
#define CORESIGHT_PERIPHIDR0	0xfe0
#define CORESIGHT_PERIPHIDR1	0xfe4
#define CORESIGHT_PERIPHIDR2	0xfe8
#define CORESIGHT_PERIPHIDR3	0xfeC
/* Component id registers (0xFF0-0xFFC) */
#define CORESIGHT_COMPIDR0	0xff0
#define CORESIGHT_COMPIDR1	0xff4
#define CORESIGHT_COMPIDR2	0xff8
#define CORESIGHT_COMPIDR3	0xffC

#define ETM_ARCH_V3_3		0x23
#define ETM_ARCH_V3_5		0x25
#define PFT_ARCH_V1_0		0x30
#define PFT_ARCH_V1_1		0x31

#define CORESIGHT_UNLOCK	0xc5acce55

extern struct bus_type coresight_bustype;

enum coresight_dev_type {
	CORESIGHT_DEV_TYPE_NONE,
	CORESIGHT_DEV_TYPE_SINK,
	CORESIGHT_DEV_TYPE_LINK,
	CORESIGHT_DEV_TYPE_LINKSINK,
	CORESIGHT_DEV_TYPE_SOURCE,
	CORESIGHT_DEV_TYPE_HELPER,
};

enum coresight_dev_subtype_sink {
	CORESIGHT_DEV_SUBTYPE_SINK_NONE,
	CORESIGHT_DEV_SUBTYPE_SINK_PORT,
	CORESIGHT_DEV_SUBTYPE_SINK_BUFFER,
};

enum coresight_dev_subtype_link {
	CORESIGHT_DEV_SUBTYPE_LINK_NONE,
	CORESIGHT_DEV_SUBTYPE_LINK_MERG,
	CORESIGHT_DEV_SUBTYPE_LINK_SPLIT,
	CORESIGHT_DEV_SUBTYPE_LINK_FIFO,
};

enum coresight_dev_subtype_source {
	CORESIGHT_DEV_SUBTYPE_SOURCE_NONE,
	CORESIGHT_DEV_SUBTYPE_SOURCE_PROC,
	CORESIGHT_DEV_SUBTYPE_SOURCE_BUS,
	CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE,
};

enum coresight_dev_subtype_helper {
	CORESIGHT_DEV_SUBTYPE_HELPER_NONE,
	CORESIGHT_DEV_SUBTYPE_HELPER_CATU,
};

/**
 * union coresight_dev_subtype - further characterisation of a type
 * @sink_subtype:	type of sink this component is, as defined
 *			by @coresight_dev_subtype_sink.
 * @link_subtype:	type of link this component is, as defined
 *			by @coresight_dev_subtype_link.
 * @source_subtype:	type of source this component is, as defined
 *			by @coresight_dev_subtype_source.
 * @helper_subtype:	type of helper this component is, as defined
 *			by @coresight_dev_subtype_helper.
 */
union coresight_dev_subtype {
	/* We have some devices which acts as LINK and SINK */
	struct {
		enum coresight_dev_subtype_sink sink_subtype;
		enum coresight_dev_subtype_link link_subtype;
	};
	enum coresight_dev_subtype_source source_subtype;
	enum coresight_dev_subtype_helper helper_subtype;
};

/**
 * struct coresight_platform_data - data harvested from the DT specification
 * @cpu:	the CPU a source belongs to. Only applicable for ETM/PTMs.
 * @name:	name of the component as shown under sysfs.
 * @nr_inport:	number of input ports for this component.
 * @nr_outport:	number of output ports for this component.
 * @conns:	Array of nr_outport connections from this component
 */
struct coresight_platform_data {
	int cpu;
	const char *name;
	int nr_inport;
	int nr_outport;
	struct coresight_connection *conns;
};

/**
 * struct coresight_desc - description of a component required from drivers
 * @type:	as defined by @coresight_dev_type.
 * @subtype:	as defined by @coresight_dev_subtype.
 * @ops:	generic operations for this component, as defined
		by @coresight_ops.
 * @pdata:	platform data collected from DT.
 * @dev:	The device entity associated to this component.
 * @groups:	operations specific to this component. These will end up
		in the component's sysfs sub-directory.
 */
struct coresight_desc {
	enum coresight_dev_type type;
	union coresight_dev_subtype subtype;
	const struct coresight_ops *ops;
	struct coresight_platform_data *pdata;
	struct device *dev;
	const struct attribute_group **groups;
};

/**
 * struct coresight_connection - representation of a single connection
 * @outport:	a connection's output port number.
 * @chid_name:	remote component's name.
 * @child_port:	remote component's port number @output is connected to.
 * @child_dev:	a @coresight_device representation of the component
		connected to @outport.
 */
struct coresight_connection {
	int outport;
	const char *child_name;
	int child_port;
	struct coresight_device *child_dev;
};

/**
 * struct coresight_device - representation of a device as used by the framework
 * @conns:	array of coresight_connections associated to this component.
 * @nr_inport:	number of input port associated to this component.
 * @nr_outport:	number of output port associated to this component.
 * @type:	as defined by @coresight_dev_type.
 * @subtype:	as defined by @coresight_dev_subtype.
 * @ops:	generic operations for this component, as defined
		by @coresight_ops.
 * @dev:	The device entity associated to this component.
 * @refcnt:	keep track of what is in use.
 * @orphan:	true if the component has connections that haven't been linked.
 * @enable:	'true' if component is currently part of an active path.
 * @activated:	'true' only if a _sink_ has been activated.  A sink can be
		activated but not yet enabled.  Enabling for a _sink_
		happens when a source has been selected for that it.
 */
struct coresight_device {
	struct coresight_connection *conns;
	int nr_inport;
	int nr_outport;
	enum coresight_dev_type type;
	union coresight_dev_subtype subtype;
	const struct coresight_ops *ops;
	struct device dev;
	atomic_t *refcnt;
	bool orphan;
	bool enable;	/* true only if configured as part of a path */
	bool activated;	/* true only if a sink is part of a path */
};

#define to_coresight_device(d) container_of(d, struct coresight_device, dev)

#define source_ops(csdev)	csdev->ops->source_ops
#define sink_ops(csdev)		csdev->ops->sink_ops
#define link_ops(csdev)		csdev->ops->link_ops
#define helper_ops(csdev)	csdev->ops->helper_ops

/**
 * struct coresight_ops_sink - basic operations for a sink
 * Operations available for sinks
 * @enable:		enables the sink.
 * @disable:		disables the sink.
 * @alloc_buffer:	initialises perf's ring buffer for trace collection.
 * @free_buffer:	release memory allocated in @get_config.
 * @update_buffer:	update buffer pointers after a trace session.
 */
struct coresight_ops_sink {
	int (*enable)(struct coresight_device *csdev, u32 mode, void *data);
	void (*disable)(struct coresight_device *csdev);
	void *(*alloc_buffer)(struct coresight_device *csdev, int cpu,
			      void **pages, int nr_pages, bool overwrite);
	void (*free_buffer)(void *config);
	unsigned long (*update_buffer)(struct coresight_device *csdev,
			      struct perf_output_handle *handle,
			      void *sink_config);
};

/**
 * struct coresight_ops_link - basic operations for a link
 * Operations available for links.
 * @enable:	enables flow between iport and oport.
 * @disable:	disables flow between iport and oport.
 */
struct coresight_ops_link {
	int (*enable)(struct coresight_device *csdev, int iport, int oport);
	void (*disable)(struct coresight_device *csdev, int iport, int oport);
};

/**
 * struct coresight_ops_source - basic operations for a source
 * Operations available for sources.
 * @cpu_id:	returns the value of the CPU number this component
 *		is associated to.
 * @trace_id:	returns the value of the component's trace ID as known
 *		to the HW.
 * @enable:	enables tracing for a source.
 * @disable:	disables tracing for a source.
 */
struct coresight_ops_source {
	int (*cpu_id)(struct coresight_device *csdev);
	int (*trace_id)(struct coresight_device *csdev);
	int (*enable)(struct coresight_device *csdev,
		      struct perf_event *event,  u32 mode);
	void (*disable)(struct coresight_device *csdev,
			struct perf_event *event);
};

/**
 * struct coresight_ops_helper - Operations for a helper device.
 *
 * All operations could pass in a device specific data, which could
 * help the helper device to determine what to do.
 *
 * @enable	: Enable the device
 * @disable	: Disable the device
 */
struct coresight_ops_helper {
	int (*enable)(struct coresight_device *csdev, void *data);
	int (*disable)(struct coresight_device *csdev, void *data);
};

struct coresight_ops {
	const struct coresight_ops_sink *sink_ops;
	const struct coresight_ops_link *link_ops;
	const struct coresight_ops_source *source_ops;
	const struct coresight_ops_helper *helper_ops;
};

#ifdef CONFIG_CORESIGHT
extern struct coresight_device *
coresight_register(struct coresight_desc *desc);
extern void coresight_unregister(struct coresight_device *csdev);
extern int coresight_enable(struct coresight_device *csdev);
extern void coresight_disable(struct coresight_device *csdev);
extern int coresight_timeout(void __iomem *addr, u32 offset,
			     int position, int value);
#else
static inline struct coresight_device *
coresight_register(struct coresight_desc *desc) { return NULL; }
static inline void coresight_unregister(struct coresight_device *csdev) {}
static inline int
coresight_enable(struct coresight_device *csdev) { return -ENOSYS; }
static inline void coresight_disable(struct coresight_device *csdev) {}
static inline int coresight_timeout(void __iomem *addr, u32 offset,
				     int position, int value) { return 1; }
#endif

#ifdef CONFIG_OF
extern int of_coresight_get_cpu(const struct device_node *node);
extern struct coresight_platform_data *
of_get_coresight_platform_data(struct device *dev,
			       const struct device_node *node);
#else
static inline int of_coresight_get_cpu(const struct device_node *node)
{ return 0; }
static inline struct coresight_platform_data *of_get_coresight_platform_data(
	struct device *dev, const struct device_node *node) { return NULL; }
#endif

#endif
Commit	Line	Data
ad0dfdfd MP	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	/*
	3	* Copyright (c) 2012, The Linux Foundation. All rights reserved.
a06ae860 PP	4	*/
	5
	6	#ifndef _LINUX_CORESIGHT_H
	7	#define _LINUX_CORESIGHT_H
	8
	9	#include <linux/device.h>
882d5e11	10	#include <linux/perf_event.h>
ff63ec13	11	#include <linux/sched.h>
a06ae860 PP	12
	13	/* Peripheral id registers (0xFD0-0xFEC) */
	14	#define CORESIGHT_PERIPHIDR4 0xfd0
	15	#define CORESIGHT_PERIPHIDR5 0xfd4
	16	#define CORESIGHT_PERIPHIDR6 0xfd8
	17	#define CORESIGHT_PERIPHIDR7 0xfdC
	18	#define CORESIGHT_PERIPHIDR0 0xfe0
	19	#define CORESIGHT_PERIPHIDR1 0xfe4
	20	#define CORESIGHT_PERIPHIDR2 0xfe8
	21	#define CORESIGHT_PERIPHIDR3 0xfeC
	22	/* Component id registers (0xFF0-0xFFC) */
	23	#define CORESIGHT_COMPIDR0 0xff0
	24	#define CORESIGHT_COMPIDR1 0xff4
	25	#define CORESIGHT_COMPIDR2 0xff8
	26	#define CORESIGHT_COMPIDR3 0xffC
	27
	28	#define ETM_ARCH_V3_3 0x23
	29	#define ETM_ARCH_V3_5 0x25
	30	#define PFT_ARCH_V1_0 0x30
	31	#define PFT_ARCH_V1_1 0x31
	32
	33	#define CORESIGHT_UNLOCK 0xc5acce55
	34
	35	extern struct bus_type coresight_bustype;
	36
	37	enum coresight_dev_type {
	38	CORESIGHT_DEV_TYPE_NONE,
	39	CORESIGHT_DEV_TYPE_SINK,
	40	CORESIGHT_DEV_TYPE_LINK,
	41	CORESIGHT_DEV_TYPE_LINKSINK,
	42	CORESIGHT_DEV_TYPE_SOURCE,
8a091d84	43	CORESIGHT_DEV_TYPE_HELPER,
a06ae860 PP	44	};
	45
	46	enum coresight_dev_subtype_sink {
	47	CORESIGHT_DEV_SUBTYPE_SINK_NONE,
	48	CORESIGHT_DEV_SUBTYPE_SINK_PORT,
	49	CORESIGHT_DEV_SUBTYPE_SINK_BUFFER,
	50	};
	51
	52	enum coresight_dev_subtype_link {
	53	CORESIGHT_DEV_SUBTYPE_LINK_NONE,
	54	CORESIGHT_DEV_SUBTYPE_LINK_MERG,
	55	CORESIGHT_DEV_SUBTYPE_LINK_SPLIT,
	56	CORESIGHT_DEV_SUBTYPE_LINK_FIFO,
	57	};
	58
	59	enum coresight_dev_subtype_source {
	60	CORESIGHT_DEV_SUBTYPE_SOURCE_NONE,
	61	CORESIGHT_DEV_SUBTYPE_SOURCE_PROC,
	62	CORESIGHT_DEV_SUBTYPE_SOURCE_BUS,
	63	CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE,
	64	};
	65
8a091d84 SP	66	enum coresight_dev_subtype_helper {
8a091d84 SP	67	CORESIGHT_DEV_SUBTYPE_HELPER_NONE,
fcacb5c1	68	CORESIGHT_DEV_SUBTYPE_HELPER_CATU,
8a091d84 SP	69	};
8a091d84 SP	70
a06ae860	71	/**
00b78e8b	72	* union coresight_dev_subtype - further characterisation of a type
a06ae860	73	* @sink_subtype: type of sink this component is, as defined
00b78e8b	74	* by @coresight_dev_subtype_sink.
a06ae860	75	* @link_subtype: type of link this component is, as defined
00b78e8b	76	* by @coresight_dev_subtype_link.
a06ae860	77	* @source_subtype: type of source this component is, as defined
00b78e8b	78	* by @coresight_dev_subtype_source.
8a091d84 SP	79	* @helper_subtype: type of helper this component is, as defined
8a091d84 SP	80	* by @coresight_dev_subtype_helper.
a06ae860	81	*/
00b78e8b SP	82	union coresight_dev_subtype {
	83	/* We have some devices which acts as LINK and SINK */
	84	struct {
	85	enum coresight_dev_subtype_sink sink_subtype;
	86	enum coresight_dev_subtype_link link_subtype;
	87	};
a06ae860	88	enum coresight_dev_subtype_source source_subtype;
8a091d84	89	enum coresight_dev_subtype_helper helper_subtype;
a06ae860 PP	90	};
	91
	92	/**
	93	* struct coresight_platform_data - data harvested from the DT specification
	94	* @cpu: the CPU a source belongs to. Only applicable for ETM/PTMs.
	95	* @name: name of the component as shown under sysfs.
	96	* @nr_inport: number of input ports for this component.
a06ae860	97	* @nr_outport: number of output ports for this component.
c2c72941	98	* @conns: Array of nr_outport connections from this component
a06ae860 PP	99	*/
	100	struct coresight_platform_data {
	101	int cpu;
	102	const char *name;
	103	int nr_inport;
a06ae860	104	int nr_outport;
c2c72941	105	struct coresight_connection *conns;
a06ae860 PP	106	};
	107
	108	/**
	109	* struct coresight_desc - description of a component required from drivers
	110	* @type: as defined by @coresight_dev_type.
	111	* @subtype: as defined by @coresight_dev_subtype.
	112	* @ops: generic operations for this component, as defined
	113	by @coresight_ops.
	114	* @pdata: platform data collected from DT.
	115	* @dev: The device entity associated to this component.
8ee885a9	116	* @groups: operations specific to this component. These will end up
a06ae860 PP	117	in the component's sysfs sub-directory.
	118	*/
	119	struct coresight_desc {
	120	enum coresight_dev_type type;
00b78e8b	121	union coresight_dev_subtype subtype;
a06ae860 PP	122	const struct coresight_ops *ops;
	123	struct coresight_platform_data *pdata;
	124	struct device *dev;
	125	const struct attribute_group **groups;
	126	};
	127
	128	/**
	129	* struct coresight_connection - representation of a single connection
a06ae860 PP	130	* @outport: a connection's output port number.
	131	* @chid_name: remote component's name.
	132	* @child_port: remote component's port number @output is connected to.
	133	* @child_dev: a @coresight_device representation of the component
	134	connected to @outport.
	135	*/
	136	struct coresight_connection {
	137	int outport;
	138	const char *child_name;
	139	int child_port;
	140	struct coresight_device *child_dev;
	141	};
	142
	143	/**
	144	* struct coresight_device - representation of a device as used by the framework
8ee885a9	145	* @conns: array of coresight_connections associated to this component.
a06ae860 PP	146	* @nr_inport: number of input port associated to this component.
	147	* @nr_outport: number of output port associated to this component.
	148	* @type: as defined by @coresight_dev_type.
	149	* @subtype: as defined by @coresight_dev_subtype.
	150	* @ops: generic operations for this component, as defined
	151	by @coresight_ops.
	152	* @dev: The device entity associated to this component.
	153	* @refcnt: keep track of what is in use.
a06ae860 PP	154	* @orphan: true if the component has connections that haven't been linked.
	155	* @enable: 'true' if component is currently part of an active path.
	156	* @activated: 'true' only if a _sink_ has been activated. A sink can be
	157	activated but not yet enabled. Enabling for a _sink_
	158	happens when a source has been selected for that it.
	159	*/
	160	struct coresight_device {
	161	struct coresight_connection *conns;
	162	int nr_inport;
	163	int nr_outport;
	164	enum coresight_dev_type type;
00b78e8b	165	union coresight_dev_subtype subtype;
a06ae860 PP	166	const struct coresight_ops *ops;
	167	struct device dev;
	168	atomic_t *refcnt;
a06ae860 PP	169	bool orphan;
	170	bool enable; /* true only if configured as part of a path */
	171	bool activated; /* true only if a sink is part of a path */
	172	};
	173
	174	#define to_coresight_device(d) container_of(d, struct coresight_device, dev)
	175
	176	#define source_ops(csdev) csdev->ops->source_ops
	177	#define sink_ops(csdev) csdev->ops->sink_ops
	178	#define link_ops(csdev) csdev->ops->link_ops
8a091d84	179	#define helper_ops(csdev) csdev->ops->helper_ops
a06ae860	180
a06ae860 PP	181	/**
	182	* struct coresight_ops_sink - basic operations for a sink
	183	* Operations available for sinks
2997aa40 MP	184	* @enable: enables the sink.
	185	* @disable: disables the sink.
	186	* @alloc_buffer: initialises perf's ring buffer for trace collection.
	187	* @free_buffer: release memory allocated in @get_config.
2997aa40	188	* @update_buffer: update buffer pointers after a trace session.
a06ae860 PP	189	*/
a06ae860 PP	190	struct coresight_ops_sink {
3d6e8935	191	int (enable)(struct coresight_device csdev, u32 mode, void *data);
a06ae860	192	void (disable)(struct coresight_device csdev);
2997aa40 MP	193	void (alloc_buffer)(struct coresight_device *csdev, int cpu,
	194	void **pages, int nr_pages, bool overwrite);
	195	void (free_buffer)(void config);
7ec786ad	196	unsigned long (update_buffer)(struct coresight_device csdev,
2997aa40 MP	197	struct perf_output_handle *handle,
2997aa40 MP	198	void *sink_config);
a06ae860 PP	199	};
	200
	201	/**
	202	* struct coresight_ops_link - basic operations for a link
	203	* Operations available for links.
	204	* @enable: enables flow between iport and oport.
	205	* @disable: disables flow between iport and oport.
	206	*/
	207	struct coresight_ops_link {
	208	int (enable)(struct coresight_device csdev, int iport, int oport);
	209	void (disable)(struct coresight_device csdev, int iport, int oport);
	210	};
	211
	212	/**
	213	* struct coresight_ops_source - basic operations for a source
	214	* Operations available for sources.
52210c87 MP	215	* @cpu_id: returns the value of the CPU number this component
52210c87 MP	216	* is associated to.
a06ae860	217	* @trace_id: returns the value of the component's trace ID as known
882d5e11	218	* to the HW.
1d27ff5a	219	* @enable: enables tracing for a source.
a06ae860 PP	220	* @disable: disables tracing for a source.
	221	*/
	222	struct coresight_ops_source {
52210c87	223	int (cpu_id)(struct coresight_device csdev);
a06ae860	224	int (trace_id)(struct coresight_device csdev);
882d5e11	225	int (enable)(struct coresight_device csdev,
68905d73 MP	226	struct perf_event *event, u32 mode);
	227	void (disable)(struct coresight_device csdev,
	228	struct perf_event *event);
a06ae860 PP	229	};
a06ae860 PP	230
8a091d84 SP	231	/**
	232	* struct coresight_ops_helper - Operations for a helper device.
	233	*
	234	* All operations could pass in a device specific data, which could
	235	* help the helper device to determine what to do.
	236	*
	237	* @enable : Enable the device
	238	* @disable : Disable the device
	239	*/
	240	struct coresight_ops_helper {
	241	int (enable)(struct coresight_device csdev, void *data);
	242	int (disable)(struct coresight_device csdev, void *data);
	243	};
	244
a06ae860 PP	245	struct coresight_ops {
	246	const struct coresight_ops_sink *sink_ops;
	247	const struct coresight_ops_link *link_ops;
	248	const struct coresight_ops_source *source_ops;
8a091d84	249	const struct coresight_ops_helper *helper_ops;
a06ae860 PP	250	};
	251
	252	#ifdef CONFIG_CORESIGHT
	253	extern struct coresight_device *
	254	coresight_register(struct coresight_desc *desc);
	255	extern void coresight_unregister(struct coresight_device *csdev);
	256	extern int coresight_enable(struct coresight_device *csdev);
	257	extern void coresight_disable(struct coresight_device *csdev);
a06ae860 PP	258	extern int coresight_timeout(void __iomem *addr, u32 offset,
a06ae860 PP	259	int position, int value);
a06ae860 PP	260	#else
	261	static inline struct coresight_device *
	262	coresight_register(struct coresight_desc *desc) { return NULL; }
	263	static inline void coresight_unregister(struct coresight_device *csdev) {}
	264	static inline int
	265	coresight_enable(struct coresight_device *csdev) { return -ENOSYS; }
	266	static inline void coresight_disable(struct coresight_device *csdev) {}
a06ae860 PP	267	static inline int coresight_timeout(void __iomem *addr, u32 offset,
a06ae860 PP	268	int position, int value) { return 1; }
c61c4b5d MP	269	#endif
c61c4b5d MP	270
a06ae860	271	#ifdef CONFIG_OF
c56cdd7a	272	extern int of_coresight_get_cpu(const struct device_node *node);
f42fe520 LY	273	extern struct coresight_platform_data *
	274	of_get_coresight_platform_data(struct device *dev,
	275	const struct device_node *node);
c61c4b5d	276	#else
c56cdd7a LY	277	static inline int of_coresight_get_cpu(const struct device_node *node)
c56cdd7a LY	278	{ return 0; }
a06ae860	279	static inline struct coresight_platform_data *of_get_coresight_platform_data(
f42fe520	280	struct device dev, const struct device_node node) { return NULL; }
a06ae860	281	#endif
a06ae860 PP	282
a06ae860 PP	283	#endif