Commit | Line | Data |
---|---|---|
ad0dfdfd MP |
1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* | |
3 | * Copyright (c) 2012, The Linux Foundation. All rights reserved. | |
a06ae860 PP |
4 | */ |
5 | ||
6 | #ifndef _LINUX_CORESIGHT_H | |
7 | #define _LINUX_CORESIGHT_H | |
8 | ||
9 | #include <linux/device.h> | |
882d5e11 | 10 | #include <linux/perf_event.h> |
ff63ec13 | 11 | #include <linux/sched.h> |
a06ae860 PP |
12 | |
13 | /* Peripheral id registers (0xFD0-0xFEC) */ | |
14 | #define CORESIGHT_PERIPHIDR4 0xfd0 | |
15 | #define CORESIGHT_PERIPHIDR5 0xfd4 | |
16 | #define CORESIGHT_PERIPHIDR6 0xfd8 | |
17 | #define CORESIGHT_PERIPHIDR7 0xfdC | |
18 | #define CORESIGHT_PERIPHIDR0 0xfe0 | |
19 | #define CORESIGHT_PERIPHIDR1 0xfe4 | |
20 | #define CORESIGHT_PERIPHIDR2 0xfe8 | |
21 | #define CORESIGHT_PERIPHIDR3 0xfeC | |
22 | /* Component id registers (0xFF0-0xFFC) */ | |
23 | #define CORESIGHT_COMPIDR0 0xff0 | |
24 | #define CORESIGHT_COMPIDR1 0xff4 | |
25 | #define CORESIGHT_COMPIDR2 0xff8 | |
26 | #define CORESIGHT_COMPIDR3 0xffC | |
27 | ||
28 | #define ETM_ARCH_V3_3 0x23 | |
29 | #define ETM_ARCH_V3_5 0x25 | |
30 | #define PFT_ARCH_V1_0 0x30 | |
31 | #define PFT_ARCH_V1_1 0x31 | |
32 | ||
33 | #define CORESIGHT_UNLOCK 0xc5acce55 | |
34 | ||
35 | extern struct bus_type coresight_bustype; | |
36 | ||
37 | enum coresight_dev_type { | |
38 | CORESIGHT_DEV_TYPE_NONE, | |
39 | CORESIGHT_DEV_TYPE_SINK, | |
40 | CORESIGHT_DEV_TYPE_LINK, | |
41 | CORESIGHT_DEV_TYPE_LINKSINK, | |
42 | CORESIGHT_DEV_TYPE_SOURCE, | |
8a091d84 | 43 | CORESIGHT_DEV_TYPE_HELPER, |
835d722b | 44 | CORESIGHT_DEV_TYPE_ECT, |
a06ae860 PP |
45 | }; |
46 | ||
47 | enum coresight_dev_subtype_sink { | |
48 | CORESIGHT_DEV_SUBTYPE_SINK_NONE, | |
49 | CORESIGHT_DEV_SUBTYPE_SINK_PORT, | |
50 | CORESIGHT_DEV_SUBTYPE_SINK_BUFFER, | |
51 | }; | |
52 | ||
53 | enum coresight_dev_subtype_link { | |
54 | CORESIGHT_DEV_SUBTYPE_LINK_NONE, | |
55 | CORESIGHT_DEV_SUBTYPE_LINK_MERG, | |
56 | CORESIGHT_DEV_SUBTYPE_LINK_SPLIT, | |
57 | CORESIGHT_DEV_SUBTYPE_LINK_FIFO, | |
58 | }; | |
59 | ||
60 | enum coresight_dev_subtype_source { | |
61 | CORESIGHT_DEV_SUBTYPE_SOURCE_NONE, | |
62 | CORESIGHT_DEV_SUBTYPE_SOURCE_PROC, | |
63 | CORESIGHT_DEV_SUBTYPE_SOURCE_BUS, | |
64 | CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE, | |
65 | }; | |
66 | ||
8a091d84 SP |
67 | enum coresight_dev_subtype_helper { |
68 | CORESIGHT_DEV_SUBTYPE_HELPER_NONE, | |
fcacb5c1 | 69 | CORESIGHT_DEV_SUBTYPE_HELPER_CATU, |
8a091d84 SP |
70 | }; |
71 | ||
835d722b ML |
72 | /* Embedded Cross Trigger (ECT) sub-types */ |
73 | enum coresight_dev_subtype_ect { | |
74 | CORESIGHT_DEV_SUBTYPE_ECT_NONE, | |
75 | CORESIGHT_DEV_SUBTYPE_ECT_CTI, | |
76 | }; | |
77 | ||
a06ae860 | 78 | /** |
00b78e8b | 79 | * union coresight_dev_subtype - further characterisation of a type |
a06ae860 | 80 | * @sink_subtype: type of sink this component is, as defined |
00b78e8b | 81 | * by @coresight_dev_subtype_sink. |
a06ae860 | 82 | * @link_subtype: type of link this component is, as defined |
00b78e8b | 83 | * by @coresight_dev_subtype_link. |
a06ae860 | 84 | * @source_subtype: type of source this component is, as defined |
00b78e8b | 85 | * by @coresight_dev_subtype_source. |
8a091d84 SP |
86 | * @helper_subtype: type of helper this component is, as defined |
87 | * by @coresight_dev_subtype_helper. | |
835d722b ML |
88 | * @ect_subtype: type of cross trigger this component is, as |
89 | * defined by @coresight_dev_subtype_ect | |
a06ae860 | 90 | */ |
00b78e8b SP |
91 | union coresight_dev_subtype { |
92 | /* We have some devices which acts as LINK and SINK */ | |
93 | struct { | |
94 | enum coresight_dev_subtype_sink sink_subtype; | |
95 | enum coresight_dev_subtype_link link_subtype; | |
96 | }; | |
a06ae860 | 97 | enum coresight_dev_subtype_source source_subtype; |
8a091d84 | 98 | enum coresight_dev_subtype_helper helper_subtype; |
835d722b | 99 | enum coresight_dev_subtype_ect ect_subtype; |
a06ae860 PP |
100 | }; |
101 | ||
102 | /** | |
103 | * struct coresight_platform_data - data harvested from the DT specification | |
a06ae860 | 104 | * @nr_inport: number of input ports for this component. |
a06ae860 | 105 | * @nr_outport: number of output ports for this component. |
c2c72941 | 106 | * @conns: Array of nr_outport connections from this component |
a06ae860 PP |
107 | */ |
108 | struct coresight_platform_data { | |
a06ae860 | 109 | int nr_inport; |
a06ae860 | 110 | int nr_outport; |
c2c72941 | 111 | struct coresight_connection *conns; |
a06ae860 PP |
112 | }; |
113 | ||
114 | /** | |
115 | * struct coresight_desc - description of a component required from drivers | |
116 | * @type: as defined by @coresight_dev_type. | |
117 | * @subtype: as defined by @coresight_dev_subtype. | |
118 | * @ops: generic operations for this component, as defined | |
2ede79a6 | 119 | * by @coresight_ops. |
a06ae860 PP |
120 | * @pdata: platform data collected from DT. |
121 | * @dev: The device entity associated to this component. | |
8ee885a9 | 122 | * @groups: operations specific to this component. These will end up |
2ede79a6 SP |
123 | * in the component's sysfs sub-directory. |
124 | * @name: name for the coresight device, also shown under sysfs. | |
a06ae860 PP |
125 | */ |
126 | struct coresight_desc { | |
127 | enum coresight_dev_type type; | |
00b78e8b | 128 | union coresight_dev_subtype subtype; |
a06ae860 PP |
129 | const struct coresight_ops *ops; |
130 | struct coresight_platform_data *pdata; | |
131 | struct device *dev; | |
132 | const struct attribute_group **groups; | |
2ede79a6 | 133 | const char *name; |
a06ae860 PP |
134 | }; |
135 | ||
136 | /** | |
137 | * struct coresight_connection - representation of a single connection | |
a06ae860 | 138 | * @outport: a connection's output port number. |
a06ae860 | 139 | * @child_port: remote component's port number @output is connected to. |
37ea1ffd | 140 | * @chid_fwnode: remote component's fwnode handle. |
a06ae860 PP |
141 | * @child_dev: a @coresight_device representation of the component |
142 | connected to @outport. | |
8a7365c2 | 143 | * @link: Representation of the connection as a sysfs link. |
a06ae860 PP |
144 | */ |
145 | struct coresight_connection { | |
146 | int outport; | |
a06ae860 | 147 | int child_port; |
37ea1ffd | 148 | struct fwnode_handle *child_fwnode; |
a06ae860 | 149 | struct coresight_device *child_dev; |
8a7365c2 | 150 | struct coresight_sysfs_link *link; |
a06ae860 PP |
151 | }; |
152 | ||
80961525 ML |
153 | /** |
154 | * struct coresight_sysfs_link - representation of a connection in sysfs. | |
155 | * @orig: Originating (master) coresight device for the link. | |
156 | * @orig_name: Name to use for the link orig->target. | |
157 | * @target: Target (slave) coresight device for the link. | |
158 | * @target_name: Name to use for the link target->orig. | |
159 | */ | |
160 | struct coresight_sysfs_link { | |
161 | struct coresight_device *orig; | |
162 | const char *orig_name; | |
163 | struct coresight_device *target; | |
164 | const char *target_name; | |
165 | }; | |
166 | ||
a06ae860 PP |
167 | /** |
168 | * struct coresight_device - representation of a device as used by the framework | |
b77e3ed0 | 169 | * @pdata: Platform data with device connections associated to this device. |
a06ae860 PP |
170 | * @type: as defined by @coresight_dev_type. |
171 | * @subtype: as defined by @coresight_dev_subtype. | |
172 | * @ops: generic operations for this component, as defined | |
173 | by @coresight_ops. | |
174 | * @dev: The device entity associated to this component. | |
175 | * @refcnt: keep track of what is in use. | |
a06ae860 PP |
176 | * @orphan: true if the component has connections that haven't been linked. |
177 | * @enable: 'true' if component is currently part of an active path. | |
178 | * @activated: 'true' only if a _sink_ has been activated. A sink can be | |
bb8e370b MP |
179 | * activated but not yet enabled. Enabling for a _sink_ |
180 | * appens when a source has been selected for that it. | |
181 | * @ea: Device attribute for sink representation under PMU directory. | |
177af828 ML |
182 | * @ect_dev: Associated cross trigger device. Not part of the trace data |
183 | * path or connections. | |
80961525 ML |
184 | * @nr_links: number of sysfs links created to other components from this |
185 | * device. These will appear in the "connections" group. | |
186 | * @has_conns_grp: Have added a "connections" group for sysfs links. | |
a06ae860 PP |
187 | */ |
188 | struct coresight_device { | |
b77e3ed0 | 189 | struct coresight_platform_data *pdata; |
a06ae860 | 190 | enum coresight_dev_type type; |
00b78e8b | 191 | union coresight_dev_subtype subtype; |
a06ae860 PP |
192 | const struct coresight_ops *ops; |
193 | struct device dev; | |
194 | atomic_t *refcnt; | |
a06ae860 PP |
195 | bool orphan; |
196 | bool enable; /* true only if configured as part of a path */ | |
bb8e370b | 197 | /* sink specific fields */ |
a06ae860 | 198 | bool activated; /* true only if a sink is part of a path */ |
bb8e370b | 199 | struct dev_ext_attribute *ea; |
177af828 ML |
200 | /* cross trigger handling */ |
201 | struct coresight_device *ect_dev; | |
80961525 ML |
202 | /* sysfs links between components */ |
203 | int nr_links; | |
204 | bool has_conns_grp; | |
a06ae860 PP |
205 | }; |
206 | ||
0f5f9b6b SP |
207 | /* |
208 | * coresight_dev_list - Mapping for devices to "name" index for device | |
209 | * names. | |
210 | * | |
211 | * @nr_idx: Number of entries already allocated. | |
212 | * @pfx: Prefix pattern for device name. | |
213 | * @fwnode_list: Array of fwnode_handles associated with each allocated | |
214 | * index, upto nr_idx entries. | |
215 | */ | |
216 | struct coresight_dev_list { | |
217 | int nr_idx; | |
218 | const char *pfx; | |
219 | struct fwnode_handle **fwnode_list; | |
220 | }; | |
221 | ||
222 | #define DEFINE_CORESIGHT_DEVLIST(var, dev_pfx) \ | |
223 | static struct coresight_dev_list (var) = { \ | |
224 | .pfx = dev_pfx, \ | |
225 | .nr_idx = 0, \ | |
226 | .fwnode_list = NULL, \ | |
227 | } | |
228 | ||
a06ae860 PP |
229 | #define to_coresight_device(d) container_of(d, struct coresight_device, dev) |
230 | ||
231 | #define source_ops(csdev) csdev->ops->source_ops | |
232 | #define sink_ops(csdev) csdev->ops->sink_ops | |
233 | #define link_ops(csdev) csdev->ops->link_ops | |
8a091d84 | 234 | #define helper_ops(csdev) csdev->ops->helper_ops |
835d722b | 235 | #define ect_ops(csdev) csdev->ops->ect_ops |
a06ae860 | 236 | |
a06ae860 PP |
237 | /** |
238 | * struct coresight_ops_sink - basic operations for a sink | |
239 | * Operations available for sinks | |
2997aa40 MP |
240 | * @enable: enables the sink. |
241 | * @disable: disables the sink. | |
242 | * @alloc_buffer: initialises perf's ring buffer for trace collection. | |
243 | * @free_buffer: release memory allocated in @get_config. | |
2997aa40 | 244 | * @update_buffer: update buffer pointers after a trace session. |
a06ae860 PP |
245 | */ |
246 | struct coresight_ops_sink { | |
3d6e8935 | 247 | int (*enable)(struct coresight_device *csdev, u32 mode, void *data); |
6c817a95 | 248 | int (*disable)(struct coresight_device *csdev); |
a0f08a6a MP |
249 | void *(*alloc_buffer)(struct coresight_device *csdev, |
250 | struct perf_event *event, void **pages, | |
251 | int nr_pages, bool overwrite); | |
2997aa40 | 252 | void (*free_buffer)(void *config); |
7ec786ad | 253 | unsigned long (*update_buffer)(struct coresight_device *csdev, |
2997aa40 MP |
254 | struct perf_output_handle *handle, |
255 | void *sink_config); | |
a06ae860 PP |
256 | }; |
257 | ||
258 | /** | |
259 | * struct coresight_ops_link - basic operations for a link | |
260 | * Operations available for links. | |
261 | * @enable: enables flow between iport and oport. | |
262 | * @disable: disables flow between iport and oport. | |
263 | */ | |
264 | struct coresight_ops_link { | |
265 | int (*enable)(struct coresight_device *csdev, int iport, int oport); | |
266 | void (*disable)(struct coresight_device *csdev, int iport, int oport); | |
267 | }; | |
268 | ||
269 | /** | |
270 | * struct coresight_ops_source - basic operations for a source | |
271 | * Operations available for sources. | |
52210c87 MP |
272 | * @cpu_id: returns the value of the CPU number this component |
273 | * is associated to. | |
a06ae860 | 274 | * @trace_id: returns the value of the component's trace ID as known |
882d5e11 | 275 | * to the HW. |
1d27ff5a | 276 | * @enable: enables tracing for a source. |
a06ae860 PP |
277 | * @disable: disables tracing for a source. |
278 | */ | |
279 | struct coresight_ops_source { | |
52210c87 | 280 | int (*cpu_id)(struct coresight_device *csdev); |
a06ae860 | 281 | int (*trace_id)(struct coresight_device *csdev); |
882d5e11 | 282 | int (*enable)(struct coresight_device *csdev, |
68905d73 MP |
283 | struct perf_event *event, u32 mode); |
284 | void (*disable)(struct coresight_device *csdev, | |
285 | struct perf_event *event); | |
a06ae860 PP |
286 | }; |
287 | ||
8a091d84 SP |
288 | /** |
289 | * struct coresight_ops_helper - Operations for a helper device. | |
290 | * | |
291 | * All operations could pass in a device specific data, which could | |
292 | * help the helper device to determine what to do. | |
293 | * | |
294 | * @enable : Enable the device | |
295 | * @disable : Disable the device | |
296 | */ | |
297 | struct coresight_ops_helper { | |
298 | int (*enable)(struct coresight_device *csdev, void *data); | |
299 | int (*disable)(struct coresight_device *csdev, void *data); | |
300 | }; | |
301 | ||
835d722b ML |
302 | /** |
303 | * struct coresight_ops_ect - Ops for an embedded cross trigger device | |
304 | * | |
305 | * @enable : Enable the device | |
306 | * @disable : Disable the device | |
307 | */ | |
308 | struct coresight_ops_ect { | |
309 | int (*enable)(struct coresight_device *csdev); | |
310 | int (*disable)(struct coresight_device *csdev); | |
311 | }; | |
312 | ||
a06ae860 PP |
313 | struct coresight_ops { |
314 | const struct coresight_ops_sink *sink_ops; | |
315 | const struct coresight_ops_link *link_ops; | |
316 | const struct coresight_ops_source *source_ops; | |
8a091d84 | 317 | const struct coresight_ops_helper *helper_ops; |
835d722b | 318 | const struct coresight_ops_ect *ect_ops; |
a06ae860 PP |
319 | }; |
320 | ||
321 | #ifdef CONFIG_CORESIGHT | |
322 | extern struct coresight_device * | |
323 | coresight_register(struct coresight_desc *desc); | |
324 | extern void coresight_unregister(struct coresight_device *csdev); | |
325 | extern int coresight_enable(struct coresight_device *csdev); | |
326 | extern void coresight_disable(struct coresight_device *csdev); | |
a06ae860 PP |
327 | extern int coresight_timeout(void __iomem *addr, u32 offset, |
328 | int position, int value); | |
2478a6ae SP |
329 | |
330 | extern int coresight_claim_device(void __iomem *base); | |
331 | extern int coresight_claim_device_unlocked(void __iomem *base); | |
332 | ||
333 | extern void coresight_disclaim_device(void __iomem *base); | |
334 | extern void coresight_disclaim_device_unlocked(void __iomem *base); | |
0f5f9b6b SP |
335 | extern char *coresight_alloc_device_name(struct coresight_dev_list *devs, |
336 | struct device *dev); | |
f188b5e7 AM |
337 | |
338 | extern bool coresight_loses_context_with_cpu(struct device *dev); | |
a06ae860 PP |
339 | #else |
340 | static inline struct coresight_device * | |
341 | coresight_register(struct coresight_desc *desc) { return NULL; } | |
342 | static inline void coresight_unregister(struct coresight_device *csdev) {} | |
343 | static inline int | |
344 | coresight_enable(struct coresight_device *csdev) { return -ENOSYS; } | |
345 | static inline void coresight_disable(struct coresight_device *csdev) {} | |
a06ae860 PP |
346 | static inline int coresight_timeout(void __iomem *addr, u32 offset, |
347 | int position, int value) { return 1; } | |
2478a6ae SP |
348 | static inline int coresight_claim_device_unlocked(void __iomem *base) |
349 | { | |
350 | return -EINVAL; | |
351 | } | |
352 | ||
353 | static inline int coresight_claim_device(void __iomem *base) | |
354 | { | |
355 | return -EINVAL; | |
356 | } | |
357 | ||
358 | static inline void coresight_disclaim_device(void __iomem *base) {} | |
359 | static inline void coresight_disclaim_device_unlocked(void __iomem *base) {} | |
360 | ||
f188b5e7 AM |
361 | static inline bool coresight_loses_context_with_cpu(struct device *dev) |
362 | { | |
363 | return false; | |
364 | } | |
c61c4b5d MP |
365 | #endif |
366 | ||
91824db2 | 367 | extern int coresight_get_cpu(struct device *dev); |
a06ae860 | 368 | |
f03631da SP |
369 | struct coresight_platform_data *coresight_get_platform_data(struct device *dev); |
370 | ||
a06ae860 | 371 | #endif |