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ad0dfdfd MP |
1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* | |
3 | * Copyright (c) 2012, The Linux Foundation. All rights reserved. | |
a06ae860 PP |
4 | */ |
5 | ||
6 | #ifndef _LINUX_CORESIGHT_H | |
7 | #define _LINUX_CORESIGHT_H | |
8 | ||
9 | #include <linux/device.h> | |
6e736c60 | 10 | #include <linux/io.h> |
882d5e11 | 11 | #include <linux/perf_event.h> |
ff63ec13 | 12 | #include <linux/sched.h> |
a06ae860 PP |
13 | |
14 | /* Peripheral id registers (0xFD0-0xFEC) */ | |
15 | #define CORESIGHT_PERIPHIDR4 0xfd0 | |
16 | #define CORESIGHT_PERIPHIDR5 0xfd4 | |
17 | #define CORESIGHT_PERIPHIDR6 0xfd8 | |
18 | #define CORESIGHT_PERIPHIDR7 0xfdC | |
19 | #define CORESIGHT_PERIPHIDR0 0xfe0 | |
20 | #define CORESIGHT_PERIPHIDR1 0xfe4 | |
21 | #define CORESIGHT_PERIPHIDR2 0xfe8 | |
22 | #define CORESIGHT_PERIPHIDR3 0xfeC | |
23 | /* Component id registers (0xFF0-0xFFC) */ | |
24 | #define CORESIGHT_COMPIDR0 0xff0 | |
25 | #define CORESIGHT_COMPIDR1 0xff4 | |
26 | #define CORESIGHT_COMPIDR2 0xff8 | |
27 | #define CORESIGHT_COMPIDR3 0xffC | |
28 | ||
29 | #define ETM_ARCH_V3_3 0x23 | |
30 | #define ETM_ARCH_V3_5 0x25 | |
31 | #define PFT_ARCH_V1_0 0x30 | |
32 | #define PFT_ARCH_V1_1 0x31 | |
33 | ||
34 | #define CORESIGHT_UNLOCK 0xc5acce55 | |
35 | ||
36 | extern struct bus_type coresight_bustype; | |
37 | ||
38 | enum coresight_dev_type { | |
a06ae860 PP |
39 | CORESIGHT_DEV_TYPE_SINK, |
40 | CORESIGHT_DEV_TYPE_LINK, | |
41 | CORESIGHT_DEV_TYPE_LINKSINK, | |
42 | CORESIGHT_DEV_TYPE_SOURCE, | |
8a091d84 | 43 | CORESIGHT_DEV_TYPE_HELPER, |
835d722b | 44 | CORESIGHT_DEV_TYPE_ECT, |
a06ae860 PP |
45 | }; |
46 | ||
47 | enum coresight_dev_subtype_sink { | |
a06ae860 PP |
48 | CORESIGHT_DEV_SUBTYPE_SINK_PORT, |
49 | CORESIGHT_DEV_SUBTYPE_SINK_BUFFER, | |
0336bdfd | 50 | CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM, |
2cd87a7b | 51 | CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM, |
a06ae860 PP |
52 | }; |
53 | ||
54 | enum coresight_dev_subtype_link { | |
a06ae860 PP |
55 | CORESIGHT_DEV_SUBTYPE_LINK_MERG, |
56 | CORESIGHT_DEV_SUBTYPE_LINK_SPLIT, | |
57 | CORESIGHT_DEV_SUBTYPE_LINK_FIFO, | |
58 | }; | |
59 | ||
60 | enum coresight_dev_subtype_source { | |
a06ae860 PP |
61 | CORESIGHT_DEV_SUBTYPE_SOURCE_PROC, |
62 | CORESIGHT_DEV_SUBTYPE_SOURCE_BUS, | |
63 | CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE, | |
64 | }; | |
65 | ||
8a091d84 | 66 | enum coresight_dev_subtype_helper { |
fcacb5c1 | 67 | CORESIGHT_DEV_SUBTYPE_HELPER_CATU, |
8a091d84 SP |
68 | }; |
69 | ||
835d722b ML |
70 | /* Embedded Cross Trigger (ECT) sub-types */ |
71 | enum coresight_dev_subtype_ect { | |
72 | CORESIGHT_DEV_SUBTYPE_ECT_NONE, | |
73 | CORESIGHT_DEV_SUBTYPE_ECT_CTI, | |
74 | }; | |
75 | ||
a06ae860 | 76 | /** |
00b78e8b | 77 | * union coresight_dev_subtype - further characterisation of a type |
a06ae860 | 78 | * @sink_subtype: type of sink this component is, as defined |
00b78e8b | 79 | * by @coresight_dev_subtype_sink. |
a06ae860 | 80 | * @link_subtype: type of link this component is, as defined |
00b78e8b | 81 | * by @coresight_dev_subtype_link. |
a06ae860 | 82 | * @source_subtype: type of source this component is, as defined |
00b78e8b | 83 | * by @coresight_dev_subtype_source. |
8a091d84 SP |
84 | * @helper_subtype: type of helper this component is, as defined |
85 | * by @coresight_dev_subtype_helper. | |
835d722b ML |
86 | * @ect_subtype: type of cross trigger this component is, as |
87 | * defined by @coresight_dev_subtype_ect | |
a06ae860 | 88 | */ |
00b78e8b SP |
89 | union coresight_dev_subtype { |
90 | /* We have some devices which acts as LINK and SINK */ | |
91 | struct { | |
92 | enum coresight_dev_subtype_sink sink_subtype; | |
93 | enum coresight_dev_subtype_link link_subtype; | |
94 | }; | |
a06ae860 | 95 | enum coresight_dev_subtype_source source_subtype; |
8a091d84 | 96 | enum coresight_dev_subtype_helper helper_subtype; |
835d722b | 97 | enum coresight_dev_subtype_ect ect_subtype; |
a06ae860 PP |
98 | }; |
99 | ||
100 | /** | |
d375b356 SP |
101 | * struct coresight_platform_data - data harvested from the firmware |
102 | * specification. | |
103 | * | |
104 | * @nr_inport: Number of elements for the input connections. | |
105 | * @nr_outport: Number of elements for the output connections. | |
106 | * @conns: Sparse array of nr_outport connections from this component. | |
a06ae860 PP |
107 | */ |
108 | struct coresight_platform_data { | |
a06ae860 | 109 | int nr_inport; |
a06ae860 | 110 | int nr_outport; |
c2c72941 | 111 | struct coresight_connection *conns; |
a06ae860 PP |
112 | }; |
113 | ||
6e736c60 SP |
114 | /** |
115 | * struct csdev_access - Abstraction of a CoreSight device access. | |
116 | * | |
117 | * @io_mem : True if the device has memory mapped I/O | |
118 | * @base : When io_mem == true, base address of the component | |
119 | * @read : Read from the given "offset" of the given instance. | |
120 | * @write : Write "val" to the given "offset". | |
121 | */ | |
122 | struct csdev_access { | |
123 | bool io_mem; | |
124 | union { | |
125 | void __iomem *base; | |
126 | struct { | |
127 | u64 (*read)(u32 offset, bool relaxed, bool _64bit); | |
128 | void (*write)(u64 val, u32 offset, bool relaxed, | |
129 | bool _64bit); | |
130 | }; | |
131 | }; | |
132 | }; | |
133 | ||
134 | #define CSDEV_ACCESS_IOMEM(_addr) \ | |
135 | ((struct csdev_access) { \ | |
136 | .io_mem = true, \ | |
137 | .base = (_addr), \ | |
138 | }) | |
139 | ||
a06ae860 PP |
140 | /** |
141 | * struct coresight_desc - description of a component required from drivers | |
142 | * @type: as defined by @coresight_dev_type. | |
143 | * @subtype: as defined by @coresight_dev_subtype. | |
144 | * @ops: generic operations for this component, as defined | |
2ede79a6 | 145 | * by @coresight_ops. |
a06ae860 PP |
146 | * @pdata: platform data collected from DT. |
147 | * @dev: The device entity associated to this component. | |
8ee885a9 | 148 | * @groups: operations specific to this component. These will end up |
2ede79a6 SP |
149 | * in the component's sysfs sub-directory. |
150 | * @name: name for the coresight device, also shown under sysfs. | |
6e736c60 | 151 | * @access: Describe access to the device |
a06ae860 PP |
152 | */ |
153 | struct coresight_desc { | |
154 | enum coresight_dev_type type; | |
00b78e8b | 155 | union coresight_dev_subtype subtype; |
a06ae860 PP |
156 | const struct coresight_ops *ops; |
157 | struct coresight_platform_data *pdata; | |
158 | struct device *dev; | |
159 | const struct attribute_group **groups; | |
2ede79a6 | 160 | const char *name; |
6e736c60 | 161 | struct csdev_access access; |
a06ae860 PP |
162 | }; |
163 | ||
164 | /** | |
165 | * struct coresight_connection - representation of a single connection | |
a06ae860 | 166 | * @outport: a connection's output port number. |
a06ae860 | 167 | * @child_port: remote component's port number @output is connected to. |
37ea1ffd | 168 | * @chid_fwnode: remote component's fwnode handle. |
a06ae860 PP |
169 | * @child_dev: a @coresight_device representation of the component |
170 | connected to @outport. | |
8a7365c2 | 171 | * @link: Representation of the connection as a sysfs link. |
a06ae860 PP |
172 | */ |
173 | struct coresight_connection { | |
174 | int outport; | |
a06ae860 | 175 | int child_port; |
37ea1ffd | 176 | struct fwnode_handle *child_fwnode; |
a06ae860 | 177 | struct coresight_device *child_dev; |
8a7365c2 | 178 | struct coresight_sysfs_link *link; |
a06ae860 PP |
179 | }; |
180 | ||
80961525 ML |
181 | /** |
182 | * struct coresight_sysfs_link - representation of a connection in sysfs. | |
183 | * @orig: Originating (master) coresight device for the link. | |
184 | * @orig_name: Name to use for the link orig->target. | |
185 | * @target: Target (slave) coresight device for the link. | |
186 | * @target_name: Name to use for the link target->orig. | |
187 | */ | |
188 | struct coresight_sysfs_link { | |
189 | struct coresight_device *orig; | |
190 | const char *orig_name; | |
191 | struct coresight_device *target; | |
192 | const char *target_name; | |
193 | }; | |
194 | ||
a06ae860 PP |
195 | /** |
196 | * struct coresight_device - representation of a device as used by the framework | |
b77e3ed0 | 197 | * @pdata: Platform data with device connections associated to this device. |
a06ae860 PP |
198 | * @type: as defined by @coresight_dev_type. |
199 | * @subtype: as defined by @coresight_dev_subtype. | |
200 | * @ops: generic operations for this component, as defined | |
6e736c60 SP |
201 | * by @coresight_ops. |
202 | * @access: Device i/o access abstraction for this device. | |
a06ae860 PP |
203 | * @dev: The device entity associated to this component. |
204 | * @refcnt: keep track of what is in use. | |
a06ae860 PP |
205 | * @orphan: true if the component has connections that haven't been linked. |
206 | * @enable: 'true' if component is currently part of an active path. | |
207 | * @activated: 'true' only if a _sink_ has been activated. A sink can be | |
bb8e370b | 208 | * activated but not yet enabled. Enabling for a _sink_ |
d061cd73 ML |
209 | * happens when a source has been selected and a path is enabled |
210 | * from source to that sink. | |
bb8e370b | 211 | * @ea: Device attribute for sink representation under PMU directory. |
0336bdfd | 212 | * @def_sink: cached reference to default sink found for this device. |
177af828 ML |
213 | * @ect_dev: Associated cross trigger device. Not part of the trace data |
214 | * path or connections. | |
80961525 ML |
215 | * @nr_links: number of sysfs links created to other components from this |
216 | * device. These will appear in the "connections" group. | |
217 | * @has_conns_grp: Have added a "connections" group for sysfs links. | |
42ff700f ML |
218 | * @feature_csdev_list: List of complex feature programming added to the device. |
219 | * @config_csdev_list: List of system configurations added to the device. | |
220 | * @cscfg_csdev_lock: Protect the lists of configurations and features. | |
f8cce2ff | 221 | * @active_cscfg_ctxt: Context information for current active system configuration. |
a06ae860 PP |
222 | */ |
223 | struct coresight_device { | |
b77e3ed0 | 224 | struct coresight_platform_data *pdata; |
a06ae860 | 225 | enum coresight_dev_type type; |
00b78e8b | 226 | union coresight_dev_subtype subtype; |
a06ae860 | 227 | const struct coresight_ops *ops; |
6e736c60 | 228 | struct csdev_access access; |
a06ae860 PP |
229 | struct device dev; |
230 | atomic_t *refcnt; | |
a06ae860 PP |
231 | bool orphan; |
232 | bool enable; /* true only if configured as part of a path */ | |
bb8e370b | 233 | /* sink specific fields */ |
a06ae860 | 234 | bool activated; /* true only if a sink is part of a path */ |
bb8e370b | 235 | struct dev_ext_attribute *ea; |
0336bdfd | 236 | struct coresight_device *def_sink; |
177af828 ML |
237 | /* cross trigger handling */ |
238 | struct coresight_device *ect_dev; | |
80961525 ML |
239 | /* sysfs links between components */ |
240 | int nr_links; | |
241 | bool has_conns_grp; | |
f2ccc7b7 | 242 | bool ect_enabled; /* true only if associated ect device is enabled */ |
42ff700f ML |
243 | /* system configuration and feature lists */ |
244 | struct list_head feature_csdev_list; | |
245 | struct list_head config_csdev_list; | |
246 | spinlock_t cscfg_csdev_lock; | |
f8cce2ff | 247 | void *active_cscfg_ctxt; |
a06ae860 PP |
248 | }; |
249 | ||
0f5f9b6b SP |
250 | /* |
251 | * coresight_dev_list - Mapping for devices to "name" index for device | |
252 | * names. | |
253 | * | |
254 | * @nr_idx: Number of entries already allocated. | |
255 | * @pfx: Prefix pattern for device name. | |
256 | * @fwnode_list: Array of fwnode_handles associated with each allocated | |
257 | * index, upto nr_idx entries. | |
258 | */ | |
259 | struct coresight_dev_list { | |
260 | int nr_idx; | |
261 | const char *pfx; | |
262 | struct fwnode_handle **fwnode_list; | |
263 | }; | |
264 | ||
265 | #define DEFINE_CORESIGHT_DEVLIST(var, dev_pfx) \ | |
266 | static struct coresight_dev_list (var) = { \ | |
267 | .pfx = dev_pfx, \ | |
268 | .nr_idx = 0, \ | |
269 | .fwnode_list = NULL, \ | |
270 | } | |
271 | ||
a06ae860 PP |
272 | #define to_coresight_device(d) container_of(d, struct coresight_device, dev) |
273 | ||
274 | #define source_ops(csdev) csdev->ops->source_ops | |
275 | #define sink_ops(csdev) csdev->ops->sink_ops | |
276 | #define link_ops(csdev) csdev->ops->link_ops | |
8a091d84 | 277 | #define helper_ops(csdev) csdev->ops->helper_ops |
835d722b | 278 | #define ect_ops(csdev) csdev->ops->ect_ops |
a06ae860 | 279 | |
a06ae860 PP |
280 | /** |
281 | * struct coresight_ops_sink - basic operations for a sink | |
282 | * Operations available for sinks | |
2997aa40 MP |
283 | * @enable: enables the sink. |
284 | * @disable: disables the sink. | |
285 | * @alloc_buffer: initialises perf's ring buffer for trace collection. | |
286 | * @free_buffer: release memory allocated in @get_config. | |
2997aa40 | 287 | * @update_buffer: update buffer pointers after a trace session. |
a06ae860 PP |
288 | */ |
289 | struct coresight_ops_sink { | |
3d6e8935 | 290 | int (*enable)(struct coresight_device *csdev, u32 mode, void *data); |
6c817a95 | 291 | int (*disable)(struct coresight_device *csdev); |
a0f08a6a MP |
292 | void *(*alloc_buffer)(struct coresight_device *csdev, |
293 | struct perf_event *event, void **pages, | |
294 | int nr_pages, bool overwrite); | |
2997aa40 | 295 | void (*free_buffer)(void *config); |
7ec786ad | 296 | unsigned long (*update_buffer)(struct coresight_device *csdev, |
2997aa40 MP |
297 | struct perf_output_handle *handle, |
298 | void *sink_config); | |
a06ae860 PP |
299 | }; |
300 | ||
301 | /** | |
302 | * struct coresight_ops_link - basic operations for a link | |
303 | * Operations available for links. | |
304 | * @enable: enables flow between iport and oport. | |
305 | * @disable: disables flow between iport and oport. | |
306 | */ | |
307 | struct coresight_ops_link { | |
308 | int (*enable)(struct coresight_device *csdev, int iport, int oport); | |
309 | void (*disable)(struct coresight_device *csdev, int iport, int oport); | |
310 | }; | |
311 | ||
312 | /** | |
313 | * struct coresight_ops_source - basic operations for a source | |
314 | * Operations available for sources. | |
52210c87 MP |
315 | * @cpu_id: returns the value of the CPU number this component |
316 | * is associated to. | |
a06ae860 | 317 | * @trace_id: returns the value of the component's trace ID as known |
882d5e11 | 318 | * to the HW. |
1d27ff5a | 319 | * @enable: enables tracing for a source. |
a06ae860 PP |
320 | * @disable: disables tracing for a source. |
321 | */ | |
322 | struct coresight_ops_source { | |
52210c87 | 323 | int (*cpu_id)(struct coresight_device *csdev); |
a06ae860 | 324 | int (*trace_id)(struct coresight_device *csdev); |
882d5e11 | 325 | int (*enable)(struct coresight_device *csdev, |
68905d73 MP |
326 | struct perf_event *event, u32 mode); |
327 | void (*disable)(struct coresight_device *csdev, | |
328 | struct perf_event *event); | |
a06ae860 PP |
329 | }; |
330 | ||
8a091d84 SP |
331 | /** |
332 | * struct coresight_ops_helper - Operations for a helper device. | |
333 | * | |
334 | * All operations could pass in a device specific data, which could | |
335 | * help the helper device to determine what to do. | |
336 | * | |
337 | * @enable : Enable the device | |
338 | * @disable : Disable the device | |
339 | */ | |
340 | struct coresight_ops_helper { | |
341 | int (*enable)(struct coresight_device *csdev, void *data); | |
342 | int (*disable)(struct coresight_device *csdev, void *data); | |
343 | }; | |
344 | ||
835d722b ML |
345 | /** |
346 | * struct coresight_ops_ect - Ops for an embedded cross trigger device | |
347 | * | |
348 | * @enable : Enable the device | |
349 | * @disable : Disable the device | |
350 | */ | |
351 | struct coresight_ops_ect { | |
352 | int (*enable)(struct coresight_device *csdev); | |
353 | int (*disable)(struct coresight_device *csdev); | |
354 | }; | |
355 | ||
a06ae860 PP |
356 | struct coresight_ops { |
357 | const struct coresight_ops_sink *sink_ops; | |
358 | const struct coresight_ops_link *link_ops; | |
359 | const struct coresight_ops_source *source_ops; | |
8a091d84 | 360 | const struct coresight_ops_helper *helper_ops; |
835d722b | 361 | const struct coresight_ops_ect *ect_ops; |
a06ae860 PP |
362 | }; |
363 | ||
b8127113 | 364 | #if IS_ENABLED(CONFIG_CORESIGHT) |
6e736c60 SP |
365 | |
366 | static inline u32 csdev_access_relaxed_read32(struct csdev_access *csa, | |
367 | u32 offset) | |
368 | { | |
369 | if (likely(csa->io_mem)) | |
370 | return readl_relaxed(csa->base + offset); | |
371 | ||
372 | return csa->read(offset, true, false); | |
373 | } | |
374 | ||
375 | static inline u32 csdev_access_read32(struct csdev_access *csa, u32 offset) | |
376 | { | |
377 | if (likely(csa->io_mem)) | |
378 | return readl(csa->base + offset); | |
379 | ||
380 | return csa->read(offset, false, false); | |
381 | } | |
382 | ||
383 | static inline void csdev_access_relaxed_write32(struct csdev_access *csa, | |
384 | u32 val, u32 offset) | |
385 | { | |
386 | if (likely(csa->io_mem)) | |
387 | writel_relaxed(val, csa->base + offset); | |
388 | else | |
389 | csa->write(val, offset, true, false); | |
390 | } | |
391 | ||
392 | static inline void csdev_access_write32(struct csdev_access *csa, u32 val, u32 offset) | |
393 | { | |
394 | if (likely(csa->io_mem)) | |
395 | writel(val, csa->base + offset); | |
396 | else | |
397 | csa->write(val, offset, false, false); | |
398 | } | |
399 | ||
400 | #ifdef CONFIG_64BIT | |
401 | ||
402 | static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa, | |
403 | u32 offset) | |
404 | { | |
405 | if (likely(csa->io_mem)) | |
406 | return readq_relaxed(csa->base + offset); | |
407 | ||
408 | return csa->read(offset, true, true); | |
409 | } | |
410 | ||
411 | static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset) | |
412 | { | |
413 | if (likely(csa->io_mem)) | |
414 | return readq(csa->base + offset); | |
415 | ||
416 | return csa->read(offset, false, true); | |
417 | } | |
418 | ||
419 | static inline void csdev_access_relaxed_write64(struct csdev_access *csa, | |
420 | u64 val, u32 offset) | |
421 | { | |
422 | if (likely(csa->io_mem)) | |
423 | writeq_relaxed(val, csa->base + offset); | |
424 | else | |
425 | csa->write(val, offset, true, true); | |
426 | } | |
427 | ||
428 | static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset) | |
429 | { | |
430 | if (likely(csa->io_mem)) | |
431 | writeq(val, csa->base + offset); | |
432 | else | |
433 | csa->write(val, offset, false, true); | |
434 | } | |
435 | ||
436 | #else /* !CONFIG_64BIT */ | |
437 | ||
438 | static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa, | |
439 | u32 offset) | |
440 | { | |
441 | WARN_ON(1); | |
442 | return 0; | |
443 | } | |
444 | ||
445 | static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset) | |
446 | { | |
447 | WARN_ON(1); | |
448 | return 0; | |
449 | } | |
450 | ||
451 | static inline void csdev_access_relaxed_write64(struct csdev_access *csa, | |
452 | u64 val, u32 offset) | |
453 | { | |
454 | WARN_ON(1); | |
455 | } | |
456 | ||
457 | static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset) | |
458 | { | |
459 | WARN_ON(1); | |
460 | } | |
461 | #endif /* CONFIG_64BIT */ | |
462 | ||
2cd87a7b AK |
463 | static inline bool coresight_is_percpu_source(struct coresight_device *csdev) |
464 | { | |
465 | return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SOURCE) && | |
466 | (csdev->subtype.source_subtype == CORESIGHT_DEV_SUBTYPE_SOURCE_PROC); | |
467 | } | |
468 | ||
469 | static inline bool coresight_is_percpu_sink(struct coresight_device *csdev) | |
470 | { | |
471 | return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SINK) && | |
472 | (csdev->subtype.sink_subtype == CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM); | |
473 | } | |
474 | ||
a06ae860 PP |
475 | extern struct coresight_device * |
476 | coresight_register(struct coresight_desc *desc); | |
477 | extern void coresight_unregister(struct coresight_device *csdev); | |
478 | extern int coresight_enable(struct coresight_device *csdev); | |
479 | extern void coresight_disable(struct coresight_device *csdev); | |
02005282 | 480 | extern int coresight_timeout(struct csdev_access *csa, u32 offset, |
a06ae860 | 481 | int position, int value); |
2478a6ae | 482 | |
8ce00296 SP |
483 | extern int coresight_claim_device(struct coresight_device *csdev); |
484 | extern int coresight_claim_device_unlocked(struct coresight_device *csdev); | |
2478a6ae | 485 | |
8ce00296 SP |
486 | extern void coresight_disclaim_device(struct coresight_device *csdev); |
487 | extern void coresight_disclaim_device_unlocked(struct coresight_device *csdev); | |
0f5f9b6b SP |
488 | extern char *coresight_alloc_device_name(struct coresight_dev_list *devs, |
489 | struct device *dev); | |
f188b5e7 AM |
490 | |
491 | extern bool coresight_loses_context_with_cpu(struct device *dev); | |
6e736c60 SP |
492 | |
493 | u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset); | |
494 | u32 coresight_read32(struct coresight_device *csdev, u32 offset); | |
495 | void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset); | |
496 | void coresight_relaxed_write32(struct coresight_device *csdev, | |
497 | u32 val, u32 offset); | |
498 | u64 coresight_relaxed_read64(struct coresight_device *csdev, u32 offset); | |
499 | u64 coresight_read64(struct coresight_device *csdev, u32 offset); | |
500 | void coresight_relaxed_write64(struct coresight_device *csdev, | |
501 | u64 val, u32 offset); | |
502 | void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset); | |
503 | ||
a06ae860 PP |
504 | #else |
505 | static inline struct coresight_device * | |
506 | coresight_register(struct coresight_desc *desc) { return NULL; } | |
507 | static inline void coresight_unregister(struct coresight_device *csdev) {} | |
508 | static inline int | |
509 | coresight_enable(struct coresight_device *csdev) { return -ENOSYS; } | |
510 | static inline void coresight_disable(struct coresight_device *csdev) {} | |
02005282 SP |
511 | |
512 | static inline int coresight_timeout(struct csdev_access *csa, u32 offset, | |
513 | int position, int value) | |
514 | { | |
515 | return 1; | |
516 | } | |
517 | ||
8ce00296 | 518 | static inline int coresight_claim_device_unlocked(struct coresight_device *csdev) |
2478a6ae SP |
519 | { |
520 | return -EINVAL; | |
521 | } | |
522 | ||
8ce00296 | 523 | static inline int coresight_claim_device(struct coresight_device *csdev) |
2478a6ae SP |
524 | { |
525 | return -EINVAL; | |
526 | } | |
527 | ||
8ce00296 SP |
528 | static inline void coresight_disclaim_device(struct coresight_device *csdev) {} |
529 | static inline void coresight_disclaim_device_unlocked(struct coresight_device *csdev) {} | |
2478a6ae | 530 | |
f188b5e7 AM |
531 | static inline bool coresight_loses_context_with_cpu(struct device *dev) |
532 | { | |
533 | return false; | |
534 | } | |
6e736c60 SP |
535 | |
536 | static inline u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset) | |
537 | { | |
538 | WARN_ON_ONCE(1); | |
539 | return 0; | |
540 | } | |
541 | ||
542 | static inline u32 coresight_read32(struct coresight_device *csdev, u32 offset) | |
543 | { | |
544 | WARN_ON_ONCE(1); | |
545 | return 0; | |
546 | } | |
547 | ||
548 | static inline void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset) | |
549 | { | |
550 | } | |
551 | ||
552 | static inline void coresight_relaxed_write32(struct coresight_device *csdev, | |
553 | u32 val, u32 offset) | |
554 | { | |
555 | } | |
556 | ||
557 | static inline u64 coresight_relaxed_read64(struct coresight_device *csdev, | |
558 | u32 offset) | |
559 | { | |
560 | WARN_ON_ONCE(1); | |
561 | return 0; | |
562 | } | |
563 | ||
564 | static inline u64 coresight_read64(struct coresight_device *csdev, u32 offset) | |
565 | { | |
566 | WARN_ON_ONCE(1); | |
567 | return 0; | |
568 | } | |
569 | ||
570 | static inline void coresight_relaxed_write64(struct coresight_device *csdev, | |
571 | u64 val, u32 offset) | |
572 | { | |
573 | } | |
574 | ||
575 | static inline void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset) | |
576 | { | |
577 | } | |
578 | ||
579 | #endif /* IS_ENABLED(CONFIG_CORESIGHT) */ | |
c61c4b5d | 580 | |
91824db2 | 581 | extern int coresight_get_cpu(struct device *dev); |
a06ae860 | 582 | |
f03631da SP |
583 | struct coresight_platform_data *coresight_get_platform_data(struct device *dev); |
584 | ||
6e736c60 | 585 | #endif /* _LINUX_COREISGHT_H */ |