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ebafb63d | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
b2476490 | 2 | /* |
b2476490 MT |
3 | * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com> |
4 | * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org> | |
b2476490 MT |
5 | */ |
6 | #ifndef __LINUX_CLK_PROVIDER_H | |
7 | #define __LINUX_CLK_PROVIDER_H | |
8 | ||
355bb165 | 9 | #include <linux/of.h> |
eb06d6bb | 10 | #include <linux/of_clk.h> |
b2476490 | 11 | |
b2476490 MT |
12 | /* |
13 | * flags used across common struct clk. these flags should only affect the | |
14 | * top-level framework. custom flags for dealing with hardware specifics | |
15 | * belong in struct clk_foo | |
a6059ab9 GU |
16 | * |
17 | * Please update clk_flags[] in drivers/clk/clk.c when making changes here! | |
b2476490 MT |
18 | */ |
19 | #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ | |
20 | #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ | |
21 | #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ | |
22 | #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ | |
b9610e74 | 23 | /* unused */ |
90b6c5c7 | 24 | /* unused */ |
a093bde2 | 25 | #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ |
819c1de3 | 26 | #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ |
5279fc40 | 27 | #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */ |
d8d91987 | 28 | #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */ |
2eb8c710 | 29 | #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */ |
32b9b109 | 30 | #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */ |
a4b3518d DA |
31 | /* parents need enable during gate/ungate, set rate and re-parent */ |
32 | #define CLK_OPS_PARENT_ENABLE BIT(12) | |
9fba738a JB |
33 | /* duty cycle call may be forwarded to the parent clock */ |
34 | #define CLK_DUTY_CYCLE_PARENT BIT(13) | |
b2476490 | 35 | |
61ae7656 | 36 | struct clk; |
0197b3ea | 37 | struct clk_hw; |
035a61c3 | 38 | struct clk_core; |
c646cbf1 | 39 | struct dentry; |
0197b3ea | 40 | |
0817b62c BB |
41 | /** |
42 | * struct clk_rate_request - Structure encoding the clk constraints that | |
43 | * a clock user might require. | |
44 | * | |
45 | * @rate: Requested clock rate. This field will be adjusted by | |
46 | * clock drivers according to hardware capabilities. | |
47 | * @min_rate: Minimum rate imposed by clk users. | |
1971dfb7 | 48 | * @max_rate: Maximum rate imposed by clk users. |
0817b62c BB |
49 | * @best_parent_rate: The best parent rate a parent can provide to fulfill the |
50 | * requested constraints. | |
51 | * @best_parent_hw: The most appropriate parent clock that fulfills the | |
52 | * requested constraints. | |
53 | * | |
54 | */ | |
55 | struct clk_rate_request { | |
56 | unsigned long rate; | |
57 | unsigned long min_rate; | |
58 | unsigned long max_rate; | |
59 | unsigned long best_parent_rate; | |
60 | struct clk_hw *best_parent_hw; | |
61 | }; | |
62 | ||
9fba738a JB |
63 | /** |
64 | * struct clk_duty - Struture encoding the duty cycle ratio of a clock | |
65 | * | |
66 | * @num: Numerator of the duty cycle ratio | |
67 | * @den: Denominator of the duty cycle ratio | |
68 | */ | |
69 | struct clk_duty { | |
70 | unsigned int num; | |
71 | unsigned int den; | |
72 | }; | |
73 | ||
b2476490 MT |
74 | /** |
75 | * struct clk_ops - Callback operations for hardware clocks; these are to | |
76 | * be provided by the clock implementation, and will be called by drivers | |
77 | * through the clk_* api. | |
78 | * | |
79 | * @prepare: Prepare the clock for enabling. This must not return until | |
725b418b GU |
80 | * the clock is fully prepared, and it's safe to call clk_enable. |
81 | * This callback is intended to allow clock implementations to | |
82 | * do any initialisation that may sleep. Called with | |
83 | * prepare_lock held. | |
b2476490 MT |
84 | * |
85 | * @unprepare: Release the clock from its prepared state. This will typically | |
725b418b GU |
86 | * undo any work done in the @prepare callback. Called with |
87 | * prepare_lock held. | |
b2476490 | 88 | * |
3d6ee287 UH |
89 | * @is_prepared: Queries the hardware to determine if the clock is prepared. |
90 | * This function is allowed to sleep. Optional, if this op is not | |
91 | * set then the prepare count will be used. | |
92 | * | |
3cc8247f UH |
93 | * @unprepare_unused: Unprepare the clock atomically. Only called from |
94 | * clk_disable_unused for prepare clocks with special needs. | |
95 | * Called with prepare mutex held. This function may sleep. | |
96 | * | |
b2476490 | 97 | * @enable: Enable the clock atomically. This must not return until the |
725b418b GU |
98 | * clock is generating a valid clock signal, usable by consumer |
99 | * devices. Called with enable_lock held. This function must not | |
100 | * sleep. | |
b2476490 MT |
101 | * |
102 | * @disable: Disable the clock atomically. Called with enable_lock held. | |
725b418b | 103 | * This function must not sleep. |
b2476490 | 104 | * |
119c7127 | 105 | * @is_enabled: Queries the hardware to determine if the clock is enabled. |
725b418b GU |
106 | * This function must not sleep. Optional, if this op is not |
107 | * set then the enable count will be used. | |
119c7127 | 108 | * |
7c045a55 MT |
109 | * @disable_unused: Disable the clock atomically. Only called from |
110 | * clk_disable_unused for gate clocks with special needs. | |
111 | * Called with enable_lock held. This function must not | |
112 | * sleep. | |
113 | * | |
8b95d1ce RD |
114 | * @save_context: Save the context of the clock in prepration for poweroff. |
115 | * | |
116 | * @restore_context: Restore the context of the clock after a restoration | |
117 | * of power. | |
118 | * | |
7ce3e8cc | 119 | * @recalc_rate Recalculate the rate of this clock, by querying hardware. The |
725b418b GU |
120 | * parent rate is an input parameter. It is up to the caller to |
121 | * ensure that the prepare_mutex is held across this call. | |
122 | * Returns the calculated rate. Optional, but recommended - if | |
123 | * this op is not set then clock rate will be initialized to 0. | |
b2476490 MT |
124 | * |
125 | * @round_rate: Given a target rate as input, returns the closest rate actually | |
54e73016 GU |
126 | * supported by the clock. The parent rate is an input/output |
127 | * parameter. | |
b2476490 | 128 | * |
71472c0c JH |
129 | * @determine_rate: Given a target rate as input, returns the closest rate |
130 | * actually supported by the clock, and optionally the parent clock | |
131 | * that should be used to provide the clock rate. | |
132 | * | |
b2476490 | 133 | * @set_parent: Change the input source of this clock; for clocks with multiple |
54e73016 GU |
134 | * possible parents specify a new parent by passing in the index |
135 | * as a u8 corresponding to the parent in either the .parent_names | |
136 | * or .parents arrays. This function in affect translates an | |
137 | * array index into the value programmed into the hardware. | |
138 | * Returns 0 on success, -EERROR otherwise. | |
139 | * | |
b2476490 | 140 | * @get_parent: Queries the hardware to determine the parent of a clock. The |
725b418b GU |
141 | * return value is a u8 which specifies the index corresponding to |
142 | * the parent clock. This index can be applied to either the | |
143 | * .parent_names or .parents arrays. In short, this function | |
144 | * translates the parent value read from hardware into an array | |
145 | * index. Currently only called when the clock is initialized by | |
146 | * __clk_init. This callback is mandatory for clocks with | |
147 | * multiple parents. It is optional (and unnecessary) for clocks | |
148 | * with 0 or 1 parents. | |
b2476490 | 149 | * |
1c0035d7 SG |
150 | * @set_rate: Change the rate of this clock. The requested rate is specified |
151 | * by the second argument, which should typically be the return | |
152 | * of .round_rate call. The third argument gives the parent rate | |
153 | * which is likely helpful for most .set_rate implementation. | |
154 | * Returns 0 on success, -EERROR otherwise. | |
b2476490 | 155 | * |
3fa2252b SB |
156 | * @set_rate_and_parent: Change the rate and the parent of this clock. The |
157 | * requested rate is specified by the second argument, which | |
158 | * should typically be the return of .round_rate call. The | |
159 | * third argument gives the parent rate which is likely helpful | |
160 | * for most .set_rate_and_parent implementation. The fourth | |
161 | * argument gives the parent index. This callback is optional (and | |
162 | * unnecessary) for clocks with 0 or 1 parents as well as | |
163 | * for clocks that can tolerate switching the rate and the parent | |
164 | * separately via calls to .set_parent and .set_rate. | |
165 | * Returns 0 on success, -EERROR otherwise. | |
166 | * | |
54e73016 GU |
167 | * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy |
168 | * is expressed in ppb (parts per billion). The parent accuracy is | |
169 | * an input parameter. | |
170 | * Returns the calculated accuracy. Optional - if this op is not | |
171 | * set then clock accuracy will be initialized to parent accuracy | |
172 | * or 0 (perfect clock) if clock has no parent. | |
173 | * | |
9824cf73 MR |
174 | * @get_phase: Queries the hardware to get the current phase of a clock. |
175 | * Returned values are 0-359 degrees on success, negative | |
176 | * error codes on failure. | |
177 | * | |
e59c5371 MT |
178 | * @set_phase: Shift the phase this clock signal in degrees specified |
179 | * by the second argument. Valid values for degrees are | |
180 | * 0-359. Return 0 on success, otherwise -EERROR. | |
181 | * | |
9fba738a JB |
182 | * @get_duty_cycle: Queries the hardware to get the current duty cycle ratio |
183 | * of a clock. Returned values denominator cannot be 0 and must be | |
184 | * superior or equal to the numerator. | |
185 | * | |
186 | * @set_duty_cycle: Apply the duty cycle ratio to this clock signal specified by | |
187 | * the numerator (2nd argurment) and denominator (3rd argument). | |
188 | * Argument must be a valid ratio (denominator > 0 | |
189 | * and >= numerator) Return 0 on success, otherwise -EERROR. | |
190 | * | |
54e73016 GU |
191 | * @init: Perform platform-specific initialization magic. |
192 | * This is not not used by any of the basic clock types. | |
193 | * Please consider other ways of solving initialization problems | |
194 | * before using this callback, as its use is discouraged. | |
195 | * | |
c646cbf1 AE |
196 | * @debug_init: Set up type-specific debugfs entries for this clock. This |
197 | * is called once, after the debugfs directory entry for this | |
198 | * clock has been created. The dentry pointer representing that | |
199 | * directory is provided as an argument. Called with | |
200 | * prepare_lock held. Returns 0 on success, -EERROR otherwise. | |
201 | * | |
3fa2252b | 202 | * |
b2476490 MT |
203 | * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow |
204 | * implementations to split any work between atomic (enable) and sleepable | |
205 | * (prepare) contexts. If enabling a clock requires code that might sleep, | |
206 | * this must be done in clk_prepare. Clock enable code that will never be | |
7ce3e8cc | 207 | * called in a sleepable context may be implemented in clk_enable. |
b2476490 MT |
208 | * |
209 | * Typically, drivers will call clk_prepare when a clock may be needed later | |
210 | * (eg. when a device is opened), and clk_enable when the clock is actually | |
211 | * required (eg. from an interrupt). Note that clk_prepare MUST have been | |
212 | * called before clk_enable. | |
213 | */ | |
214 | struct clk_ops { | |
215 | int (*prepare)(struct clk_hw *hw); | |
216 | void (*unprepare)(struct clk_hw *hw); | |
3d6ee287 | 217 | int (*is_prepared)(struct clk_hw *hw); |
3cc8247f | 218 | void (*unprepare_unused)(struct clk_hw *hw); |
b2476490 MT |
219 | int (*enable)(struct clk_hw *hw); |
220 | void (*disable)(struct clk_hw *hw); | |
221 | int (*is_enabled)(struct clk_hw *hw); | |
7c045a55 | 222 | void (*disable_unused)(struct clk_hw *hw); |
8b95d1ce RD |
223 | int (*save_context)(struct clk_hw *hw); |
224 | void (*restore_context)(struct clk_hw *hw); | |
b2476490 MT |
225 | unsigned long (*recalc_rate)(struct clk_hw *hw, |
226 | unsigned long parent_rate); | |
54e73016 GU |
227 | long (*round_rate)(struct clk_hw *hw, unsigned long rate, |
228 | unsigned long *parent_rate); | |
0817b62c BB |
229 | int (*determine_rate)(struct clk_hw *hw, |
230 | struct clk_rate_request *req); | |
b2476490 MT |
231 | int (*set_parent)(struct clk_hw *hw, u8 index); |
232 | u8 (*get_parent)(struct clk_hw *hw); | |
54e73016 GU |
233 | int (*set_rate)(struct clk_hw *hw, unsigned long rate, |
234 | unsigned long parent_rate); | |
3fa2252b SB |
235 | int (*set_rate_and_parent)(struct clk_hw *hw, |
236 | unsigned long rate, | |
237 | unsigned long parent_rate, u8 index); | |
5279fc40 BB |
238 | unsigned long (*recalc_accuracy)(struct clk_hw *hw, |
239 | unsigned long parent_accuracy); | |
9824cf73 | 240 | int (*get_phase)(struct clk_hw *hw); |
e59c5371 | 241 | int (*set_phase)(struct clk_hw *hw, int degrees); |
9fba738a JB |
242 | int (*get_duty_cycle)(struct clk_hw *hw, |
243 | struct clk_duty *duty); | |
244 | int (*set_duty_cycle)(struct clk_hw *hw, | |
245 | struct clk_duty *duty); | |
b2476490 | 246 | void (*init)(struct clk_hw *hw); |
d75d50c0 | 247 | void (*debug_init)(struct clk_hw *hw, struct dentry *dentry); |
b2476490 MT |
248 | }; |
249 | ||
fc0c209c SB |
250 | /** |
251 | * struct clk_parent_data - clk parent information | |
252 | * @hw: parent clk_hw pointer (used for clk providers with internal clks) | |
253 | * @fw_name: parent name local to provider registering clk | |
254 | * @name: globally unique parent name (used as a fallback) | |
601b6e93 | 255 | * @index: parent index local to provider registering clk (if @fw_name absent) |
fc0c209c SB |
256 | */ |
257 | struct clk_parent_data { | |
258 | const struct clk_hw *hw; | |
259 | const char *fw_name; | |
260 | const char *name; | |
601b6e93 | 261 | int index; |
fc0c209c SB |
262 | }; |
263 | ||
0197b3ea SK |
264 | /** |
265 | * struct clk_init_data - holds init data that's common to all clocks and is | |
266 | * shared between the clock provider and the common clock framework. | |
267 | * | |
268 | * @name: clock name | |
269 | * @ops: operations this clock supports | |
270 | * @parent_names: array of string names for all possible parents | |
fc0c209c SB |
271 | * @parent_data: array of parent data for all possible parents (when some |
272 | * parents are external to the clk controller) | |
273 | * @parent_hws: array of pointers to all possible parents (when all parents | |
274 | * are internal to the clk controller) | |
0197b3ea SK |
275 | * @num_parents: number of possible parents |
276 | * @flags: framework-level hints and quirks | |
277 | */ | |
278 | struct clk_init_data { | |
279 | const char *name; | |
280 | const struct clk_ops *ops; | |
fc0c209c | 281 | /* Only one of the following three should be assigned */ |
2893c379 | 282 | const char * const *parent_names; |
fc0c209c SB |
283 | const struct clk_parent_data *parent_data; |
284 | const struct clk_hw **parent_hws; | |
0197b3ea SK |
285 | u8 num_parents; |
286 | unsigned long flags; | |
287 | }; | |
288 | ||
289 | /** | |
290 | * struct clk_hw - handle for traversing from a struct clk to its corresponding | |
291 | * hardware-specific structure. struct clk_hw should be declared within struct | |
292 | * clk_foo and then referenced by the struct clk instance that uses struct | |
293 | * clk_foo's clk_ops | |
294 | * | |
035a61c3 TV |
295 | * @core: pointer to the struct clk_core instance that points back to this |
296 | * struct clk_hw instance | |
297 | * | |
298 | * @clk: pointer to the per-user struct clk instance that can be used to call | |
299 | * into the clk API | |
0197b3ea SK |
300 | * |
301 | * @init: pointer to struct clk_init_data that contains the init data shared | |
0214f33c SB |
302 | * with the common clock framework. This pointer will be set to NULL once |
303 | * a clk_register() variant is called on this clk_hw pointer. | |
0197b3ea SK |
304 | */ |
305 | struct clk_hw { | |
035a61c3 | 306 | struct clk_core *core; |
0197b3ea | 307 | struct clk *clk; |
dc4cd941 | 308 | const struct clk_init_data *init; |
0197b3ea SK |
309 | }; |
310 | ||
9d9f78ed MT |
311 | /* |
312 | * DOC: Basic clock implementations common to many platforms | |
313 | * | |
314 | * Each basic clock hardware type is comprised of a structure describing the | |
315 | * clock hardware, implementations of the relevant callbacks in struct clk_ops, | |
316 | * unique flags for that hardware type, a registration function and an | |
317 | * alternative macro for static initialization | |
318 | */ | |
319 | ||
320 | /** | |
321 | * struct clk_fixed_rate - fixed-rate clock | |
322 | * @hw: handle between common and hardware-specific interfaces | |
323 | * @fixed_rate: constant frequency of clock | |
32205b75 | 324 | * @fixed_accuracy: constant accuracy of clock in ppb (parts per billion) |
2d34f09e | 325 | * @flags: hardware specific flags |
58f0c4ba SB |
326 | * |
327 | * Flags: | |
328 | * * CLK_FIXED_RATE_PARENT_ACCURACY - Use the accuracy of the parent clk | |
329 | * instead of what's set in @fixed_accuracy. | |
9d9f78ed MT |
330 | */ |
331 | struct clk_fixed_rate { | |
332 | struct clk_hw hw; | |
333 | unsigned long fixed_rate; | |
0903ea60 | 334 | unsigned long fixed_accuracy; |
2d34f09e | 335 | unsigned long flags; |
9d9f78ed MT |
336 | }; |
337 | ||
58f0c4ba SB |
338 | #define CLK_FIXED_RATE_PARENT_ACCURACY BIT(0) |
339 | ||
bffad66e | 340 | extern const struct clk_ops clk_fixed_rate_ops; |
2d34f09e SB |
341 | struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev, |
342 | struct device_node *np, const char *name, | |
343 | const char *parent_name, const struct clk_hw *parent_hw, | |
344 | const struct clk_parent_data *parent_data, unsigned long flags, | |
345 | unsigned long fixed_rate, unsigned long fixed_accuracy, | |
346 | unsigned long clk_fixed_flags); | |
9d9f78ed MT |
347 | struct clk *clk_register_fixed_rate(struct device *dev, const char *name, |
348 | const char *parent_name, unsigned long flags, | |
349 | unsigned long fixed_rate); | |
2d34f09e SB |
350 | /** |
351 | * clk_hw_register_fixed_rate - register fixed-rate clock with the clock | |
352 | * framework | |
353 | * @dev: device that is registering this clock | |
354 | * @name: name of this clock | |
355 | * @parent_name: name of clock's parent | |
356 | * @flags: framework-specific flags | |
357 | * @fixed_rate: non-adjustable clock rate | |
358 | */ | |
359 | #define clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate) \ | |
360 | __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \ | |
361 | NULL, (flags), (fixed_rate), 0, 0) | |
362 | /** | |
363 | * clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with | |
364 | * the clock framework | |
365 | * @dev: device that is registering this clock | |
366 | * @name: name of this clock | |
367 | * @parent_hw: pointer to parent clk | |
368 | * @flags: framework-specific flags | |
369 | * @fixed_rate: non-adjustable clock rate | |
370 | */ | |
371 | #define clk_hw_register_fixed_rate_parent_hw(dev, name, parent_hw, flags, \ | |
372 | fixed_rate) \ | |
373 | __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw), \ | |
374 | NULL, (flags), (fixed_rate), 0, 0) | |
375 | /** | |
376 | * clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with | |
377 | * the clock framework | |
378 | * @dev: device that is registering this clock | |
379 | * @name: name of this clock | |
380 | * @parent_data: parent clk data | |
381 | * @flags: framework-specific flags | |
382 | * @fixed_rate: non-adjustable clock rate | |
383 | */ | |
384 | #define clk_hw_register_fixed_rate_parent_data(dev, name, parent_hw, flags, \ | |
385 | fixed_rate) \ | |
386 | __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \ | |
387 | (parent_data), (flags), (fixed_rate), 0, \ | |
388 | 0) | |
389 | /** | |
390 | * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with | |
391 | * the clock framework | |
392 | * @dev: device that is registering this clock | |
393 | * @name: name of this clock | |
394 | * @parent_name: name of clock's parent | |
395 | * @flags: framework-specific flags | |
396 | * @fixed_rate: non-adjustable clock rate | |
1f1bb96d | 397 | * @fixed_accuracy: non-adjustable clock accuracy |
2d34f09e SB |
398 | */ |
399 | #define clk_hw_register_fixed_rate_with_accuracy(dev, name, parent_name, \ | |
400 | flags, fixed_rate, \ | |
401 | fixed_accuracy) \ | |
402 | __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), \ | |
403 | NULL, NULL, (flags), (fixed_rate), \ | |
404 | (fixed_accuracy), 0) | |
405 | /** | |
406 | * clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate | |
407 | * clock with the clock framework | |
408 | * @dev: device that is registering this clock | |
409 | * @name: name of this clock | |
410 | * @parent_hw: pointer to parent clk | |
411 | * @flags: framework-specific flags | |
412 | * @fixed_rate: non-adjustable clock rate | |
413 | * @fixed_accuracy: non-adjustable clock accuracy | |
414 | */ | |
415 | #define clk_hw_register_fixed_rate_with_accuracy_parent_hw(dev, name, \ | |
416 | parent_hw, flags, fixed_rate, fixed_accuracy) \ | |
417 | __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw) \ | |
418 | NULL, NULL, (flags), (fixed_rate), \ | |
419 | (fixed_accuracy), 0) | |
420 | /** | |
421 | * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate | |
422 | * clock with the clock framework | |
423 | * @dev: device that is registering this clock | |
424 | * @name: name of this clock | |
425 | * @parent_name: name of clock's parent | |
426 | * @flags: framework-specific flags | |
427 | * @fixed_rate: non-adjustable clock rate | |
428 | * @fixed_accuracy: non-adjustable clock accuracy | |
429 | */ | |
430 | #define clk_hw_register_fixed_rate_with_accuracy_parent_data(dev, name, \ | |
431 | parent_data, flags, fixed_rate, fixed_accuracy) \ | |
432 | __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \ | |
433 | (parent_data), NULL, (flags), \ | |
434 | (fixed_rate), (fixed_accuracy), 0) | |
435 | ||
0b225e41 | 436 | void clk_unregister_fixed_rate(struct clk *clk); |
52445637 | 437 | void clk_hw_unregister_fixed_rate(struct clk_hw *hw); |
26ef56be | 438 | |
015ba402 GL |
439 | void of_fixed_clk_setup(struct device_node *np); |
440 | ||
9d9f78ed MT |
441 | /** |
442 | * struct clk_gate - gating clock | |
443 | * | |
444 | * @hw: handle between common and hardware-specific interfaces | |
445 | * @reg: register controlling gate | |
446 | * @bit_idx: single bit controlling gate | |
447 | * @flags: hardware-specific flags | |
448 | * @lock: register lock | |
449 | * | |
450 | * Clock which can gate its output. Implements .enable & .disable | |
451 | * | |
452 | * Flags: | |
1f73f31a | 453 | * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to |
725b418b GU |
454 | * enable the clock. Setting this flag does the opposite: setting the bit |
455 | * disable the clock and clearing it enables the clock | |
04577994 | 456 | * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit |
725b418b GU |
457 | * of this register, and mask of gate bits are in higher 16-bit of this |
458 | * register. While setting the gate bits, higher 16-bit should also be | |
459 | * updated to indicate changing gate bits. | |
d1c8a501 JG |
460 | * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for |
461 | * the gate register. Setting this flag makes the register accesses big | |
462 | * endian. | |
9d9f78ed MT |
463 | */ |
464 | struct clk_gate { | |
465 | struct clk_hw hw; | |
466 | void __iomem *reg; | |
467 | u8 bit_idx; | |
468 | u8 flags; | |
469 | spinlock_t *lock; | |
9d9f78ed MT |
470 | }; |
471 | ||
5fd9c05c GT |
472 | #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw) |
473 | ||
9d9f78ed | 474 | #define CLK_GATE_SET_TO_DISABLE BIT(0) |
04577994 | 475 | #define CLK_GATE_HIWORD_MASK BIT(1) |
d1c8a501 | 476 | #define CLK_GATE_BIG_ENDIAN BIT(2) |
9d9f78ed | 477 | |
bffad66e | 478 | extern const struct clk_ops clk_gate_ops; |
194efb6e SB |
479 | struct clk_hw *__clk_hw_register_gate(struct device *dev, |
480 | struct device_node *np, const char *name, | |
481 | const char *parent_name, const struct clk_hw *parent_hw, | |
482 | const struct clk_parent_data *parent_data, | |
483 | unsigned long flags, | |
9d9f78ed MT |
484 | void __iomem *reg, u8 bit_idx, |
485 | u8 clk_gate_flags, spinlock_t *lock); | |
194efb6e | 486 | struct clk *clk_register_gate(struct device *dev, const char *name, |
e270d8cb SB |
487 | const char *parent_name, unsigned long flags, |
488 | void __iomem *reg, u8 bit_idx, | |
489 | u8 clk_gate_flags, spinlock_t *lock); | |
194efb6e SB |
490 | /** |
491 | * clk_hw_register_gate - register a gate clock with the clock framework | |
492 | * @dev: device that is registering this clock | |
493 | * @name: name of this clock | |
494 | * @parent_name: name of this clock's parent | |
495 | * @flags: framework-specific flags for this clock | |
496 | * @reg: register address to control gating of this clock | |
497 | * @bit_idx: which bit in the register controls gating of this clock | |
498 | * @clk_gate_flags: gate-specific flags for this clock | |
499 | * @lock: shared register lock for this clock | |
500 | */ | |
501 | #define clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx, \ | |
502 | clk_gate_flags, lock) \ | |
503 | __clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \ | |
504 | NULL, (flags), (reg), (bit_idx), \ | |
505 | (clk_gate_flags), (lock)) | |
506 | /** | |
507 | * clk_hw_register_gate_parent_hw - register a gate clock with the clock | |
508 | * framework | |
509 | * @dev: device that is registering this clock | |
510 | * @name: name of this clock | |
511 | * @parent_hw: pointer to parent clk | |
512 | * @flags: framework-specific flags for this clock | |
513 | * @reg: register address to control gating of this clock | |
514 | * @bit_idx: which bit in the register controls gating of this clock | |
515 | * @clk_gate_flags: gate-specific flags for this clock | |
516 | * @lock: shared register lock for this clock | |
517 | */ | |
518 | #define clk_hw_register_gate_parent_hw(dev, name, parent_name, flags, reg, \ | |
519 | bit_idx, clk_gate_flags, lock) \ | |
520 | __clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \ | |
521 | NULL, (flags), (reg), (bit_idx), \ | |
522 | (clk_gate_flags), (lock)) | |
523 | /** | |
524 | * clk_hw_register_gate_parent_data - register a gate clock with the clock | |
525 | * framework | |
526 | * @dev: device that is registering this clock | |
527 | * @name: name of this clock | |
528 | * @parent_data: parent clk data | |
529 | * @flags: framework-specific flags for this clock | |
530 | * @reg: register address to control gating of this clock | |
531 | * @bit_idx: which bit in the register controls gating of this clock | |
532 | * @clk_gate_flags: gate-specific flags for this clock | |
533 | * @lock: shared register lock for this clock | |
534 | */ | |
535 | #define clk_hw_register_gate_parent_data(dev, name, parent_name, flags, reg, \ | |
536 | bit_idx, clk_gate_flags, lock) \ | |
537 | __clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \ | |
538 | NULL, (flags), (reg), (bit_idx), \ | |
539 | (clk_gate_flags), (lock)) | |
4e3c021f | 540 | void clk_unregister_gate(struct clk *clk); |
e270d8cb | 541 | void clk_hw_unregister_gate(struct clk_hw *hw); |
0a9c869d | 542 | int clk_gate_is_enabled(struct clk_hw *hw); |
9d9f78ed | 543 | |
357c3f0a RN |
544 | struct clk_div_table { |
545 | unsigned int val; | |
546 | unsigned int div; | |
547 | }; | |
548 | ||
9d9f78ed MT |
549 | /** |
550 | * struct clk_divider - adjustable divider clock | |
551 | * | |
552 | * @hw: handle between common and hardware-specific interfaces | |
553 | * @reg: register containing the divider | |
554 | * @shift: shift to the divider bit field | |
555 | * @width: width of the divider bit field | |
357c3f0a | 556 | * @table: array of value/divider pairs, last entry should have div = 0 |
9d9f78ed MT |
557 | * @lock: register lock |
558 | * | |
559 | * Clock with an adjustable divider affecting its output frequency. Implements | |
560 | * .recalc_rate, .set_rate and .round_rate | |
561 | * | |
562 | * Flags: | |
563 | * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the | |
725b418b GU |
564 | * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is |
565 | * the raw value read from the register, with the value of zero considered | |
056b2053 | 566 | * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set. |
9d9f78ed | 567 | * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from |
725b418b | 568 | * the hardware register |
056b2053 SB |
569 | * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have |
570 | * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor. | |
571 | * Some hardware implementations gracefully handle this case and allow a | |
572 | * zero divisor by not modifying their input clock | |
573 | * (divide by one / bypass). | |
d57dfe75 | 574 | * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit |
725b418b GU |
575 | * of this register, and mask of divider bits are in higher 16-bit of this |
576 | * register. While setting the divider bits, higher 16-bit should also be | |
577 | * updated to indicate changing divider bits. | |
774b5143 MC |
578 | * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded |
579 | * to the closest integer instead of the up one. | |
79c6ab50 HS |
580 | * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should |
581 | * not be changed by the clock framework. | |
afe76c8f JQ |
582 | * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED |
583 | * except when the value read from the register is zero, the divisor is | |
584 | * 2^width of the field. | |
434d69fa JG |
585 | * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used |
586 | * for the divider register. Setting this flag makes the register accesses | |
587 | * big endian. | |
9d9f78ed MT |
588 | */ |
589 | struct clk_divider { | |
590 | struct clk_hw hw; | |
591 | void __iomem *reg; | |
592 | u8 shift; | |
593 | u8 width; | |
594 | u8 flags; | |
357c3f0a | 595 | const struct clk_div_table *table; |
9d9f78ed | 596 | spinlock_t *lock; |
9d9f78ed MT |
597 | }; |
598 | ||
e6d3cc7b | 599 | #define clk_div_mask(width) ((1 << (width)) - 1) |
5fd9c05c GT |
600 | #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) |
601 | ||
9d9f78ed MT |
602 | #define CLK_DIVIDER_ONE_BASED BIT(0) |
603 | #define CLK_DIVIDER_POWER_OF_TWO BIT(1) | |
056b2053 | 604 | #define CLK_DIVIDER_ALLOW_ZERO BIT(2) |
d57dfe75 | 605 | #define CLK_DIVIDER_HIWORD_MASK BIT(3) |
774b5143 | 606 | #define CLK_DIVIDER_ROUND_CLOSEST BIT(4) |
79c6ab50 | 607 | #define CLK_DIVIDER_READ_ONLY BIT(5) |
afe76c8f | 608 | #define CLK_DIVIDER_MAX_AT_ZERO BIT(6) |
434d69fa | 609 | #define CLK_DIVIDER_BIG_ENDIAN BIT(7) |
9d9f78ed | 610 | |
bffad66e | 611 | extern const struct clk_ops clk_divider_ops; |
50359819 | 612 | extern const struct clk_ops clk_divider_ro_ops; |
bca9690b SB |
613 | |
614 | unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate, | |
615 | unsigned int val, const struct clk_div_table *table, | |
12a26c29 | 616 | unsigned long flags, unsigned long width); |
22833a91 MR |
617 | long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, |
618 | unsigned long rate, unsigned long *prate, | |
619 | const struct clk_div_table *table, | |
620 | u8 width, unsigned long flags); | |
b15ee490 JB |
621 | long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, |
622 | unsigned long rate, unsigned long *prate, | |
623 | const struct clk_div_table *table, u8 width, | |
624 | unsigned long flags, unsigned int val); | |
bca9690b SB |
625 | int divider_get_val(unsigned long rate, unsigned long parent_rate, |
626 | const struct clk_div_table *table, u8 width, | |
627 | unsigned long flags); | |
628 | ||
9d9f78ed MT |
629 | struct clk *clk_register_divider(struct device *dev, const char *name, |
630 | const char *parent_name, unsigned long flags, | |
631 | void __iomem *reg, u8 shift, u8 width, | |
632 | u8 clk_divider_flags, spinlock_t *lock); | |
eb7d264f SB |
633 | struct clk_hw *clk_hw_register_divider(struct device *dev, const char *name, |
634 | const char *parent_name, unsigned long flags, | |
635 | void __iomem *reg, u8 shift, u8 width, | |
636 | u8 clk_divider_flags, spinlock_t *lock); | |
357c3f0a RN |
637 | struct clk *clk_register_divider_table(struct device *dev, const char *name, |
638 | const char *parent_name, unsigned long flags, | |
639 | void __iomem *reg, u8 shift, u8 width, | |
640 | u8 clk_divider_flags, const struct clk_div_table *table, | |
641 | spinlock_t *lock); | |
eb7d264f SB |
642 | struct clk_hw *clk_hw_register_divider_table(struct device *dev, |
643 | const char *name, const char *parent_name, unsigned long flags, | |
644 | void __iomem *reg, u8 shift, u8 width, | |
645 | u8 clk_divider_flags, const struct clk_div_table *table, | |
646 | spinlock_t *lock); | |
4e3c021f | 647 | void clk_unregister_divider(struct clk *clk); |
eb7d264f | 648 | void clk_hw_unregister_divider(struct clk_hw *hw); |
9d9f78ed MT |
649 | |
650 | /** | |
651 | * struct clk_mux - multiplexer clock | |
652 | * | |
653 | * @hw: handle between common and hardware-specific interfaces | |
654 | * @reg: register controlling multiplexer | |
fe3f338f | 655 | * @table: array of register values corresponding to the parent index |
9d9f78ed | 656 | * @shift: shift to multiplexer bit field |
fe3f338f | 657 | * @mask: mask of mutliplexer bit field |
3566d40c | 658 | * @flags: hardware-specific flags |
9d9f78ed MT |
659 | * @lock: register lock |
660 | * | |
661 | * Clock with multiple selectable parents. Implements .get_parent, .set_parent | |
662 | * and .recalc_rate | |
663 | * | |
664 | * Flags: | |
665 | * CLK_MUX_INDEX_ONE - register index starts at 1, not 0 | |
1f73f31a | 666 | * CLK_MUX_INDEX_BIT - register index is a single bit (power of two) |
ba492e90 | 667 | * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this |
725b418b GU |
668 | * register, and mask of mux bits are in higher 16-bit of this register. |
669 | * While setting the mux bits, higher 16-bit should also be updated to | |
670 | * indicate changing mux bits. | |
31f6e870 SB |
671 | * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the |
672 | * .get_parent clk_op. | |
15a02c1f SB |
673 | * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired |
674 | * frequency. | |
3a727519 JG |
675 | * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for |
676 | * the mux register. Setting this flag makes the register accesses big | |
677 | * endian. | |
9d9f78ed MT |
678 | */ |
679 | struct clk_mux { | |
680 | struct clk_hw hw; | |
681 | void __iomem *reg; | |
ce4f3313 PDS |
682 | u32 *table; |
683 | u32 mask; | |
9d9f78ed | 684 | u8 shift; |
9d9f78ed MT |
685 | u8 flags; |
686 | spinlock_t *lock; | |
687 | }; | |
688 | ||
5fd9c05c GT |
689 | #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw) |
690 | ||
9d9f78ed MT |
691 | #define CLK_MUX_INDEX_ONE BIT(0) |
692 | #define CLK_MUX_INDEX_BIT BIT(1) | |
ba492e90 | 693 | #define CLK_MUX_HIWORD_MASK BIT(2) |
15a02c1f SB |
694 | #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */ |
695 | #define CLK_MUX_ROUND_CLOSEST BIT(4) | |
3a727519 | 696 | #define CLK_MUX_BIG_ENDIAN BIT(5) |
9d9f78ed | 697 | |
bffad66e | 698 | extern const struct clk_ops clk_mux_ops; |
c57acd14 | 699 | extern const struct clk_ops clk_mux_ro_ops; |
ce4f3313 | 700 | |
9611b3aa SB |
701 | struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np, |
702 | const char *name, u8 num_parents, | |
703 | const char * const *parent_names, | |
704 | const struct clk_hw **parent_hws, | |
705 | const struct clk_parent_data *parent_data, | |
706 | unsigned long flags, void __iomem *reg, u8 shift, u32 mask, | |
ce4f3313 | 707 | u8 clk_mux_flags, u32 *table, spinlock_t *lock); |
9611b3aa | 708 | struct clk *clk_register_mux_table(struct device *dev, const char *name, |
264b3171 | 709 | const char * const *parent_names, u8 num_parents, |
9611b3aa | 710 | unsigned long flags, void __iomem *reg, u8 shift, u32 mask, |
264b3171 | 711 | u8 clk_mux_flags, u32 *table, spinlock_t *lock); |
ce4f3313 | 712 | |
9611b3aa SB |
713 | #define clk_register_mux(dev, name, parent_names, num_parents, flags, reg, \ |
714 | shift, width, clk_mux_flags, lock) \ | |
715 | clk_register_mux_table((dev), (name), (parent_names), (num_parents), \ | |
716 | (flags), (reg), (shift), BIT((width)) - 1, \ | |
717 | (clk_mux_flags), NULL, (lock)) | |
718 | #define clk_hw_register_mux_table(dev, name, parent_names, num_parents, \ | |
719 | flags, reg, shift, mask, clk_mux_flags, \ | |
720 | table, lock) \ | |
721 | __clk_hw_register_mux((dev), NULL, (name), (num_parents), \ | |
722 | (parent_names), NULL, NULL, (flags), (reg), \ | |
723 | (shift), (mask), (clk_mux_flags), (table), \ | |
724 | (lock)) | |
725 | #define clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \ | |
726 | shift, width, clk_mux_flags, lock) \ | |
727 | __clk_hw_register_mux((dev), NULL, (name), (num_parents), \ | |
728 | (parent_names), NULL, NULL, (flags), (reg), \ | |
729 | (shift), BIT((width)) - 1, (clk_mux_flags), \ | |
730 | NULL, (lock)) | |
731 | #define clk_hw_register_mux_hws(dev, name, parent_hws, num_parents, flags, \ | |
732 | reg, shift, width, clk_mux_flags, lock) \ | |
733 | __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \ | |
734 | (parent_hws), NULL, (flags), (reg), (shift), \ | |
735 | BIT((width)) - 1, (clk_mux_flags), NULL, (lock)) | |
736 | #define clk_hw_register_mux_parent_data(dev, name, parent_data, num_parents, \ | |
737 | flags, reg, shift, width, \ | |
738 | clk_mux_flags, lock) \ | |
739 | __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \ | |
740 | (parent_data), (flags), (reg), (shift), \ | |
741 | BIT((width)) - 1, (clk_mux_flags), NULL, (lock)) | |
742 | ||
77deb66d JB |
743 | int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags, |
744 | unsigned int val); | |
745 | unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index); | |
746 | ||
4e3c021f | 747 | void clk_unregister_mux(struct clk *clk); |
264b3171 | 748 | void clk_hw_unregister_mux(struct clk_hw *hw); |
4e3c021f | 749 | |
79b16641 GC |
750 | void of_fixed_factor_clk_setup(struct device_node *node); |
751 | ||
f0948f59 SH |
752 | /** |
753 | * struct clk_fixed_factor - fixed multiplier and divider clock | |
754 | * | |
755 | * @hw: handle between common and hardware-specific interfaces | |
756 | * @mult: multiplier | |
757 | * @div: divider | |
758 | * | |
759 | * Clock with a fixed multiplier and divider. The output frequency is the | |
760 | * parent clock rate divided by div and multiplied by mult. | |
761 | * Implements .recalc_rate, .set_rate and .round_rate | |
762 | */ | |
763 | ||
764 | struct clk_fixed_factor { | |
765 | struct clk_hw hw; | |
766 | unsigned int mult; | |
767 | unsigned int div; | |
768 | }; | |
769 | ||
5fd9c05c GT |
770 | #define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw) |
771 | ||
3037e9ea | 772 | extern const struct clk_ops clk_fixed_factor_ops; |
f0948f59 SH |
773 | struct clk *clk_register_fixed_factor(struct device *dev, const char *name, |
774 | const char *parent_name, unsigned long flags, | |
775 | unsigned int mult, unsigned int div); | |
cbf9591f | 776 | void clk_unregister_fixed_factor(struct clk *clk); |
0759ac8a SB |
777 | struct clk_hw *clk_hw_register_fixed_factor(struct device *dev, |
778 | const char *name, const char *parent_name, unsigned long flags, | |
779 | unsigned int mult, unsigned int div); | |
780 | void clk_hw_unregister_fixed_factor(struct clk_hw *hw); | |
f0948f59 | 781 | |
e2d0e90f HK |
782 | /** |
783 | * struct clk_fractional_divider - adjustable fractional divider clock | |
784 | * | |
785 | * @hw: handle between common and hardware-specific interfaces | |
786 | * @reg: register containing the divider | |
787 | * @mshift: shift to the numerator bit field | |
788 | * @mwidth: width of the numerator bit field | |
789 | * @nshift: shift to the denominator bit field | |
790 | * @nwidth: width of the denominator bit field | |
791 | * @lock: register lock | |
792 | * | |
793 | * Clock with adjustable fractional divider affecting its output frequency. | |
e983da27 D |
794 | * |
795 | * Flags: | |
796 | * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator | |
797 | * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED | |
798 | * is set then the numerator and denominator are both the value read | |
799 | * plus one. | |
58a2b4c9 JG |
800 | * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are |
801 | * used for the divider register. Setting this flag makes the register | |
802 | * accesses big endian. | |
e2d0e90f | 803 | */ |
e2d0e90f HK |
804 | struct clk_fractional_divider { |
805 | struct clk_hw hw; | |
806 | void __iomem *reg; | |
807 | u8 mshift; | |
934e2536 | 808 | u8 mwidth; |
e2d0e90f HK |
809 | u32 mmask; |
810 | u8 nshift; | |
934e2536 | 811 | u8 nwidth; |
e2d0e90f HK |
812 | u32 nmask; |
813 | u8 flags; | |
ec52e462 EZ |
814 | void (*approximation)(struct clk_hw *hw, |
815 | unsigned long rate, unsigned long *parent_rate, | |
816 | unsigned long *m, unsigned long *n); | |
e2d0e90f HK |
817 | spinlock_t *lock; |
818 | }; | |
819 | ||
5fd9c05c GT |
820 | #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw) |
821 | ||
e983da27 | 822 | #define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0) |
58a2b4c9 | 823 | #define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1) |
e983da27 | 824 | |
e2d0e90f HK |
825 | extern const struct clk_ops clk_fractional_divider_ops; |
826 | struct clk *clk_register_fractional_divider(struct device *dev, | |
827 | const char *name, const char *parent_name, unsigned long flags, | |
828 | void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, | |
829 | u8 clk_divider_flags, spinlock_t *lock); | |
39b44cff SB |
830 | struct clk_hw *clk_hw_register_fractional_divider(struct device *dev, |
831 | const char *name, const char *parent_name, unsigned long flags, | |
832 | void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, | |
833 | u8 clk_divider_flags, spinlock_t *lock); | |
834 | void clk_hw_unregister_fractional_divider(struct clk_hw *hw); | |
e2d0e90f | 835 | |
f2e0a532 MR |
836 | /** |
837 | * struct clk_multiplier - adjustable multiplier clock | |
838 | * | |
839 | * @hw: handle between common and hardware-specific interfaces | |
840 | * @reg: register containing the multiplier | |
841 | * @shift: shift to the multiplier bit field | |
842 | * @width: width of the multiplier bit field | |
843 | * @lock: register lock | |
844 | * | |
845 | * Clock with an adjustable multiplier affecting its output frequency. | |
846 | * Implements .recalc_rate, .set_rate and .round_rate | |
847 | * | |
848 | * Flags: | |
849 | * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read | |
850 | * from the register, with 0 being a valid value effectively | |
851 | * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is | |
852 | * set, then a null multiplier will be considered as a bypass, | |
853 | * leaving the parent rate unmodified. | |
854 | * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be | |
855 | * rounded to the closest integer instead of the down one. | |
9427b71a JG |
856 | * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are |
857 | * used for the multiplier register. Setting this flag makes the register | |
858 | * accesses big endian. | |
f2e0a532 MR |
859 | */ |
860 | struct clk_multiplier { | |
861 | struct clk_hw hw; | |
862 | void __iomem *reg; | |
863 | u8 shift; | |
864 | u8 width; | |
865 | u8 flags; | |
866 | spinlock_t *lock; | |
867 | }; | |
868 | ||
5fd9c05c GT |
869 | #define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw) |
870 | ||
f2e0a532 MR |
871 | #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0) |
872 | #define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1) | |
9427b71a | 873 | #define CLK_MULTIPLIER_BIG_ENDIAN BIT(2) |
f2e0a532 MR |
874 | |
875 | extern const struct clk_ops clk_multiplier_ops; | |
876 | ||
ece70094 PG |
877 | /*** |
878 | * struct clk_composite - aggregate clock of mux, divider and gate clocks | |
879 | * | |
880 | * @hw: handle between common and hardware-specific interfaces | |
d3a1c7be MT |
881 | * @mux_hw: handle between composite and hardware-specific mux clock |
882 | * @rate_hw: handle between composite and hardware-specific rate clock | |
883 | * @gate_hw: handle between composite and hardware-specific gate clock | |
ece70094 | 884 | * @mux_ops: clock ops for mux |
d3a1c7be | 885 | * @rate_ops: clock ops for rate |
ece70094 PG |
886 | * @gate_ops: clock ops for gate |
887 | */ | |
888 | struct clk_composite { | |
889 | struct clk_hw hw; | |
890 | struct clk_ops ops; | |
891 | ||
892 | struct clk_hw *mux_hw; | |
d3a1c7be | 893 | struct clk_hw *rate_hw; |
ece70094 PG |
894 | struct clk_hw *gate_hw; |
895 | ||
896 | const struct clk_ops *mux_ops; | |
d3a1c7be | 897 | const struct clk_ops *rate_ops; |
ece70094 PG |
898 | const struct clk_ops *gate_ops; |
899 | }; | |
900 | ||
5fd9c05c GT |
901 | #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw) |
902 | ||
ece70094 | 903 | struct clk *clk_register_composite(struct device *dev, const char *name, |
2893c379 | 904 | const char * const *parent_names, int num_parents, |
ece70094 | 905 | struct clk_hw *mux_hw, const struct clk_ops *mux_ops, |
d3a1c7be | 906 | struct clk_hw *rate_hw, const struct clk_ops *rate_ops, |
ece70094 PG |
907 | struct clk_hw *gate_hw, const struct clk_ops *gate_ops, |
908 | unsigned long flags); | |
92a39d90 | 909 | void clk_unregister_composite(struct clk *clk); |
49cb392d SB |
910 | struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name, |
911 | const char * const *parent_names, int num_parents, | |
912 | struct clk_hw *mux_hw, const struct clk_ops *mux_ops, | |
913 | struct clk_hw *rate_hw, const struct clk_ops *rate_ops, | |
914 | struct clk_hw *gate_hw, const struct clk_ops *gate_ops, | |
915 | unsigned long flags); | |
916 | void clk_hw_unregister_composite(struct clk_hw *hw); | |
ece70094 | 917 | |
0197b3ea | 918 | struct clk *clk_register(struct device *dev, struct clk_hw *hw); |
46c8773a | 919 | struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw); |
b2476490 | 920 | |
4143804c SB |
921 | int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw); |
922 | int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw); | |
89a5ddcc | 923 | int __must_check of_clk_hw_register(struct device_node *node, struct clk_hw *hw); |
4143804c | 924 | |
1df5c939 | 925 | void clk_unregister(struct clk *clk); |
46c8773a | 926 | void devm_clk_unregister(struct device *dev, struct clk *clk); |
1df5c939 | 927 | |
4143804c SB |
928 | void clk_hw_unregister(struct clk_hw *hw); |
929 | void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw); | |
930 | ||
b2476490 | 931 | /* helper functions */ |
b76281cb | 932 | const char *__clk_get_name(const struct clk *clk); |
e7df6f6e | 933 | const char *clk_hw_get_name(const struct clk_hw *hw); |
1df37992 | 934 | #ifdef CONFIG_COMMON_CLK |
b2476490 | 935 | struct clk_hw *__clk_get_hw(struct clk *clk); |
1df37992 SR |
936 | #else |
937 | static inline struct clk_hw *__clk_get_hw(struct clk *clk) | |
938 | { | |
939 | return (struct clk_hw *)clk; | |
940 | } | |
941 | #endif | |
e7df6f6e SB |
942 | unsigned int clk_hw_get_num_parents(const struct clk_hw *hw); |
943 | struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw); | |
944 | struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw, | |
1a9c069c | 945 | unsigned int index); |
d9b86cc4 | 946 | int clk_hw_get_parent_index(struct clk_hw *hw); |
3567894b | 947 | int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *new_parent); |
93874681 | 948 | unsigned int __clk_get_enable_count(struct clk *clk); |
e7df6f6e | 949 | unsigned long clk_hw_get_rate(const struct clk_hw *hw); |
b2476490 | 950 | unsigned long __clk_get_flags(struct clk *clk); |
e7df6f6e | 951 | unsigned long clk_hw_get_flags(const struct clk_hw *hw); |
d13501a2 KS |
952 | #define clk_hw_can_set_rate_parent(hw) \ |
953 | (clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT) | |
954 | ||
e7df6f6e | 955 | bool clk_hw_is_prepared(const struct clk_hw *hw); |
e55a839a | 956 | bool clk_hw_rate_is_protected(const struct clk_hw *hw); |
be68bf88 | 957 | bool clk_hw_is_enabled(const struct clk_hw *hw); |
2ac6b1f5 | 958 | bool __clk_is_enabled(struct clk *clk); |
b2476490 | 959 | struct clk *__clk_lookup(const char *name); |
0817b62c BB |
960 | int __clk_mux_determine_rate(struct clk_hw *hw, |
961 | struct clk_rate_request *req); | |
962 | int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req); | |
963 | int __clk_mux_determine_rate_closest(struct clk_hw *hw, | |
964 | struct clk_rate_request *req); | |
4ad69b80 JB |
965 | int clk_mux_determine_rate_flags(struct clk_hw *hw, |
966 | struct clk_rate_request *req, | |
967 | unsigned long flags); | |
42c86547 | 968 | void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent); |
9783c0d9 SB |
969 | void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate, |
970 | unsigned long max_rate); | |
b2476490 | 971 | |
2e65d8bf JMC |
972 | static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src) |
973 | { | |
974 | dst->clk = src->clk; | |
975 | dst->core = src->core; | |
976 | } | |
977 | ||
22833a91 MR |
978 | static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate, |
979 | unsigned long *prate, | |
980 | const struct clk_div_table *table, | |
981 | u8 width, unsigned long flags) | |
982 | { | |
983 | return divider_round_rate_parent(hw, clk_hw_get_parent(hw), | |
984 | rate, prate, table, width, flags); | |
985 | } | |
986 | ||
b15ee490 JB |
987 | static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate, |
988 | unsigned long *prate, | |
989 | const struct clk_div_table *table, | |
990 | u8 width, unsigned long flags, | |
991 | unsigned int val) | |
992 | { | |
993 | return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw), | |
994 | rate, prate, table, width, flags, | |
995 | val); | |
996 | } | |
997 | ||
b2476490 MT |
998 | /* |
999 | * FIXME clock api without lock protection | |
1000 | */ | |
1a9c069c | 1001 | unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate); |
b2476490 | 1002 | |
0b151deb SH |
1003 | struct clk_onecell_data { |
1004 | struct clk **clks; | |
1005 | unsigned int clk_num; | |
1006 | }; | |
1007 | ||
0861e5b8 | 1008 | struct clk_hw_onecell_data { |
5963f19c | 1009 | unsigned int num; |
0861e5b8 SB |
1010 | struct clk_hw *hws[]; |
1011 | }; | |
1012 | ||
54196ccb | 1013 | #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn) |
0b151deb | 1014 | |
c7296c51 RRD |
1015 | /* |
1016 | * Use this macro when you have a driver that requires two initialization | |
1017 | * routines, one at of_clk_init(), and one at platform device probe | |
1018 | */ | |
1019 | #define CLK_OF_DECLARE_DRIVER(name, compat, fn) \ | |
339e1e54 | 1020 | static void __init name##_of_clk_init_driver(struct device_node *np) \ |
c7296c51 RRD |
1021 | { \ |
1022 | of_node_clear_flag(np, OF_POPULATED); \ | |
1023 | fn(np); \ | |
1024 | } \ | |
1025 | OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver) | |
1026 | ||
1ded879e CZ |
1027 | #define CLK_HW_INIT(_name, _parent, _ops, _flags) \ |
1028 | (&(struct clk_init_data) { \ | |
1029 | .flags = _flags, \ | |
1030 | .name = _name, \ | |
1031 | .parent_names = (const char *[]) { _parent }, \ | |
1032 | .num_parents = 1, \ | |
1033 | .ops = _ops, \ | |
1034 | }) | |
1035 | ||
99600fd4 CYT |
1036 | #define CLK_HW_INIT_HW(_name, _parent, _ops, _flags) \ |
1037 | (&(struct clk_init_data) { \ | |
1038 | .flags = _flags, \ | |
1039 | .name = _name, \ | |
1040 | .parent_hws = (const struct clk_hw*[]) { _parent }, \ | |
1041 | .num_parents = 1, \ | |
1042 | .ops = _ops, \ | |
1043 | }) | |
1044 | ||
1045 | /* | |
1046 | * This macro is intended for drivers to be able to share the otherwise | |
1047 | * individual struct clk_hw[] compound literals created by the compiler | |
1048 | * when using CLK_HW_INIT_HW. It does NOT support multiple parents. | |
1049 | */ | |
1050 | #define CLK_HW_INIT_HWS(_name, _parent, _ops, _flags) \ | |
1051 | (&(struct clk_init_data) { \ | |
1052 | .flags = _flags, \ | |
1053 | .name = _name, \ | |
1054 | .parent_hws = _parent, \ | |
1055 | .num_parents = 1, \ | |
1056 | .ops = _ops, \ | |
1057 | }) | |
1058 | ||
2d6b4f33 CYT |
1059 | #define CLK_HW_INIT_FW_NAME(_name, _parent, _ops, _flags) \ |
1060 | (&(struct clk_init_data) { \ | |
1061 | .flags = _flags, \ | |
1062 | .name = _name, \ | |
1063 | .parent_data = (const struct clk_parent_data[]) { \ | |
1064 | { .fw_name = _parent }, \ | |
1065 | }, \ | |
1066 | .num_parents = 1, \ | |
1067 | .ops = _ops, \ | |
1068 | }) | |
1069 | ||
1ded879e CZ |
1070 | #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \ |
1071 | (&(struct clk_init_data) { \ | |
1072 | .flags = _flags, \ | |
1073 | .name = _name, \ | |
1074 | .parent_names = _parents, \ | |
1075 | .num_parents = ARRAY_SIZE(_parents), \ | |
1076 | .ops = _ops, \ | |
1077 | }) | |
1078 | ||
99600fd4 CYT |
1079 | #define CLK_HW_INIT_PARENTS_HW(_name, _parents, _ops, _flags) \ |
1080 | (&(struct clk_init_data) { \ | |
1081 | .flags = _flags, \ | |
1082 | .name = _name, \ | |
1083 | .parent_hws = _parents, \ | |
1084 | .num_parents = ARRAY_SIZE(_parents), \ | |
1085 | .ops = _ops, \ | |
1086 | }) | |
1087 | ||
13933109 CYT |
1088 | #define CLK_HW_INIT_PARENTS_DATA(_name, _parents, _ops, _flags) \ |
1089 | (&(struct clk_init_data) { \ | |
1090 | .flags = _flags, \ | |
1091 | .name = _name, \ | |
1092 | .parent_data = _parents, \ | |
1093 | .num_parents = ARRAY_SIZE(_parents), \ | |
1094 | .ops = _ops, \ | |
1095 | }) | |
1096 | ||
1ded879e CZ |
1097 | #define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \ |
1098 | (&(struct clk_init_data) { \ | |
1099 | .flags = _flags, \ | |
1100 | .name = _name, \ | |
1101 | .parent_names = NULL, \ | |
1102 | .num_parents = 0, \ | |
1103 | .ops = _ops, \ | |
1104 | }) | |
1105 | ||
1106 | #define CLK_FIXED_FACTOR(_struct, _name, _parent, \ | |
1107 | _div, _mult, _flags) \ | |
1108 | struct clk_fixed_factor _struct = { \ | |
1109 | .div = _div, \ | |
1110 | .mult = _mult, \ | |
1111 | .hw.init = CLK_HW_INIT(_name, \ | |
1112 | _parent, \ | |
1113 | &clk_fixed_factor_ops, \ | |
1114 | _flags), \ | |
1115 | } | |
1116 | ||
d7b15114 CYT |
1117 | #define CLK_FIXED_FACTOR_HW(_struct, _name, _parent, \ |
1118 | _div, _mult, _flags) \ | |
1119 | struct clk_fixed_factor _struct = { \ | |
1120 | .div = _div, \ | |
1121 | .mult = _mult, \ | |
1122 | .hw.init = CLK_HW_INIT_HW(_name, \ | |
1123 | _parent, \ | |
1124 | &clk_fixed_factor_ops, \ | |
1125 | _flags), \ | |
1126 | } | |
1127 | ||
1bef004e CYT |
1128 | /* |
1129 | * This macro allows the driver to reuse the _parent array for multiple | |
1130 | * fixed factor clk declarations. | |
1131 | */ | |
1132 | #define CLK_FIXED_FACTOR_HWS(_struct, _name, _parent, \ | |
1133 | _div, _mult, _flags) \ | |
1134 | struct clk_fixed_factor _struct = { \ | |
1135 | .div = _div, \ | |
1136 | .mult = _mult, \ | |
1137 | .hw.init = CLK_HW_INIT_HWS(_name, \ | |
1138 | _parent, \ | |
1139 | &clk_fixed_factor_ops, \ | |
1140 | _flags), \ | |
1141 | } | |
1142 | ||
8b13a48b CYT |
1143 | #define CLK_FIXED_FACTOR_FW_NAME(_struct, _name, _parent, \ |
1144 | _div, _mult, _flags) \ | |
1145 | struct clk_fixed_factor _struct = { \ | |
1146 | .div = _div, \ | |
1147 | .mult = _mult, \ | |
1148 | .hw.init = CLK_HW_INIT_FW_NAME(_name, \ | |
1149 | _parent, \ | |
1150 | &clk_fixed_factor_ops, \ | |
1151 | _flags), \ | |
1152 | } | |
1153 | ||
0b151deb | 1154 | #ifdef CONFIG_OF |
766e6a4e GL |
1155 | int of_clk_add_provider(struct device_node *np, |
1156 | struct clk *(*clk_src_get)(struct of_phandle_args *args, | |
1157 | void *data), | |
1158 | void *data); | |
0861e5b8 SB |
1159 | int of_clk_add_hw_provider(struct device_node *np, |
1160 | struct clk_hw *(*get)(struct of_phandle_args *clkspec, | |
1161 | void *data), | |
1162 | void *data); | |
aa795c41 SB |
1163 | int devm_of_clk_add_hw_provider(struct device *dev, |
1164 | struct clk_hw *(*get)(struct of_phandle_args *clkspec, | |
1165 | void *data), | |
1166 | void *data); | |
766e6a4e | 1167 | void of_clk_del_provider(struct device_node *np); |
aa795c41 | 1168 | void devm_of_clk_del_provider(struct device *dev); |
766e6a4e GL |
1169 | struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, |
1170 | void *data); | |
0861e5b8 SB |
1171 | struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec, |
1172 | void *data); | |
494bfec9 | 1173 | struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data); |
0861e5b8 SB |
1174 | struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec, |
1175 | void *data); | |
2e61dfb3 DN |
1176 | int of_clk_parent_fill(struct device_node *np, const char **parents, |
1177 | unsigned int size); | |
d56f8994 LJ |
1178 | int of_clk_detect_critical(struct device_node *np, int index, |
1179 | unsigned long *flags); | |
766e6a4e | 1180 | |
0b151deb | 1181 | #else /* !CONFIG_OF */ |
f2f6c255 | 1182 | |
0b151deb SH |
1183 | static inline int of_clk_add_provider(struct device_node *np, |
1184 | struct clk *(*clk_src_get)(struct of_phandle_args *args, | |
1185 | void *data), | |
1186 | void *data) | |
1187 | { | |
1188 | return 0; | |
1189 | } | |
0861e5b8 SB |
1190 | static inline int of_clk_add_hw_provider(struct device_node *np, |
1191 | struct clk_hw *(*get)(struct of_phandle_args *clkspec, | |
1192 | void *data), | |
1193 | void *data) | |
1194 | { | |
1195 | return 0; | |
1196 | } | |
aa795c41 SB |
1197 | static inline int devm_of_clk_add_hw_provider(struct device *dev, |
1198 | struct clk_hw *(*get)(struct of_phandle_args *clkspec, | |
1199 | void *data), | |
1200 | void *data) | |
1201 | { | |
1202 | return 0; | |
1203 | } | |
20dd882a | 1204 | static inline void of_clk_del_provider(struct device_node *np) {} |
aa795c41 | 1205 | static inline void devm_of_clk_del_provider(struct device *dev) {} |
0b151deb SH |
1206 | static inline struct clk *of_clk_src_simple_get( |
1207 | struct of_phandle_args *clkspec, void *data) | |
1208 | { | |
1209 | return ERR_PTR(-ENOENT); | |
1210 | } | |
0861e5b8 SB |
1211 | static inline struct clk_hw * |
1212 | of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data) | |
1213 | { | |
1214 | return ERR_PTR(-ENOENT); | |
1215 | } | |
0b151deb SH |
1216 | static inline struct clk *of_clk_src_onecell_get( |
1217 | struct of_phandle_args *clkspec, void *data) | |
1218 | { | |
1219 | return ERR_PTR(-ENOENT); | |
1220 | } | |
0861e5b8 SB |
1221 | static inline struct clk_hw * |
1222 | of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data) | |
1223 | { | |
1224 | return ERR_PTR(-ENOENT); | |
1225 | } | |
679c51cf SB |
1226 | static inline int of_clk_parent_fill(struct device_node *np, |
1227 | const char **parents, unsigned int size) | |
1228 | { | |
1229 | return 0; | |
1230 | } | |
d56f8994 LJ |
1231 | static inline int of_clk_detect_critical(struct device_node *np, int index, |
1232 | unsigned long *flags) | |
1233 | { | |
1234 | return 0; | |
1235 | } | |
0b151deb | 1236 | #endif /* CONFIG_OF */ |
aa514ce3 | 1237 | |
43536548 K |
1238 | void clk_gate_restore_context(struct clk_hw *hw); |
1239 | ||
b2476490 | 1240 | #endif /* CLK_PROVIDER_H */ |