Commit | Line | Data |
---|---|---|
b2476490 MT |
1 | /* |
2 | * linux/include/linux/clk-provider.h | |
3 | * | |
4 | * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com> | |
5 | * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | #ifndef __LINUX_CLK_PROVIDER_H | |
12 | #define __LINUX_CLK_PROVIDER_H | |
13 | ||
aa514ce3 | 14 | #include <linux/io.h> |
355bb165 | 15 | #include <linux/of.h> |
b2476490 MT |
16 | |
17 | #ifdef CONFIG_COMMON_CLK | |
18 | ||
b2476490 MT |
19 | /* |
20 | * flags used across common struct clk. these flags should only affect the | |
21 | * top-level framework. custom flags for dealing with hardware specifics | |
22 | * belong in struct clk_foo | |
a6059ab9 GU |
23 | * |
24 | * Please update clk_flags[] in drivers/clk/clk.c when making changes here! | |
b2476490 MT |
25 | */ |
26 | #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ | |
27 | #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ | |
28 | #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ | |
29 | #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ | |
b9610e74 | 30 | /* unused */ |
f7d8caad | 31 | #define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */ |
a093bde2 | 32 | #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ |
819c1de3 | 33 | #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ |
5279fc40 | 34 | #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */ |
d8d91987 | 35 | #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */ |
2eb8c710 | 36 | #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */ |
32b9b109 | 37 | #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */ |
a4b3518d DA |
38 | /* parents need enable during gate/ungate, set rate and re-parent */ |
39 | #define CLK_OPS_PARENT_ENABLE BIT(12) | |
b2476490 | 40 | |
61ae7656 | 41 | struct clk; |
0197b3ea | 42 | struct clk_hw; |
035a61c3 | 43 | struct clk_core; |
c646cbf1 | 44 | struct dentry; |
0197b3ea | 45 | |
0817b62c BB |
46 | /** |
47 | * struct clk_rate_request - Structure encoding the clk constraints that | |
48 | * a clock user might require. | |
49 | * | |
50 | * @rate: Requested clock rate. This field will be adjusted by | |
51 | * clock drivers according to hardware capabilities. | |
52 | * @min_rate: Minimum rate imposed by clk users. | |
1971dfb7 | 53 | * @max_rate: Maximum rate imposed by clk users. |
0817b62c BB |
54 | * @best_parent_rate: The best parent rate a parent can provide to fulfill the |
55 | * requested constraints. | |
56 | * @best_parent_hw: The most appropriate parent clock that fulfills the | |
57 | * requested constraints. | |
58 | * | |
59 | */ | |
60 | struct clk_rate_request { | |
61 | unsigned long rate; | |
62 | unsigned long min_rate; | |
63 | unsigned long max_rate; | |
64 | unsigned long best_parent_rate; | |
65 | struct clk_hw *best_parent_hw; | |
66 | }; | |
67 | ||
b2476490 MT |
68 | /** |
69 | * struct clk_ops - Callback operations for hardware clocks; these are to | |
70 | * be provided by the clock implementation, and will be called by drivers | |
71 | * through the clk_* api. | |
72 | * | |
73 | * @prepare: Prepare the clock for enabling. This must not return until | |
725b418b GU |
74 | * the clock is fully prepared, and it's safe to call clk_enable. |
75 | * This callback is intended to allow clock implementations to | |
76 | * do any initialisation that may sleep. Called with | |
77 | * prepare_lock held. | |
b2476490 MT |
78 | * |
79 | * @unprepare: Release the clock from its prepared state. This will typically | |
725b418b GU |
80 | * undo any work done in the @prepare callback. Called with |
81 | * prepare_lock held. | |
b2476490 | 82 | * |
3d6ee287 UH |
83 | * @is_prepared: Queries the hardware to determine if the clock is prepared. |
84 | * This function is allowed to sleep. Optional, if this op is not | |
85 | * set then the prepare count will be used. | |
86 | * | |
3cc8247f UH |
87 | * @unprepare_unused: Unprepare the clock atomically. Only called from |
88 | * clk_disable_unused for prepare clocks with special needs. | |
89 | * Called with prepare mutex held. This function may sleep. | |
90 | * | |
b2476490 | 91 | * @enable: Enable the clock atomically. This must not return until the |
725b418b GU |
92 | * clock is generating a valid clock signal, usable by consumer |
93 | * devices. Called with enable_lock held. This function must not | |
94 | * sleep. | |
b2476490 MT |
95 | * |
96 | * @disable: Disable the clock atomically. Called with enable_lock held. | |
725b418b | 97 | * This function must not sleep. |
b2476490 | 98 | * |
119c7127 | 99 | * @is_enabled: Queries the hardware to determine if the clock is enabled. |
725b418b GU |
100 | * This function must not sleep. Optional, if this op is not |
101 | * set then the enable count will be used. | |
119c7127 | 102 | * |
7c045a55 MT |
103 | * @disable_unused: Disable the clock atomically. Only called from |
104 | * clk_disable_unused for gate clocks with special needs. | |
105 | * Called with enable_lock held. This function must not | |
106 | * sleep. | |
107 | * | |
7ce3e8cc | 108 | * @recalc_rate Recalculate the rate of this clock, by querying hardware. The |
725b418b GU |
109 | * parent rate is an input parameter. It is up to the caller to |
110 | * ensure that the prepare_mutex is held across this call. | |
111 | * Returns the calculated rate. Optional, but recommended - if | |
112 | * this op is not set then clock rate will be initialized to 0. | |
b2476490 MT |
113 | * |
114 | * @round_rate: Given a target rate as input, returns the closest rate actually | |
54e73016 GU |
115 | * supported by the clock. The parent rate is an input/output |
116 | * parameter. | |
b2476490 | 117 | * |
71472c0c JH |
118 | * @determine_rate: Given a target rate as input, returns the closest rate |
119 | * actually supported by the clock, and optionally the parent clock | |
120 | * that should be used to provide the clock rate. | |
121 | * | |
b2476490 | 122 | * @set_parent: Change the input source of this clock; for clocks with multiple |
54e73016 GU |
123 | * possible parents specify a new parent by passing in the index |
124 | * as a u8 corresponding to the parent in either the .parent_names | |
125 | * or .parents arrays. This function in affect translates an | |
126 | * array index into the value programmed into the hardware. | |
127 | * Returns 0 on success, -EERROR otherwise. | |
128 | * | |
b2476490 | 129 | * @get_parent: Queries the hardware to determine the parent of a clock. The |
725b418b GU |
130 | * return value is a u8 which specifies the index corresponding to |
131 | * the parent clock. This index can be applied to either the | |
132 | * .parent_names or .parents arrays. In short, this function | |
133 | * translates the parent value read from hardware into an array | |
134 | * index. Currently only called when the clock is initialized by | |
135 | * __clk_init. This callback is mandatory for clocks with | |
136 | * multiple parents. It is optional (and unnecessary) for clocks | |
137 | * with 0 or 1 parents. | |
b2476490 | 138 | * |
1c0035d7 SG |
139 | * @set_rate: Change the rate of this clock. The requested rate is specified |
140 | * by the second argument, which should typically be the return | |
141 | * of .round_rate call. The third argument gives the parent rate | |
142 | * which is likely helpful for most .set_rate implementation. | |
143 | * Returns 0 on success, -EERROR otherwise. | |
b2476490 | 144 | * |
3fa2252b SB |
145 | * @set_rate_and_parent: Change the rate and the parent of this clock. The |
146 | * requested rate is specified by the second argument, which | |
147 | * should typically be the return of .round_rate call. The | |
148 | * third argument gives the parent rate which is likely helpful | |
149 | * for most .set_rate_and_parent implementation. The fourth | |
150 | * argument gives the parent index. This callback is optional (and | |
151 | * unnecessary) for clocks with 0 or 1 parents as well as | |
152 | * for clocks that can tolerate switching the rate and the parent | |
153 | * separately via calls to .set_parent and .set_rate. | |
154 | * Returns 0 on success, -EERROR otherwise. | |
155 | * | |
54e73016 GU |
156 | * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy |
157 | * is expressed in ppb (parts per billion). The parent accuracy is | |
158 | * an input parameter. | |
159 | * Returns the calculated accuracy. Optional - if this op is not | |
160 | * set then clock accuracy will be initialized to parent accuracy | |
161 | * or 0 (perfect clock) if clock has no parent. | |
162 | * | |
9824cf73 MR |
163 | * @get_phase: Queries the hardware to get the current phase of a clock. |
164 | * Returned values are 0-359 degrees on success, negative | |
165 | * error codes on failure. | |
166 | * | |
e59c5371 MT |
167 | * @set_phase: Shift the phase this clock signal in degrees specified |
168 | * by the second argument. Valid values for degrees are | |
169 | * 0-359. Return 0 on success, otherwise -EERROR. | |
170 | * | |
54e73016 GU |
171 | * @init: Perform platform-specific initialization magic. |
172 | * This is not not used by any of the basic clock types. | |
173 | * Please consider other ways of solving initialization problems | |
174 | * before using this callback, as its use is discouraged. | |
175 | * | |
c646cbf1 AE |
176 | * @debug_init: Set up type-specific debugfs entries for this clock. This |
177 | * is called once, after the debugfs directory entry for this | |
178 | * clock has been created. The dentry pointer representing that | |
179 | * directory is provided as an argument. Called with | |
180 | * prepare_lock held. Returns 0 on success, -EERROR otherwise. | |
181 | * | |
3fa2252b | 182 | * |
b2476490 MT |
183 | * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow |
184 | * implementations to split any work between atomic (enable) and sleepable | |
185 | * (prepare) contexts. If enabling a clock requires code that might sleep, | |
186 | * this must be done in clk_prepare. Clock enable code that will never be | |
7ce3e8cc | 187 | * called in a sleepable context may be implemented in clk_enable. |
b2476490 MT |
188 | * |
189 | * Typically, drivers will call clk_prepare when a clock may be needed later | |
190 | * (eg. when a device is opened), and clk_enable when the clock is actually | |
191 | * required (eg. from an interrupt). Note that clk_prepare MUST have been | |
192 | * called before clk_enable. | |
193 | */ | |
194 | struct clk_ops { | |
195 | int (*prepare)(struct clk_hw *hw); | |
196 | void (*unprepare)(struct clk_hw *hw); | |
3d6ee287 | 197 | int (*is_prepared)(struct clk_hw *hw); |
3cc8247f | 198 | void (*unprepare_unused)(struct clk_hw *hw); |
b2476490 MT |
199 | int (*enable)(struct clk_hw *hw); |
200 | void (*disable)(struct clk_hw *hw); | |
201 | int (*is_enabled)(struct clk_hw *hw); | |
7c045a55 | 202 | void (*disable_unused)(struct clk_hw *hw); |
b2476490 MT |
203 | unsigned long (*recalc_rate)(struct clk_hw *hw, |
204 | unsigned long parent_rate); | |
54e73016 GU |
205 | long (*round_rate)(struct clk_hw *hw, unsigned long rate, |
206 | unsigned long *parent_rate); | |
0817b62c BB |
207 | int (*determine_rate)(struct clk_hw *hw, |
208 | struct clk_rate_request *req); | |
b2476490 MT |
209 | int (*set_parent)(struct clk_hw *hw, u8 index); |
210 | u8 (*get_parent)(struct clk_hw *hw); | |
54e73016 GU |
211 | int (*set_rate)(struct clk_hw *hw, unsigned long rate, |
212 | unsigned long parent_rate); | |
3fa2252b SB |
213 | int (*set_rate_and_parent)(struct clk_hw *hw, |
214 | unsigned long rate, | |
215 | unsigned long parent_rate, u8 index); | |
5279fc40 BB |
216 | unsigned long (*recalc_accuracy)(struct clk_hw *hw, |
217 | unsigned long parent_accuracy); | |
9824cf73 | 218 | int (*get_phase)(struct clk_hw *hw); |
e59c5371 | 219 | int (*set_phase)(struct clk_hw *hw, int degrees); |
b2476490 | 220 | void (*init)(struct clk_hw *hw); |
c646cbf1 | 221 | int (*debug_init)(struct clk_hw *hw, struct dentry *dentry); |
b2476490 MT |
222 | }; |
223 | ||
0197b3ea SK |
224 | /** |
225 | * struct clk_init_data - holds init data that's common to all clocks and is | |
226 | * shared between the clock provider and the common clock framework. | |
227 | * | |
228 | * @name: clock name | |
229 | * @ops: operations this clock supports | |
230 | * @parent_names: array of string names for all possible parents | |
231 | * @num_parents: number of possible parents | |
232 | * @flags: framework-level hints and quirks | |
233 | */ | |
234 | struct clk_init_data { | |
235 | const char *name; | |
236 | const struct clk_ops *ops; | |
2893c379 | 237 | const char * const *parent_names; |
0197b3ea SK |
238 | u8 num_parents; |
239 | unsigned long flags; | |
240 | }; | |
241 | ||
242 | /** | |
243 | * struct clk_hw - handle for traversing from a struct clk to its corresponding | |
244 | * hardware-specific structure. struct clk_hw should be declared within struct | |
245 | * clk_foo and then referenced by the struct clk instance that uses struct | |
246 | * clk_foo's clk_ops | |
247 | * | |
035a61c3 TV |
248 | * @core: pointer to the struct clk_core instance that points back to this |
249 | * struct clk_hw instance | |
250 | * | |
251 | * @clk: pointer to the per-user struct clk instance that can be used to call | |
252 | * into the clk API | |
0197b3ea SK |
253 | * |
254 | * @init: pointer to struct clk_init_data that contains the init data shared | |
255 | * with the common clock framework. | |
256 | */ | |
257 | struct clk_hw { | |
035a61c3 | 258 | struct clk_core *core; |
0197b3ea | 259 | struct clk *clk; |
dc4cd941 | 260 | const struct clk_init_data *init; |
0197b3ea SK |
261 | }; |
262 | ||
9d9f78ed MT |
263 | /* |
264 | * DOC: Basic clock implementations common to many platforms | |
265 | * | |
266 | * Each basic clock hardware type is comprised of a structure describing the | |
267 | * clock hardware, implementations of the relevant callbacks in struct clk_ops, | |
268 | * unique flags for that hardware type, a registration function and an | |
269 | * alternative macro for static initialization | |
270 | */ | |
271 | ||
272 | /** | |
273 | * struct clk_fixed_rate - fixed-rate clock | |
274 | * @hw: handle between common and hardware-specific interfaces | |
275 | * @fixed_rate: constant frequency of clock | |
276 | */ | |
277 | struct clk_fixed_rate { | |
278 | struct clk_hw hw; | |
279 | unsigned long fixed_rate; | |
0903ea60 | 280 | unsigned long fixed_accuracy; |
9d9f78ed MT |
281 | u8 flags; |
282 | }; | |
283 | ||
5fd9c05c GT |
284 | #define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw) |
285 | ||
bffad66e | 286 | extern const struct clk_ops clk_fixed_rate_ops; |
9d9f78ed MT |
287 | struct clk *clk_register_fixed_rate(struct device *dev, const char *name, |
288 | const char *parent_name, unsigned long flags, | |
289 | unsigned long fixed_rate); | |
26ef56be SB |
290 | struct clk_hw *clk_hw_register_fixed_rate(struct device *dev, const char *name, |
291 | const char *parent_name, unsigned long flags, | |
292 | unsigned long fixed_rate); | |
0903ea60 BB |
293 | struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev, |
294 | const char *name, const char *parent_name, unsigned long flags, | |
295 | unsigned long fixed_rate, unsigned long fixed_accuracy); | |
0b225e41 | 296 | void clk_unregister_fixed_rate(struct clk *clk); |
26ef56be SB |
297 | struct clk_hw *clk_hw_register_fixed_rate_with_accuracy(struct device *dev, |
298 | const char *name, const char *parent_name, unsigned long flags, | |
299 | unsigned long fixed_rate, unsigned long fixed_accuracy); | |
52445637 | 300 | void clk_hw_unregister_fixed_rate(struct clk_hw *hw); |
26ef56be | 301 | |
015ba402 GL |
302 | void of_fixed_clk_setup(struct device_node *np); |
303 | ||
9d9f78ed MT |
304 | /** |
305 | * struct clk_gate - gating clock | |
306 | * | |
307 | * @hw: handle between common and hardware-specific interfaces | |
308 | * @reg: register controlling gate | |
309 | * @bit_idx: single bit controlling gate | |
310 | * @flags: hardware-specific flags | |
311 | * @lock: register lock | |
312 | * | |
313 | * Clock which can gate its output. Implements .enable & .disable | |
314 | * | |
315 | * Flags: | |
1f73f31a | 316 | * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to |
725b418b GU |
317 | * enable the clock. Setting this flag does the opposite: setting the bit |
318 | * disable the clock and clearing it enables the clock | |
04577994 | 319 | * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit |
725b418b GU |
320 | * of this register, and mask of gate bits are in higher 16-bit of this |
321 | * register. While setting the gate bits, higher 16-bit should also be | |
322 | * updated to indicate changing gate bits. | |
9d9f78ed MT |
323 | */ |
324 | struct clk_gate { | |
325 | struct clk_hw hw; | |
326 | void __iomem *reg; | |
327 | u8 bit_idx; | |
328 | u8 flags; | |
329 | spinlock_t *lock; | |
9d9f78ed MT |
330 | }; |
331 | ||
5fd9c05c GT |
332 | #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw) |
333 | ||
9d9f78ed | 334 | #define CLK_GATE_SET_TO_DISABLE BIT(0) |
04577994 | 335 | #define CLK_GATE_HIWORD_MASK BIT(1) |
9d9f78ed | 336 | |
bffad66e | 337 | extern const struct clk_ops clk_gate_ops; |
9d9f78ed MT |
338 | struct clk *clk_register_gate(struct device *dev, const char *name, |
339 | const char *parent_name, unsigned long flags, | |
340 | void __iomem *reg, u8 bit_idx, | |
341 | u8 clk_gate_flags, spinlock_t *lock); | |
e270d8cb SB |
342 | struct clk_hw *clk_hw_register_gate(struct device *dev, const char *name, |
343 | const char *parent_name, unsigned long flags, | |
344 | void __iomem *reg, u8 bit_idx, | |
345 | u8 clk_gate_flags, spinlock_t *lock); | |
4e3c021f | 346 | void clk_unregister_gate(struct clk *clk); |
e270d8cb | 347 | void clk_hw_unregister_gate(struct clk_hw *hw); |
0a9c869d | 348 | int clk_gate_is_enabled(struct clk_hw *hw); |
9d9f78ed | 349 | |
357c3f0a RN |
350 | struct clk_div_table { |
351 | unsigned int val; | |
352 | unsigned int div; | |
353 | }; | |
354 | ||
9d9f78ed MT |
355 | /** |
356 | * struct clk_divider - adjustable divider clock | |
357 | * | |
358 | * @hw: handle between common and hardware-specific interfaces | |
359 | * @reg: register containing the divider | |
360 | * @shift: shift to the divider bit field | |
361 | * @width: width of the divider bit field | |
357c3f0a | 362 | * @table: array of value/divider pairs, last entry should have div = 0 |
9d9f78ed MT |
363 | * @lock: register lock |
364 | * | |
365 | * Clock with an adjustable divider affecting its output frequency. Implements | |
366 | * .recalc_rate, .set_rate and .round_rate | |
367 | * | |
368 | * Flags: | |
369 | * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the | |
725b418b GU |
370 | * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is |
371 | * the raw value read from the register, with the value of zero considered | |
056b2053 | 372 | * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set. |
9d9f78ed | 373 | * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from |
725b418b | 374 | * the hardware register |
056b2053 SB |
375 | * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have |
376 | * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor. | |
377 | * Some hardware implementations gracefully handle this case and allow a | |
378 | * zero divisor by not modifying their input clock | |
379 | * (divide by one / bypass). | |
d57dfe75 | 380 | * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit |
725b418b GU |
381 | * of this register, and mask of divider bits are in higher 16-bit of this |
382 | * register. While setting the divider bits, higher 16-bit should also be | |
383 | * updated to indicate changing divider bits. | |
774b5143 MC |
384 | * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded |
385 | * to the closest integer instead of the up one. | |
79c6ab50 HS |
386 | * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should |
387 | * not be changed by the clock framework. | |
afe76c8f JQ |
388 | * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED |
389 | * except when the value read from the register is zero, the divisor is | |
390 | * 2^width of the field. | |
9d9f78ed MT |
391 | */ |
392 | struct clk_divider { | |
393 | struct clk_hw hw; | |
394 | void __iomem *reg; | |
395 | u8 shift; | |
396 | u8 width; | |
397 | u8 flags; | |
357c3f0a | 398 | const struct clk_div_table *table; |
9d9f78ed | 399 | spinlock_t *lock; |
9d9f78ed MT |
400 | }; |
401 | ||
5fd9c05c GT |
402 | #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) |
403 | ||
9d9f78ed MT |
404 | #define CLK_DIVIDER_ONE_BASED BIT(0) |
405 | #define CLK_DIVIDER_POWER_OF_TWO BIT(1) | |
056b2053 | 406 | #define CLK_DIVIDER_ALLOW_ZERO BIT(2) |
d57dfe75 | 407 | #define CLK_DIVIDER_HIWORD_MASK BIT(3) |
774b5143 | 408 | #define CLK_DIVIDER_ROUND_CLOSEST BIT(4) |
79c6ab50 | 409 | #define CLK_DIVIDER_READ_ONLY BIT(5) |
afe76c8f | 410 | #define CLK_DIVIDER_MAX_AT_ZERO BIT(6) |
9d9f78ed | 411 | |
bffad66e | 412 | extern const struct clk_ops clk_divider_ops; |
50359819 | 413 | extern const struct clk_ops clk_divider_ro_ops; |
bca9690b SB |
414 | |
415 | unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate, | |
416 | unsigned int val, const struct clk_div_table *table, | |
12a26c29 | 417 | unsigned long flags, unsigned long width); |
22833a91 MR |
418 | long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, |
419 | unsigned long rate, unsigned long *prate, | |
420 | const struct clk_div_table *table, | |
421 | u8 width, unsigned long flags); | |
bca9690b SB |
422 | int divider_get_val(unsigned long rate, unsigned long parent_rate, |
423 | const struct clk_div_table *table, u8 width, | |
424 | unsigned long flags); | |
425 | ||
9d9f78ed MT |
426 | struct clk *clk_register_divider(struct device *dev, const char *name, |
427 | const char *parent_name, unsigned long flags, | |
428 | void __iomem *reg, u8 shift, u8 width, | |
429 | u8 clk_divider_flags, spinlock_t *lock); | |
eb7d264f SB |
430 | struct clk_hw *clk_hw_register_divider(struct device *dev, const char *name, |
431 | const char *parent_name, unsigned long flags, | |
432 | void __iomem *reg, u8 shift, u8 width, | |
433 | u8 clk_divider_flags, spinlock_t *lock); | |
357c3f0a RN |
434 | struct clk *clk_register_divider_table(struct device *dev, const char *name, |
435 | const char *parent_name, unsigned long flags, | |
436 | void __iomem *reg, u8 shift, u8 width, | |
437 | u8 clk_divider_flags, const struct clk_div_table *table, | |
438 | spinlock_t *lock); | |
eb7d264f SB |
439 | struct clk_hw *clk_hw_register_divider_table(struct device *dev, |
440 | const char *name, const char *parent_name, unsigned long flags, | |
441 | void __iomem *reg, u8 shift, u8 width, | |
442 | u8 clk_divider_flags, const struct clk_div_table *table, | |
443 | spinlock_t *lock); | |
4e3c021f | 444 | void clk_unregister_divider(struct clk *clk); |
eb7d264f | 445 | void clk_hw_unregister_divider(struct clk_hw *hw); |
9d9f78ed MT |
446 | |
447 | /** | |
448 | * struct clk_mux - multiplexer clock | |
449 | * | |
450 | * @hw: handle between common and hardware-specific interfaces | |
451 | * @reg: register controlling multiplexer | |
452 | * @shift: shift to multiplexer bit field | |
453 | * @width: width of mutliplexer bit field | |
3566d40c | 454 | * @flags: hardware-specific flags |
9d9f78ed MT |
455 | * @lock: register lock |
456 | * | |
457 | * Clock with multiple selectable parents. Implements .get_parent, .set_parent | |
458 | * and .recalc_rate | |
459 | * | |
460 | * Flags: | |
461 | * CLK_MUX_INDEX_ONE - register index starts at 1, not 0 | |
1f73f31a | 462 | * CLK_MUX_INDEX_BIT - register index is a single bit (power of two) |
ba492e90 | 463 | * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this |
725b418b GU |
464 | * register, and mask of mux bits are in higher 16-bit of this register. |
465 | * While setting the mux bits, higher 16-bit should also be updated to | |
466 | * indicate changing mux bits. | |
15a02c1f SB |
467 | * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired |
468 | * frequency. | |
9d9f78ed MT |
469 | */ |
470 | struct clk_mux { | |
471 | struct clk_hw hw; | |
472 | void __iomem *reg; | |
ce4f3313 PDS |
473 | u32 *table; |
474 | u32 mask; | |
9d9f78ed | 475 | u8 shift; |
9d9f78ed MT |
476 | u8 flags; |
477 | spinlock_t *lock; | |
478 | }; | |
479 | ||
5fd9c05c GT |
480 | #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw) |
481 | ||
9d9f78ed MT |
482 | #define CLK_MUX_INDEX_ONE BIT(0) |
483 | #define CLK_MUX_INDEX_BIT BIT(1) | |
ba492e90 | 484 | #define CLK_MUX_HIWORD_MASK BIT(2) |
15a02c1f SB |
485 | #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */ |
486 | #define CLK_MUX_ROUND_CLOSEST BIT(4) | |
9d9f78ed | 487 | |
bffad66e | 488 | extern const struct clk_ops clk_mux_ops; |
c57acd14 | 489 | extern const struct clk_ops clk_mux_ro_ops; |
ce4f3313 | 490 | |
9d9f78ed | 491 | struct clk *clk_register_mux(struct device *dev, const char *name, |
2893c379 SH |
492 | const char * const *parent_names, u8 num_parents, |
493 | unsigned long flags, | |
9d9f78ed MT |
494 | void __iomem *reg, u8 shift, u8 width, |
495 | u8 clk_mux_flags, spinlock_t *lock); | |
264b3171 SB |
496 | struct clk_hw *clk_hw_register_mux(struct device *dev, const char *name, |
497 | const char * const *parent_names, u8 num_parents, | |
498 | unsigned long flags, | |
499 | void __iomem *reg, u8 shift, u8 width, | |
500 | u8 clk_mux_flags, spinlock_t *lock); | |
b2476490 | 501 | |
ce4f3313 | 502 | struct clk *clk_register_mux_table(struct device *dev, const char *name, |
2893c379 SH |
503 | const char * const *parent_names, u8 num_parents, |
504 | unsigned long flags, | |
ce4f3313 PDS |
505 | void __iomem *reg, u8 shift, u32 mask, |
506 | u8 clk_mux_flags, u32 *table, spinlock_t *lock); | |
264b3171 SB |
507 | struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name, |
508 | const char * const *parent_names, u8 num_parents, | |
509 | unsigned long flags, | |
510 | void __iomem *reg, u8 shift, u32 mask, | |
511 | u8 clk_mux_flags, u32 *table, spinlock_t *lock); | |
ce4f3313 | 512 | |
4e3c021f | 513 | void clk_unregister_mux(struct clk *clk); |
264b3171 | 514 | void clk_hw_unregister_mux(struct clk_hw *hw); |
4e3c021f | 515 | |
79b16641 GC |
516 | void of_fixed_factor_clk_setup(struct device_node *node); |
517 | ||
f0948f59 SH |
518 | /** |
519 | * struct clk_fixed_factor - fixed multiplier and divider clock | |
520 | * | |
521 | * @hw: handle between common and hardware-specific interfaces | |
522 | * @mult: multiplier | |
523 | * @div: divider | |
524 | * | |
525 | * Clock with a fixed multiplier and divider. The output frequency is the | |
526 | * parent clock rate divided by div and multiplied by mult. | |
527 | * Implements .recalc_rate, .set_rate and .round_rate | |
528 | */ | |
529 | ||
530 | struct clk_fixed_factor { | |
531 | struct clk_hw hw; | |
532 | unsigned int mult; | |
533 | unsigned int div; | |
534 | }; | |
535 | ||
5fd9c05c GT |
536 | #define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw) |
537 | ||
3037e9ea | 538 | extern const struct clk_ops clk_fixed_factor_ops; |
f0948f59 SH |
539 | struct clk *clk_register_fixed_factor(struct device *dev, const char *name, |
540 | const char *parent_name, unsigned long flags, | |
541 | unsigned int mult, unsigned int div); | |
cbf9591f | 542 | void clk_unregister_fixed_factor(struct clk *clk); |
0759ac8a SB |
543 | struct clk_hw *clk_hw_register_fixed_factor(struct device *dev, |
544 | const char *name, const char *parent_name, unsigned long flags, | |
545 | unsigned int mult, unsigned int div); | |
546 | void clk_hw_unregister_fixed_factor(struct clk_hw *hw); | |
f0948f59 | 547 | |
e2d0e90f HK |
548 | /** |
549 | * struct clk_fractional_divider - adjustable fractional divider clock | |
550 | * | |
551 | * @hw: handle between common and hardware-specific interfaces | |
552 | * @reg: register containing the divider | |
553 | * @mshift: shift to the numerator bit field | |
554 | * @mwidth: width of the numerator bit field | |
555 | * @nshift: shift to the denominator bit field | |
556 | * @nwidth: width of the denominator bit field | |
557 | * @lock: register lock | |
558 | * | |
559 | * Clock with adjustable fractional divider affecting its output frequency. | |
560 | */ | |
e2d0e90f HK |
561 | struct clk_fractional_divider { |
562 | struct clk_hw hw; | |
563 | void __iomem *reg; | |
564 | u8 mshift; | |
934e2536 | 565 | u8 mwidth; |
e2d0e90f HK |
566 | u32 mmask; |
567 | u8 nshift; | |
934e2536 | 568 | u8 nwidth; |
e2d0e90f HK |
569 | u32 nmask; |
570 | u8 flags; | |
ec52e462 EZ |
571 | void (*approximation)(struct clk_hw *hw, |
572 | unsigned long rate, unsigned long *parent_rate, | |
573 | unsigned long *m, unsigned long *n); | |
e2d0e90f HK |
574 | spinlock_t *lock; |
575 | }; | |
576 | ||
5fd9c05c GT |
577 | #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw) |
578 | ||
e2d0e90f HK |
579 | extern const struct clk_ops clk_fractional_divider_ops; |
580 | struct clk *clk_register_fractional_divider(struct device *dev, | |
581 | const char *name, const char *parent_name, unsigned long flags, | |
582 | void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, | |
583 | u8 clk_divider_flags, spinlock_t *lock); | |
39b44cff SB |
584 | struct clk_hw *clk_hw_register_fractional_divider(struct device *dev, |
585 | const char *name, const char *parent_name, unsigned long flags, | |
586 | void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, | |
587 | u8 clk_divider_flags, spinlock_t *lock); | |
588 | void clk_hw_unregister_fractional_divider(struct clk_hw *hw); | |
e2d0e90f | 589 | |
f2e0a532 MR |
590 | /** |
591 | * struct clk_multiplier - adjustable multiplier clock | |
592 | * | |
593 | * @hw: handle between common and hardware-specific interfaces | |
594 | * @reg: register containing the multiplier | |
595 | * @shift: shift to the multiplier bit field | |
596 | * @width: width of the multiplier bit field | |
597 | * @lock: register lock | |
598 | * | |
599 | * Clock with an adjustable multiplier affecting its output frequency. | |
600 | * Implements .recalc_rate, .set_rate and .round_rate | |
601 | * | |
602 | * Flags: | |
603 | * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read | |
604 | * from the register, with 0 being a valid value effectively | |
605 | * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is | |
606 | * set, then a null multiplier will be considered as a bypass, | |
607 | * leaving the parent rate unmodified. | |
608 | * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be | |
609 | * rounded to the closest integer instead of the down one. | |
610 | */ | |
611 | struct clk_multiplier { | |
612 | struct clk_hw hw; | |
613 | void __iomem *reg; | |
614 | u8 shift; | |
615 | u8 width; | |
616 | u8 flags; | |
617 | spinlock_t *lock; | |
618 | }; | |
619 | ||
5fd9c05c GT |
620 | #define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw) |
621 | ||
f2e0a532 MR |
622 | #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0) |
623 | #define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1) | |
624 | ||
625 | extern const struct clk_ops clk_multiplier_ops; | |
626 | ||
ece70094 PG |
627 | /*** |
628 | * struct clk_composite - aggregate clock of mux, divider and gate clocks | |
629 | * | |
630 | * @hw: handle between common and hardware-specific interfaces | |
d3a1c7be MT |
631 | * @mux_hw: handle between composite and hardware-specific mux clock |
632 | * @rate_hw: handle between composite and hardware-specific rate clock | |
633 | * @gate_hw: handle between composite and hardware-specific gate clock | |
ece70094 | 634 | * @mux_ops: clock ops for mux |
d3a1c7be | 635 | * @rate_ops: clock ops for rate |
ece70094 PG |
636 | * @gate_ops: clock ops for gate |
637 | */ | |
638 | struct clk_composite { | |
639 | struct clk_hw hw; | |
640 | struct clk_ops ops; | |
641 | ||
642 | struct clk_hw *mux_hw; | |
d3a1c7be | 643 | struct clk_hw *rate_hw; |
ece70094 PG |
644 | struct clk_hw *gate_hw; |
645 | ||
646 | const struct clk_ops *mux_ops; | |
d3a1c7be | 647 | const struct clk_ops *rate_ops; |
ece70094 PG |
648 | const struct clk_ops *gate_ops; |
649 | }; | |
650 | ||
5fd9c05c GT |
651 | #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw) |
652 | ||
ece70094 | 653 | struct clk *clk_register_composite(struct device *dev, const char *name, |
2893c379 | 654 | const char * const *parent_names, int num_parents, |
ece70094 | 655 | struct clk_hw *mux_hw, const struct clk_ops *mux_ops, |
d3a1c7be | 656 | struct clk_hw *rate_hw, const struct clk_ops *rate_ops, |
ece70094 PG |
657 | struct clk_hw *gate_hw, const struct clk_ops *gate_ops, |
658 | unsigned long flags); | |
92a39d90 | 659 | void clk_unregister_composite(struct clk *clk); |
49cb392d SB |
660 | struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name, |
661 | const char * const *parent_names, int num_parents, | |
662 | struct clk_hw *mux_hw, const struct clk_ops *mux_ops, | |
663 | struct clk_hw *rate_hw, const struct clk_ops *rate_ops, | |
664 | struct clk_hw *gate_hw, const struct clk_ops *gate_ops, | |
665 | unsigned long flags); | |
666 | void clk_hw_unregister_composite(struct clk_hw *hw); | |
ece70094 | 667 | |
c873d14d JS |
668 | /*** |
669 | * struct clk_gpio_gate - gpio gated clock | |
670 | * | |
671 | * @hw: handle between common and hardware-specific interfaces | |
672 | * @gpiod: gpio descriptor | |
673 | * | |
674 | * Clock with a gpio control for enabling and disabling the parent clock. | |
675 | * Implements .enable, .disable and .is_enabled | |
676 | */ | |
677 | ||
678 | struct clk_gpio { | |
679 | struct clk_hw hw; | |
680 | struct gpio_desc *gpiod; | |
681 | }; | |
682 | ||
5fd9c05c GT |
683 | #define to_clk_gpio(_hw) container_of(_hw, struct clk_gpio, hw) |
684 | ||
c873d14d JS |
685 | extern const struct clk_ops clk_gpio_gate_ops; |
686 | struct clk *clk_register_gpio_gate(struct device *dev, const char *name, | |
908a543a | 687 | const char *parent_name, struct gpio_desc *gpiod, |
c873d14d | 688 | unsigned long flags); |
b120743a | 689 | struct clk_hw *clk_hw_register_gpio_gate(struct device *dev, const char *name, |
908a543a | 690 | const char *parent_name, struct gpio_desc *gpiod, |
b120743a SB |
691 | unsigned long flags); |
692 | void clk_hw_unregister_gpio_gate(struct clk_hw *hw); | |
c873d14d | 693 | |
80eeb1f0 SS |
694 | /** |
695 | * struct clk_gpio_mux - gpio controlled clock multiplexer | |
696 | * | |
697 | * @hw: see struct clk_gpio | |
698 | * @gpiod: gpio descriptor to select the parent of this clock multiplexer | |
699 | * | |
700 | * Clock with a gpio control for selecting the parent clock. | |
701 | * Implements .get_parent, .set_parent and .determine_rate | |
702 | */ | |
703 | ||
704 | extern const struct clk_ops clk_gpio_mux_ops; | |
705 | struct clk *clk_register_gpio_mux(struct device *dev, const char *name, | |
908a543a LW |
706 | const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod, |
707 | unsigned long flags); | |
b120743a | 708 | struct clk_hw *clk_hw_register_gpio_mux(struct device *dev, const char *name, |
908a543a LW |
709 | const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod, |
710 | unsigned long flags); | |
b120743a | 711 | void clk_hw_unregister_gpio_mux(struct clk_hw *hw); |
80eeb1f0 | 712 | |
b2476490 MT |
713 | /** |
714 | * clk_register - allocate a new clock, register it and return an opaque cookie | |
715 | * @dev: device that is registering this clock | |
b2476490 | 716 | * @hw: link to hardware-specific clock data |
b2476490 MT |
717 | * |
718 | * clk_register is the primary interface for populating the clock tree with new | |
719 | * clock nodes. It returns a pointer to the newly allocated struct clk which | |
720 | * cannot be dereferenced by driver code but may be used in conjuction with the | |
d1302a36 MT |
721 | * rest of the clock API. In the event of an error clk_register will return an |
722 | * error code; drivers must test for an error code after calling clk_register. | |
b2476490 | 723 | */ |
0197b3ea | 724 | struct clk *clk_register(struct device *dev, struct clk_hw *hw); |
46c8773a | 725 | struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw); |
b2476490 | 726 | |
4143804c SB |
727 | int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw); |
728 | int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw); | |
729 | ||
1df5c939 | 730 | void clk_unregister(struct clk *clk); |
46c8773a | 731 | void devm_clk_unregister(struct device *dev, struct clk *clk); |
1df5c939 | 732 | |
4143804c SB |
733 | void clk_hw_unregister(struct clk_hw *hw); |
734 | void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw); | |
735 | ||
b2476490 | 736 | /* helper functions */ |
b76281cb | 737 | const char *__clk_get_name(const struct clk *clk); |
e7df6f6e | 738 | const char *clk_hw_get_name(const struct clk_hw *hw); |
b2476490 | 739 | struct clk_hw *__clk_get_hw(struct clk *clk); |
e7df6f6e SB |
740 | unsigned int clk_hw_get_num_parents(const struct clk_hw *hw); |
741 | struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw); | |
742 | struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw, | |
1a9c069c | 743 | unsigned int index); |
93874681 | 744 | unsigned int __clk_get_enable_count(struct clk *clk); |
e7df6f6e | 745 | unsigned long clk_hw_get_rate(const struct clk_hw *hw); |
b2476490 | 746 | unsigned long __clk_get_flags(struct clk *clk); |
e7df6f6e SB |
747 | unsigned long clk_hw_get_flags(const struct clk_hw *hw); |
748 | bool clk_hw_is_prepared(const struct clk_hw *hw); | |
e55a839a | 749 | bool clk_hw_rate_is_protected(const struct clk_hw *hw); |
be68bf88 | 750 | bool clk_hw_is_enabled(const struct clk_hw *hw); |
2ac6b1f5 | 751 | bool __clk_is_enabled(struct clk *clk); |
b2476490 | 752 | struct clk *__clk_lookup(const char *name); |
0817b62c BB |
753 | int __clk_mux_determine_rate(struct clk_hw *hw, |
754 | struct clk_rate_request *req); | |
755 | int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req); | |
756 | int __clk_mux_determine_rate_closest(struct clk_hw *hw, | |
757 | struct clk_rate_request *req); | |
42c86547 | 758 | void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent); |
9783c0d9 SB |
759 | void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate, |
760 | unsigned long max_rate); | |
b2476490 | 761 | |
2e65d8bf JMC |
762 | static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src) |
763 | { | |
764 | dst->clk = src->clk; | |
765 | dst->core = src->core; | |
766 | } | |
767 | ||
22833a91 MR |
768 | static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate, |
769 | unsigned long *prate, | |
770 | const struct clk_div_table *table, | |
771 | u8 width, unsigned long flags) | |
772 | { | |
773 | return divider_round_rate_parent(hw, clk_hw_get_parent(hw), | |
774 | rate, prate, table, width, flags); | |
775 | } | |
776 | ||
b2476490 MT |
777 | /* |
778 | * FIXME clock api without lock protection | |
779 | */ | |
1a9c069c | 780 | unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate); |
b2476490 | 781 | |
766e6a4e GL |
782 | struct of_device_id; |
783 | ||
784 | typedef void (*of_clk_init_cb_t)(struct device_node *); | |
785 | ||
0b151deb SH |
786 | struct clk_onecell_data { |
787 | struct clk **clks; | |
788 | unsigned int clk_num; | |
789 | }; | |
790 | ||
0861e5b8 | 791 | struct clk_hw_onecell_data { |
5963f19c | 792 | unsigned int num; |
0861e5b8 SB |
793 | struct clk_hw *hws[]; |
794 | }; | |
795 | ||
819b4861 TK |
796 | extern struct of_device_id __clk_of_table; |
797 | ||
54196ccb | 798 | #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn) |
0b151deb | 799 | |
c7296c51 RRD |
800 | /* |
801 | * Use this macro when you have a driver that requires two initialization | |
802 | * routines, one at of_clk_init(), and one at platform device probe | |
803 | */ | |
804 | #define CLK_OF_DECLARE_DRIVER(name, compat, fn) \ | |
339e1e54 | 805 | static void __init name##_of_clk_init_driver(struct device_node *np) \ |
c7296c51 RRD |
806 | { \ |
807 | of_node_clear_flag(np, OF_POPULATED); \ | |
808 | fn(np); \ | |
809 | } \ | |
810 | OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver) | |
811 | ||
1ded879e CZ |
812 | #define CLK_HW_INIT(_name, _parent, _ops, _flags) \ |
813 | (&(struct clk_init_data) { \ | |
814 | .flags = _flags, \ | |
815 | .name = _name, \ | |
816 | .parent_names = (const char *[]) { _parent }, \ | |
817 | .num_parents = 1, \ | |
818 | .ops = _ops, \ | |
819 | }) | |
820 | ||
821 | #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \ | |
822 | (&(struct clk_init_data) { \ | |
823 | .flags = _flags, \ | |
824 | .name = _name, \ | |
825 | .parent_names = _parents, \ | |
826 | .num_parents = ARRAY_SIZE(_parents), \ | |
827 | .ops = _ops, \ | |
828 | }) | |
829 | ||
830 | #define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \ | |
831 | (&(struct clk_init_data) { \ | |
832 | .flags = _flags, \ | |
833 | .name = _name, \ | |
834 | .parent_names = NULL, \ | |
835 | .num_parents = 0, \ | |
836 | .ops = _ops, \ | |
837 | }) | |
838 | ||
839 | #define CLK_FIXED_FACTOR(_struct, _name, _parent, \ | |
840 | _div, _mult, _flags) \ | |
841 | struct clk_fixed_factor _struct = { \ | |
842 | .div = _div, \ | |
843 | .mult = _mult, \ | |
844 | .hw.init = CLK_HW_INIT(_name, \ | |
845 | _parent, \ | |
846 | &clk_fixed_factor_ops, \ | |
847 | _flags), \ | |
848 | } | |
849 | ||
0b151deb | 850 | #ifdef CONFIG_OF |
766e6a4e GL |
851 | int of_clk_add_provider(struct device_node *np, |
852 | struct clk *(*clk_src_get)(struct of_phandle_args *args, | |
853 | void *data), | |
854 | void *data); | |
0861e5b8 SB |
855 | int of_clk_add_hw_provider(struct device_node *np, |
856 | struct clk_hw *(*get)(struct of_phandle_args *clkspec, | |
857 | void *data), | |
858 | void *data); | |
aa795c41 SB |
859 | int devm_of_clk_add_hw_provider(struct device *dev, |
860 | struct clk_hw *(*get)(struct of_phandle_args *clkspec, | |
861 | void *data), | |
862 | void *data); | |
766e6a4e | 863 | void of_clk_del_provider(struct device_node *np); |
aa795c41 | 864 | void devm_of_clk_del_provider(struct device *dev); |
766e6a4e GL |
865 | struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, |
866 | void *data); | |
0861e5b8 SB |
867 | struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec, |
868 | void *data); | |
494bfec9 | 869 | struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data); |
0861e5b8 SB |
870 | struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec, |
871 | void *data); | |
929e7f3b | 872 | unsigned int of_clk_get_parent_count(struct device_node *np); |
2e61dfb3 DN |
873 | int of_clk_parent_fill(struct device_node *np, const char **parents, |
874 | unsigned int size); | |
766e6a4e | 875 | const char *of_clk_get_parent_name(struct device_node *np, int index); |
d56f8994 LJ |
876 | int of_clk_detect_critical(struct device_node *np, int index, |
877 | unsigned long *flags); | |
766e6a4e GL |
878 | void of_clk_init(const struct of_device_id *matches); |
879 | ||
0b151deb | 880 | #else /* !CONFIG_OF */ |
f2f6c255 | 881 | |
0b151deb SH |
882 | static inline int of_clk_add_provider(struct device_node *np, |
883 | struct clk *(*clk_src_get)(struct of_phandle_args *args, | |
884 | void *data), | |
885 | void *data) | |
886 | { | |
887 | return 0; | |
888 | } | |
0861e5b8 SB |
889 | static inline int of_clk_add_hw_provider(struct device_node *np, |
890 | struct clk_hw *(*get)(struct of_phandle_args *clkspec, | |
891 | void *data), | |
892 | void *data) | |
893 | { | |
894 | return 0; | |
895 | } | |
aa795c41 SB |
896 | static inline int devm_of_clk_add_hw_provider(struct device *dev, |
897 | struct clk_hw *(*get)(struct of_phandle_args *clkspec, | |
898 | void *data), | |
899 | void *data) | |
900 | { | |
901 | return 0; | |
902 | } | |
20dd882a | 903 | static inline void of_clk_del_provider(struct device_node *np) {} |
aa795c41 | 904 | static inline void devm_of_clk_del_provider(struct device *dev) {} |
0b151deb SH |
905 | static inline struct clk *of_clk_src_simple_get( |
906 | struct of_phandle_args *clkspec, void *data) | |
907 | { | |
908 | return ERR_PTR(-ENOENT); | |
909 | } | |
0861e5b8 SB |
910 | static inline struct clk_hw * |
911 | of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data) | |
912 | { | |
913 | return ERR_PTR(-ENOENT); | |
914 | } | |
0b151deb SH |
915 | static inline struct clk *of_clk_src_onecell_get( |
916 | struct of_phandle_args *clkspec, void *data) | |
917 | { | |
918 | return ERR_PTR(-ENOENT); | |
919 | } | |
0861e5b8 SB |
920 | static inline struct clk_hw * |
921 | of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data) | |
922 | { | |
923 | return ERR_PTR(-ENOENT); | |
924 | } | |
d42c0472 | 925 | static inline unsigned int of_clk_get_parent_count(struct device_node *np) |
679c51cf SB |
926 | { |
927 | return 0; | |
928 | } | |
929 | static inline int of_clk_parent_fill(struct device_node *np, | |
930 | const char **parents, unsigned int size) | |
931 | { | |
932 | return 0; | |
933 | } | |
0b151deb SH |
934 | static inline const char *of_clk_get_parent_name(struct device_node *np, |
935 | int index) | |
936 | { | |
937 | return NULL; | |
938 | } | |
d56f8994 LJ |
939 | static inline int of_clk_detect_critical(struct device_node *np, int index, |
940 | unsigned long *flags) | |
941 | { | |
942 | return 0; | |
943 | } | |
20dd882a | 944 | static inline void of_clk_init(const struct of_device_id *matches) {} |
0b151deb | 945 | #endif /* CONFIG_OF */ |
aa514ce3 GS |
946 | |
947 | /* | |
948 | * wrap access to peripherals in accessor routines | |
949 | * for improved portability across platforms | |
950 | */ | |
951 | ||
6d8cdb68 GS |
952 | #if IS_ENABLED(CONFIG_PPC) |
953 | ||
954 | static inline u32 clk_readl(u32 __iomem *reg) | |
955 | { | |
956 | return ioread32be(reg); | |
957 | } | |
958 | ||
959 | static inline void clk_writel(u32 val, u32 __iomem *reg) | |
960 | { | |
961 | iowrite32be(val, reg); | |
962 | } | |
963 | ||
964 | #else /* platform dependent I/O accessors */ | |
965 | ||
aa514ce3 GS |
966 | static inline u32 clk_readl(u32 __iomem *reg) |
967 | { | |
968 | return readl(reg); | |
969 | } | |
970 | ||
971 | static inline void clk_writel(u32 val, u32 __iomem *reg) | |
972 | { | |
973 | writel(val, reg); | |
974 | } | |
975 | ||
6d8cdb68 GS |
976 | #endif /* platform dependent I/O accessors */ |
977 | ||
fb2b3c9f | 978 | #ifdef CONFIG_DEBUG_FS |
61c7cddf | 979 | struct dentry *clk_debugfs_add_file(struct clk_hw *hw, char *name, umode_t mode, |
fb2b3c9f PDS |
980 | void *data, const struct file_operations *fops); |
981 | #endif | |
982 | ||
b2476490 MT |
983 | #endif /* CONFIG_COMMON_CLK */ |
984 | #endif /* CLK_PROVIDER_H */ |