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b2476490 MT |
1 | /* |
2 | * linux/include/linux/clk-provider.h | |
3 | * | |
4 | * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com> | |
5 | * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | #ifndef __LINUX_CLK_PROVIDER_H | |
12 | #define __LINUX_CLK_PROVIDER_H | |
13 | ||
aa514ce3 | 14 | #include <linux/io.h> |
355bb165 | 15 | #include <linux/of.h> |
eb06d6bb | 16 | #include <linux/of_clk.h> |
b2476490 MT |
17 | |
18 | #ifdef CONFIG_COMMON_CLK | |
19 | ||
b2476490 MT |
20 | /* |
21 | * flags used across common struct clk. these flags should only affect the | |
22 | * top-level framework. custom flags for dealing with hardware specifics | |
23 | * belong in struct clk_foo | |
a6059ab9 GU |
24 | * |
25 | * Please update clk_flags[] in drivers/clk/clk.c when making changes here! | |
b2476490 MT |
26 | */ |
27 | #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ | |
28 | #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ | |
29 | #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ | |
30 | #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ | |
b9610e74 | 31 | /* unused */ |
f7d8caad | 32 | #define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */ |
a093bde2 | 33 | #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ |
819c1de3 | 34 | #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ |
5279fc40 | 35 | #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */ |
d8d91987 | 36 | #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */ |
2eb8c710 | 37 | #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */ |
32b9b109 | 38 | #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */ |
a4b3518d DA |
39 | /* parents need enable during gate/ungate, set rate and re-parent */ |
40 | #define CLK_OPS_PARENT_ENABLE BIT(12) | |
9fba738a JB |
41 | /* duty cycle call may be forwarded to the parent clock */ |
42 | #define CLK_DUTY_CYCLE_PARENT BIT(13) | |
b2476490 | 43 | |
61ae7656 | 44 | struct clk; |
0197b3ea | 45 | struct clk_hw; |
035a61c3 | 46 | struct clk_core; |
c646cbf1 | 47 | struct dentry; |
0197b3ea | 48 | |
0817b62c BB |
49 | /** |
50 | * struct clk_rate_request - Structure encoding the clk constraints that | |
51 | * a clock user might require. | |
52 | * | |
53 | * @rate: Requested clock rate. This field will be adjusted by | |
54 | * clock drivers according to hardware capabilities. | |
55 | * @min_rate: Minimum rate imposed by clk users. | |
1971dfb7 | 56 | * @max_rate: Maximum rate imposed by clk users. |
0817b62c BB |
57 | * @best_parent_rate: The best parent rate a parent can provide to fulfill the |
58 | * requested constraints. | |
59 | * @best_parent_hw: The most appropriate parent clock that fulfills the | |
60 | * requested constraints. | |
61 | * | |
62 | */ | |
63 | struct clk_rate_request { | |
64 | unsigned long rate; | |
65 | unsigned long min_rate; | |
66 | unsigned long max_rate; | |
67 | unsigned long best_parent_rate; | |
68 | struct clk_hw *best_parent_hw; | |
69 | }; | |
70 | ||
9fba738a JB |
71 | /** |
72 | * struct clk_duty - Struture encoding the duty cycle ratio of a clock | |
73 | * | |
74 | * @num: Numerator of the duty cycle ratio | |
75 | * @den: Denominator of the duty cycle ratio | |
76 | */ | |
77 | struct clk_duty { | |
78 | unsigned int num; | |
79 | unsigned int den; | |
80 | }; | |
81 | ||
b2476490 MT |
82 | /** |
83 | * struct clk_ops - Callback operations for hardware clocks; these are to | |
84 | * be provided by the clock implementation, and will be called by drivers | |
85 | * through the clk_* api. | |
86 | * | |
87 | * @prepare: Prepare the clock for enabling. This must not return until | |
725b418b GU |
88 | * the clock is fully prepared, and it's safe to call clk_enable. |
89 | * This callback is intended to allow clock implementations to | |
90 | * do any initialisation that may sleep. Called with | |
91 | * prepare_lock held. | |
b2476490 MT |
92 | * |
93 | * @unprepare: Release the clock from its prepared state. This will typically | |
725b418b GU |
94 | * undo any work done in the @prepare callback. Called with |
95 | * prepare_lock held. | |
b2476490 | 96 | * |
3d6ee287 UH |
97 | * @is_prepared: Queries the hardware to determine if the clock is prepared. |
98 | * This function is allowed to sleep. Optional, if this op is not | |
99 | * set then the prepare count will be used. | |
100 | * | |
3cc8247f UH |
101 | * @unprepare_unused: Unprepare the clock atomically. Only called from |
102 | * clk_disable_unused for prepare clocks with special needs. | |
103 | * Called with prepare mutex held. This function may sleep. | |
104 | * | |
b2476490 | 105 | * @enable: Enable the clock atomically. This must not return until the |
725b418b GU |
106 | * clock is generating a valid clock signal, usable by consumer |
107 | * devices. Called with enable_lock held. This function must not | |
108 | * sleep. | |
b2476490 MT |
109 | * |
110 | * @disable: Disable the clock atomically. Called with enable_lock held. | |
725b418b | 111 | * This function must not sleep. |
b2476490 | 112 | * |
119c7127 | 113 | * @is_enabled: Queries the hardware to determine if the clock is enabled. |
725b418b GU |
114 | * This function must not sleep. Optional, if this op is not |
115 | * set then the enable count will be used. | |
119c7127 | 116 | * |
7c045a55 MT |
117 | * @disable_unused: Disable the clock atomically. Only called from |
118 | * clk_disable_unused for gate clocks with special needs. | |
119 | * Called with enable_lock held. This function must not | |
120 | * sleep. | |
121 | * | |
8b95d1ce RD |
122 | * @save_context: Save the context of the clock in prepration for poweroff. |
123 | * | |
124 | * @restore_context: Restore the context of the clock after a restoration | |
125 | * of power. | |
126 | * | |
7ce3e8cc | 127 | * @recalc_rate Recalculate the rate of this clock, by querying hardware. The |
725b418b GU |
128 | * parent rate is an input parameter. It is up to the caller to |
129 | * ensure that the prepare_mutex is held across this call. | |
130 | * Returns the calculated rate. Optional, but recommended - if | |
131 | * this op is not set then clock rate will be initialized to 0. | |
b2476490 MT |
132 | * |
133 | * @round_rate: Given a target rate as input, returns the closest rate actually | |
54e73016 GU |
134 | * supported by the clock. The parent rate is an input/output |
135 | * parameter. | |
b2476490 | 136 | * |
71472c0c JH |
137 | * @determine_rate: Given a target rate as input, returns the closest rate |
138 | * actually supported by the clock, and optionally the parent clock | |
139 | * that should be used to provide the clock rate. | |
140 | * | |
b2476490 | 141 | * @set_parent: Change the input source of this clock; for clocks with multiple |
54e73016 GU |
142 | * possible parents specify a new parent by passing in the index |
143 | * as a u8 corresponding to the parent in either the .parent_names | |
144 | * or .parents arrays. This function in affect translates an | |
145 | * array index into the value programmed into the hardware. | |
146 | * Returns 0 on success, -EERROR otherwise. | |
147 | * | |
b2476490 | 148 | * @get_parent: Queries the hardware to determine the parent of a clock. The |
725b418b GU |
149 | * return value is a u8 which specifies the index corresponding to |
150 | * the parent clock. This index can be applied to either the | |
151 | * .parent_names or .parents arrays. In short, this function | |
152 | * translates the parent value read from hardware into an array | |
153 | * index. Currently only called when the clock is initialized by | |
154 | * __clk_init. This callback is mandatory for clocks with | |
155 | * multiple parents. It is optional (and unnecessary) for clocks | |
156 | * with 0 or 1 parents. | |
b2476490 | 157 | * |
1c0035d7 SG |
158 | * @set_rate: Change the rate of this clock. The requested rate is specified |
159 | * by the second argument, which should typically be the return | |
160 | * of .round_rate call. The third argument gives the parent rate | |
161 | * which is likely helpful for most .set_rate implementation. | |
162 | * Returns 0 on success, -EERROR otherwise. | |
b2476490 | 163 | * |
3fa2252b SB |
164 | * @set_rate_and_parent: Change the rate and the parent of this clock. The |
165 | * requested rate is specified by the second argument, which | |
166 | * should typically be the return of .round_rate call. The | |
167 | * third argument gives the parent rate which is likely helpful | |
168 | * for most .set_rate_and_parent implementation. The fourth | |
169 | * argument gives the parent index. This callback is optional (and | |
170 | * unnecessary) for clocks with 0 or 1 parents as well as | |
171 | * for clocks that can tolerate switching the rate and the parent | |
172 | * separately via calls to .set_parent and .set_rate. | |
173 | * Returns 0 on success, -EERROR otherwise. | |
174 | * | |
54e73016 GU |
175 | * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy |
176 | * is expressed in ppb (parts per billion). The parent accuracy is | |
177 | * an input parameter. | |
178 | * Returns the calculated accuracy. Optional - if this op is not | |
179 | * set then clock accuracy will be initialized to parent accuracy | |
180 | * or 0 (perfect clock) if clock has no parent. | |
181 | * | |
9824cf73 MR |
182 | * @get_phase: Queries the hardware to get the current phase of a clock. |
183 | * Returned values are 0-359 degrees on success, negative | |
184 | * error codes on failure. | |
185 | * | |
e59c5371 MT |
186 | * @set_phase: Shift the phase this clock signal in degrees specified |
187 | * by the second argument. Valid values for degrees are | |
188 | * 0-359. Return 0 on success, otherwise -EERROR. | |
189 | * | |
9fba738a JB |
190 | * @get_duty_cycle: Queries the hardware to get the current duty cycle ratio |
191 | * of a clock. Returned values denominator cannot be 0 and must be | |
192 | * superior or equal to the numerator. | |
193 | * | |
194 | * @set_duty_cycle: Apply the duty cycle ratio to this clock signal specified by | |
195 | * the numerator (2nd argurment) and denominator (3rd argument). | |
196 | * Argument must be a valid ratio (denominator > 0 | |
197 | * and >= numerator) Return 0 on success, otherwise -EERROR. | |
198 | * | |
54e73016 GU |
199 | * @init: Perform platform-specific initialization magic. |
200 | * This is not not used by any of the basic clock types. | |
201 | * Please consider other ways of solving initialization problems | |
202 | * before using this callback, as its use is discouraged. | |
203 | * | |
c646cbf1 AE |
204 | * @debug_init: Set up type-specific debugfs entries for this clock. This |
205 | * is called once, after the debugfs directory entry for this | |
206 | * clock has been created. The dentry pointer representing that | |
207 | * directory is provided as an argument. Called with | |
208 | * prepare_lock held. Returns 0 on success, -EERROR otherwise. | |
209 | * | |
3fa2252b | 210 | * |
b2476490 MT |
211 | * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow |
212 | * implementations to split any work between atomic (enable) and sleepable | |
213 | * (prepare) contexts. If enabling a clock requires code that might sleep, | |
214 | * this must be done in clk_prepare. Clock enable code that will never be | |
7ce3e8cc | 215 | * called in a sleepable context may be implemented in clk_enable. |
b2476490 MT |
216 | * |
217 | * Typically, drivers will call clk_prepare when a clock may be needed later | |
218 | * (eg. when a device is opened), and clk_enable when the clock is actually | |
219 | * required (eg. from an interrupt). Note that clk_prepare MUST have been | |
220 | * called before clk_enable. | |
221 | */ | |
222 | struct clk_ops { | |
223 | int (*prepare)(struct clk_hw *hw); | |
224 | void (*unprepare)(struct clk_hw *hw); | |
3d6ee287 | 225 | int (*is_prepared)(struct clk_hw *hw); |
3cc8247f | 226 | void (*unprepare_unused)(struct clk_hw *hw); |
b2476490 MT |
227 | int (*enable)(struct clk_hw *hw); |
228 | void (*disable)(struct clk_hw *hw); | |
229 | int (*is_enabled)(struct clk_hw *hw); | |
7c045a55 | 230 | void (*disable_unused)(struct clk_hw *hw); |
8b95d1ce RD |
231 | int (*save_context)(struct clk_hw *hw); |
232 | void (*restore_context)(struct clk_hw *hw); | |
b2476490 MT |
233 | unsigned long (*recalc_rate)(struct clk_hw *hw, |
234 | unsigned long parent_rate); | |
54e73016 GU |
235 | long (*round_rate)(struct clk_hw *hw, unsigned long rate, |
236 | unsigned long *parent_rate); | |
0817b62c BB |
237 | int (*determine_rate)(struct clk_hw *hw, |
238 | struct clk_rate_request *req); | |
b2476490 MT |
239 | int (*set_parent)(struct clk_hw *hw, u8 index); |
240 | u8 (*get_parent)(struct clk_hw *hw); | |
54e73016 GU |
241 | int (*set_rate)(struct clk_hw *hw, unsigned long rate, |
242 | unsigned long parent_rate); | |
3fa2252b SB |
243 | int (*set_rate_and_parent)(struct clk_hw *hw, |
244 | unsigned long rate, | |
245 | unsigned long parent_rate, u8 index); | |
5279fc40 BB |
246 | unsigned long (*recalc_accuracy)(struct clk_hw *hw, |
247 | unsigned long parent_accuracy); | |
9824cf73 | 248 | int (*get_phase)(struct clk_hw *hw); |
e59c5371 | 249 | int (*set_phase)(struct clk_hw *hw, int degrees); |
9fba738a JB |
250 | int (*get_duty_cycle)(struct clk_hw *hw, |
251 | struct clk_duty *duty); | |
252 | int (*set_duty_cycle)(struct clk_hw *hw, | |
253 | struct clk_duty *duty); | |
b2476490 | 254 | void (*init)(struct clk_hw *hw); |
d75d50c0 | 255 | void (*debug_init)(struct clk_hw *hw, struct dentry *dentry); |
b2476490 MT |
256 | }; |
257 | ||
0197b3ea SK |
258 | /** |
259 | * struct clk_init_data - holds init data that's common to all clocks and is | |
260 | * shared between the clock provider and the common clock framework. | |
261 | * | |
262 | * @name: clock name | |
263 | * @ops: operations this clock supports | |
264 | * @parent_names: array of string names for all possible parents | |
265 | * @num_parents: number of possible parents | |
266 | * @flags: framework-level hints and quirks | |
267 | */ | |
268 | struct clk_init_data { | |
269 | const char *name; | |
270 | const struct clk_ops *ops; | |
2893c379 | 271 | const char * const *parent_names; |
0197b3ea SK |
272 | u8 num_parents; |
273 | unsigned long flags; | |
274 | }; | |
275 | ||
276 | /** | |
277 | * struct clk_hw - handle for traversing from a struct clk to its corresponding | |
278 | * hardware-specific structure. struct clk_hw should be declared within struct | |
279 | * clk_foo and then referenced by the struct clk instance that uses struct | |
280 | * clk_foo's clk_ops | |
281 | * | |
035a61c3 TV |
282 | * @core: pointer to the struct clk_core instance that points back to this |
283 | * struct clk_hw instance | |
284 | * | |
285 | * @clk: pointer to the per-user struct clk instance that can be used to call | |
286 | * into the clk API | |
0197b3ea SK |
287 | * |
288 | * @init: pointer to struct clk_init_data that contains the init data shared | |
289 | * with the common clock framework. | |
290 | */ | |
291 | struct clk_hw { | |
035a61c3 | 292 | struct clk_core *core; |
0197b3ea | 293 | struct clk *clk; |
dc4cd941 | 294 | const struct clk_init_data *init; |
0197b3ea SK |
295 | }; |
296 | ||
9d9f78ed MT |
297 | /* |
298 | * DOC: Basic clock implementations common to many platforms | |
299 | * | |
300 | * Each basic clock hardware type is comprised of a structure describing the | |
301 | * clock hardware, implementations of the relevant callbacks in struct clk_ops, | |
302 | * unique flags for that hardware type, a registration function and an | |
303 | * alternative macro for static initialization | |
304 | */ | |
305 | ||
306 | /** | |
307 | * struct clk_fixed_rate - fixed-rate clock | |
308 | * @hw: handle between common and hardware-specific interfaces | |
309 | * @fixed_rate: constant frequency of clock | |
310 | */ | |
311 | struct clk_fixed_rate { | |
312 | struct clk_hw hw; | |
313 | unsigned long fixed_rate; | |
0903ea60 | 314 | unsigned long fixed_accuracy; |
9d9f78ed MT |
315 | u8 flags; |
316 | }; | |
317 | ||
5fd9c05c GT |
318 | #define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw) |
319 | ||
bffad66e | 320 | extern const struct clk_ops clk_fixed_rate_ops; |
9d9f78ed MT |
321 | struct clk *clk_register_fixed_rate(struct device *dev, const char *name, |
322 | const char *parent_name, unsigned long flags, | |
323 | unsigned long fixed_rate); | |
26ef56be SB |
324 | struct clk_hw *clk_hw_register_fixed_rate(struct device *dev, const char *name, |
325 | const char *parent_name, unsigned long flags, | |
326 | unsigned long fixed_rate); | |
0903ea60 BB |
327 | struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev, |
328 | const char *name, const char *parent_name, unsigned long flags, | |
329 | unsigned long fixed_rate, unsigned long fixed_accuracy); | |
0b225e41 | 330 | void clk_unregister_fixed_rate(struct clk *clk); |
26ef56be SB |
331 | struct clk_hw *clk_hw_register_fixed_rate_with_accuracy(struct device *dev, |
332 | const char *name, const char *parent_name, unsigned long flags, | |
333 | unsigned long fixed_rate, unsigned long fixed_accuracy); | |
52445637 | 334 | void clk_hw_unregister_fixed_rate(struct clk_hw *hw); |
26ef56be | 335 | |
015ba402 GL |
336 | void of_fixed_clk_setup(struct device_node *np); |
337 | ||
9d9f78ed MT |
338 | /** |
339 | * struct clk_gate - gating clock | |
340 | * | |
341 | * @hw: handle between common and hardware-specific interfaces | |
342 | * @reg: register controlling gate | |
343 | * @bit_idx: single bit controlling gate | |
344 | * @flags: hardware-specific flags | |
345 | * @lock: register lock | |
346 | * | |
347 | * Clock which can gate its output. Implements .enable & .disable | |
348 | * | |
349 | * Flags: | |
1f73f31a | 350 | * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to |
725b418b GU |
351 | * enable the clock. Setting this flag does the opposite: setting the bit |
352 | * disable the clock and clearing it enables the clock | |
04577994 | 353 | * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit |
725b418b GU |
354 | * of this register, and mask of gate bits are in higher 16-bit of this |
355 | * register. While setting the gate bits, higher 16-bit should also be | |
356 | * updated to indicate changing gate bits. | |
9d9f78ed MT |
357 | */ |
358 | struct clk_gate { | |
359 | struct clk_hw hw; | |
360 | void __iomem *reg; | |
361 | u8 bit_idx; | |
362 | u8 flags; | |
363 | spinlock_t *lock; | |
9d9f78ed MT |
364 | }; |
365 | ||
5fd9c05c GT |
366 | #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw) |
367 | ||
9d9f78ed | 368 | #define CLK_GATE_SET_TO_DISABLE BIT(0) |
04577994 | 369 | #define CLK_GATE_HIWORD_MASK BIT(1) |
9d9f78ed | 370 | |
bffad66e | 371 | extern const struct clk_ops clk_gate_ops; |
9d9f78ed MT |
372 | struct clk *clk_register_gate(struct device *dev, const char *name, |
373 | const char *parent_name, unsigned long flags, | |
374 | void __iomem *reg, u8 bit_idx, | |
375 | u8 clk_gate_flags, spinlock_t *lock); | |
e270d8cb SB |
376 | struct clk_hw *clk_hw_register_gate(struct device *dev, const char *name, |
377 | const char *parent_name, unsigned long flags, | |
378 | void __iomem *reg, u8 bit_idx, | |
379 | u8 clk_gate_flags, spinlock_t *lock); | |
4e3c021f | 380 | void clk_unregister_gate(struct clk *clk); |
e270d8cb | 381 | void clk_hw_unregister_gate(struct clk_hw *hw); |
0a9c869d | 382 | int clk_gate_is_enabled(struct clk_hw *hw); |
9d9f78ed | 383 | |
357c3f0a RN |
384 | struct clk_div_table { |
385 | unsigned int val; | |
386 | unsigned int div; | |
387 | }; | |
388 | ||
9d9f78ed MT |
389 | /** |
390 | * struct clk_divider - adjustable divider clock | |
391 | * | |
392 | * @hw: handle between common and hardware-specific interfaces | |
393 | * @reg: register containing the divider | |
394 | * @shift: shift to the divider bit field | |
395 | * @width: width of the divider bit field | |
357c3f0a | 396 | * @table: array of value/divider pairs, last entry should have div = 0 |
9d9f78ed MT |
397 | * @lock: register lock |
398 | * | |
399 | * Clock with an adjustable divider affecting its output frequency. Implements | |
400 | * .recalc_rate, .set_rate and .round_rate | |
401 | * | |
402 | * Flags: | |
403 | * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the | |
725b418b GU |
404 | * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is |
405 | * the raw value read from the register, with the value of zero considered | |
056b2053 | 406 | * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set. |
9d9f78ed | 407 | * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from |
725b418b | 408 | * the hardware register |
056b2053 SB |
409 | * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have |
410 | * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor. | |
411 | * Some hardware implementations gracefully handle this case and allow a | |
412 | * zero divisor by not modifying their input clock | |
413 | * (divide by one / bypass). | |
d57dfe75 | 414 | * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit |
725b418b GU |
415 | * of this register, and mask of divider bits are in higher 16-bit of this |
416 | * register. While setting the divider bits, higher 16-bit should also be | |
417 | * updated to indicate changing divider bits. | |
774b5143 MC |
418 | * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded |
419 | * to the closest integer instead of the up one. | |
79c6ab50 HS |
420 | * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should |
421 | * not be changed by the clock framework. | |
afe76c8f JQ |
422 | * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED |
423 | * except when the value read from the register is zero, the divisor is | |
424 | * 2^width of the field. | |
9d9f78ed MT |
425 | */ |
426 | struct clk_divider { | |
427 | struct clk_hw hw; | |
428 | void __iomem *reg; | |
429 | u8 shift; | |
430 | u8 width; | |
431 | u8 flags; | |
357c3f0a | 432 | const struct clk_div_table *table; |
9d9f78ed | 433 | spinlock_t *lock; |
9d9f78ed MT |
434 | }; |
435 | ||
e6d3cc7b | 436 | #define clk_div_mask(width) ((1 << (width)) - 1) |
5fd9c05c GT |
437 | #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) |
438 | ||
9d9f78ed MT |
439 | #define CLK_DIVIDER_ONE_BASED BIT(0) |
440 | #define CLK_DIVIDER_POWER_OF_TWO BIT(1) | |
056b2053 | 441 | #define CLK_DIVIDER_ALLOW_ZERO BIT(2) |
d57dfe75 | 442 | #define CLK_DIVIDER_HIWORD_MASK BIT(3) |
774b5143 | 443 | #define CLK_DIVIDER_ROUND_CLOSEST BIT(4) |
79c6ab50 | 444 | #define CLK_DIVIDER_READ_ONLY BIT(5) |
afe76c8f | 445 | #define CLK_DIVIDER_MAX_AT_ZERO BIT(6) |
9d9f78ed | 446 | |
bffad66e | 447 | extern const struct clk_ops clk_divider_ops; |
50359819 | 448 | extern const struct clk_ops clk_divider_ro_ops; |
bca9690b SB |
449 | |
450 | unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate, | |
451 | unsigned int val, const struct clk_div_table *table, | |
12a26c29 | 452 | unsigned long flags, unsigned long width); |
22833a91 MR |
453 | long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, |
454 | unsigned long rate, unsigned long *prate, | |
455 | const struct clk_div_table *table, | |
456 | u8 width, unsigned long flags); | |
b15ee490 JB |
457 | long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, |
458 | unsigned long rate, unsigned long *prate, | |
459 | const struct clk_div_table *table, u8 width, | |
460 | unsigned long flags, unsigned int val); | |
bca9690b SB |
461 | int divider_get_val(unsigned long rate, unsigned long parent_rate, |
462 | const struct clk_div_table *table, u8 width, | |
463 | unsigned long flags); | |
464 | ||
9d9f78ed MT |
465 | struct clk *clk_register_divider(struct device *dev, const char *name, |
466 | const char *parent_name, unsigned long flags, | |
467 | void __iomem *reg, u8 shift, u8 width, | |
468 | u8 clk_divider_flags, spinlock_t *lock); | |
eb7d264f SB |
469 | struct clk_hw *clk_hw_register_divider(struct device *dev, const char *name, |
470 | const char *parent_name, unsigned long flags, | |
471 | void __iomem *reg, u8 shift, u8 width, | |
472 | u8 clk_divider_flags, spinlock_t *lock); | |
357c3f0a RN |
473 | struct clk *clk_register_divider_table(struct device *dev, const char *name, |
474 | const char *parent_name, unsigned long flags, | |
475 | void __iomem *reg, u8 shift, u8 width, | |
476 | u8 clk_divider_flags, const struct clk_div_table *table, | |
477 | spinlock_t *lock); | |
eb7d264f SB |
478 | struct clk_hw *clk_hw_register_divider_table(struct device *dev, |
479 | const char *name, const char *parent_name, unsigned long flags, | |
480 | void __iomem *reg, u8 shift, u8 width, | |
481 | u8 clk_divider_flags, const struct clk_div_table *table, | |
482 | spinlock_t *lock); | |
4e3c021f | 483 | void clk_unregister_divider(struct clk *clk); |
eb7d264f | 484 | void clk_hw_unregister_divider(struct clk_hw *hw); |
9d9f78ed MT |
485 | |
486 | /** | |
487 | * struct clk_mux - multiplexer clock | |
488 | * | |
489 | * @hw: handle between common and hardware-specific interfaces | |
490 | * @reg: register controlling multiplexer | |
fe3f338f | 491 | * @table: array of register values corresponding to the parent index |
9d9f78ed | 492 | * @shift: shift to multiplexer bit field |
fe3f338f | 493 | * @mask: mask of mutliplexer bit field |
3566d40c | 494 | * @flags: hardware-specific flags |
9d9f78ed MT |
495 | * @lock: register lock |
496 | * | |
497 | * Clock with multiple selectable parents. Implements .get_parent, .set_parent | |
498 | * and .recalc_rate | |
499 | * | |
500 | * Flags: | |
501 | * CLK_MUX_INDEX_ONE - register index starts at 1, not 0 | |
1f73f31a | 502 | * CLK_MUX_INDEX_BIT - register index is a single bit (power of two) |
ba492e90 | 503 | * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this |
725b418b GU |
504 | * register, and mask of mux bits are in higher 16-bit of this register. |
505 | * While setting the mux bits, higher 16-bit should also be updated to | |
506 | * indicate changing mux bits. | |
15a02c1f SB |
507 | * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired |
508 | * frequency. | |
9d9f78ed MT |
509 | */ |
510 | struct clk_mux { | |
511 | struct clk_hw hw; | |
512 | void __iomem *reg; | |
ce4f3313 PDS |
513 | u32 *table; |
514 | u32 mask; | |
9d9f78ed | 515 | u8 shift; |
9d9f78ed MT |
516 | u8 flags; |
517 | spinlock_t *lock; | |
518 | }; | |
519 | ||
5fd9c05c GT |
520 | #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw) |
521 | ||
9d9f78ed MT |
522 | #define CLK_MUX_INDEX_ONE BIT(0) |
523 | #define CLK_MUX_INDEX_BIT BIT(1) | |
ba492e90 | 524 | #define CLK_MUX_HIWORD_MASK BIT(2) |
15a02c1f SB |
525 | #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */ |
526 | #define CLK_MUX_ROUND_CLOSEST BIT(4) | |
9d9f78ed | 527 | |
bffad66e | 528 | extern const struct clk_ops clk_mux_ops; |
c57acd14 | 529 | extern const struct clk_ops clk_mux_ro_ops; |
ce4f3313 | 530 | |
9d9f78ed | 531 | struct clk *clk_register_mux(struct device *dev, const char *name, |
2893c379 SH |
532 | const char * const *parent_names, u8 num_parents, |
533 | unsigned long flags, | |
9d9f78ed MT |
534 | void __iomem *reg, u8 shift, u8 width, |
535 | u8 clk_mux_flags, spinlock_t *lock); | |
264b3171 SB |
536 | struct clk_hw *clk_hw_register_mux(struct device *dev, const char *name, |
537 | const char * const *parent_names, u8 num_parents, | |
538 | unsigned long flags, | |
539 | void __iomem *reg, u8 shift, u8 width, | |
540 | u8 clk_mux_flags, spinlock_t *lock); | |
b2476490 | 541 | |
ce4f3313 | 542 | struct clk *clk_register_mux_table(struct device *dev, const char *name, |
2893c379 SH |
543 | const char * const *parent_names, u8 num_parents, |
544 | unsigned long flags, | |
ce4f3313 PDS |
545 | void __iomem *reg, u8 shift, u32 mask, |
546 | u8 clk_mux_flags, u32 *table, spinlock_t *lock); | |
264b3171 SB |
547 | struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name, |
548 | const char * const *parent_names, u8 num_parents, | |
549 | unsigned long flags, | |
550 | void __iomem *reg, u8 shift, u32 mask, | |
551 | u8 clk_mux_flags, u32 *table, spinlock_t *lock); | |
ce4f3313 | 552 | |
77deb66d JB |
553 | int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags, |
554 | unsigned int val); | |
555 | unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index); | |
556 | ||
4e3c021f | 557 | void clk_unregister_mux(struct clk *clk); |
264b3171 | 558 | void clk_hw_unregister_mux(struct clk_hw *hw); |
4e3c021f | 559 | |
79b16641 GC |
560 | void of_fixed_factor_clk_setup(struct device_node *node); |
561 | ||
f0948f59 SH |
562 | /** |
563 | * struct clk_fixed_factor - fixed multiplier and divider clock | |
564 | * | |
565 | * @hw: handle between common and hardware-specific interfaces | |
566 | * @mult: multiplier | |
567 | * @div: divider | |
568 | * | |
569 | * Clock with a fixed multiplier and divider. The output frequency is the | |
570 | * parent clock rate divided by div and multiplied by mult. | |
571 | * Implements .recalc_rate, .set_rate and .round_rate | |
572 | */ | |
573 | ||
574 | struct clk_fixed_factor { | |
575 | struct clk_hw hw; | |
576 | unsigned int mult; | |
577 | unsigned int div; | |
578 | }; | |
579 | ||
5fd9c05c GT |
580 | #define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw) |
581 | ||
3037e9ea | 582 | extern const struct clk_ops clk_fixed_factor_ops; |
f0948f59 SH |
583 | struct clk *clk_register_fixed_factor(struct device *dev, const char *name, |
584 | const char *parent_name, unsigned long flags, | |
585 | unsigned int mult, unsigned int div); | |
cbf9591f | 586 | void clk_unregister_fixed_factor(struct clk *clk); |
0759ac8a SB |
587 | struct clk_hw *clk_hw_register_fixed_factor(struct device *dev, |
588 | const char *name, const char *parent_name, unsigned long flags, | |
589 | unsigned int mult, unsigned int div); | |
590 | void clk_hw_unregister_fixed_factor(struct clk_hw *hw); | |
f0948f59 | 591 | |
e2d0e90f HK |
592 | /** |
593 | * struct clk_fractional_divider - adjustable fractional divider clock | |
594 | * | |
595 | * @hw: handle between common and hardware-specific interfaces | |
596 | * @reg: register containing the divider | |
597 | * @mshift: shift to the numerator bit field | |
598 | * @mwidth: width of the numerator bit field | |
599 | * @nshift: shift to the denominator bit field | |
600 | * @nwidth: width of the denominator bit field | |
601 | * @lock: register lock | |
602 | * | |
603 | * Clock with adjustable fractional divider affecting its output frequency. | |
604 | */ | |
e2d0e90f HK |
605 | struct clk_fractional_divider { |
606 | struct clk_hw hw; | |
607 | void __iomem *reg; | |
608 | u8 mshift; | |
934e2536 | 609 | u8 mwidth; |
e2d0e90f HK |
610 | u32 mmask; |
611 | u8 nshift; | |
934e2536 | 612 | u8 nwidth; |
e2d0e90f HK |
613 | u32 nmask; |
614 | u8 flags; | |
ec52e462 EZ |
615 | void (*approximation)(struct clk_hw *hw, |
616 | unsigned long rate, unsigned long *parent_rate, | |
617 | unsigned long *m, unsigned long *n); | |
e2d0e90f HK |
618 | spinlock_t *lock; |
619 | }; | |
620 | ||
5fd9c05c GT |
621 | #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw) |
622 | ||
e2d0e90f HK |
623 | extern const struct clk_ops clk_fractional_divider_ops; |
624 | struct clk *clk_register_fractional_divider(struct device *dev, | |
625 | const char *name, const char *parent_name, unsigned long flags, | |
626 | void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, | |
627 | u8 clk_divider_flags, spinlock_t *lock); | |
39b44cff SB |
628 | struct clk_hw *clk_hw_register_fractional_divider(struct device *dev, |
629 | const char *name, const char *parent_name, unsigned long flags, | |
630 | void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, | |
631 | u8 clk_divider_flags, spinlock_t *lock); | |
632 | void clk_hw_unregister_fractional_divider(struct clk_hw *hw); | |
e2d0e90f | 633 | |
f2e0a532 MR |
634 | /** |
635 | * struct clk_multiplier - adjustable multiplier clock | |
636 | * | |
637 | * @hw: handle between common and hardware-specific interfaces | |
638 | * @reg: register containing the multiplier | |
639 | * @shift: shift to the multiplier bit field | |
640 | * @width: width of the multiplier bit field | |
641 | * @lock: register lock | |
642 | * | |
643 | * Clock with an adjustable multiplier affecting its output frequency. | |
644 | * Implements .recalc_rate, .set_rate and .round_rate | |
645 | * | |
646 | * Flags: | |
647 | * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read | |
648 | * from the register, with 0 being a valid value effectively | |
649 | * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is | |
650 | * set, then a null multiplier will be considered as a bypass, | |
651 | * leaving the parent rate unmodified. | |
652 | * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be | |
653 | * rounded to the closest integer instead of the down one. | |
654 | */ | |
655 | struct clk_multiplier { | |
656 | struct clk_hw hw; | |
657 | void __iomem *reg; | |
658 | u8 shift; | |
659 | u8 width; | |
660 | u8 flags; | |
661 | spinlock_t *lock; | |
662 | }; | |
663 | ||
5fd9c05c GT |
664 | #define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw) |
665 | ||
f2e0a532 MR |
666 | #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0) |
667 | #define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1) | |
668 | ||
669 | extern const struct clk_ops clk_multiplier_ops; | |
670 | ||
ece70094 PG |
671 | /*** |
672 | * struct clk_composite - aggregate clock of mux, divider and gate clocks | |
673 | * | |
674 | * @hw: handle between common and hardware-specific interfaces | |
d3a1c7be MT |
675 | * @mux_hw: handle between composite and hardware-specific mux clock |
676 | * @rate_hw: handle between composite and hardware-specific rate clock | |
677 | * @gate_hw: handle between composite and hardware-specific gate clock | |
ece70094 | 678 | * @mux_ops: clock ops for mux |
d3a1c7be | 679 | * @rate_ops: clock ops for rate |
ece70094 PG |
680 | * @gate_ops: clock ops for gate |
681 | */ | |
682 | struct clk_composite { | |
683 | struct clk_hw hw; | |
684 | struct clk_ops ops; | |
685 | ||
686 | struct clk_hw *mux_hw; | |
d3a1c7be | 687 | struct clk_hw *rate_hw; |
ece70094 PG |
688 | struct clk_hw *gate_hw; |
689 | ||
690 | const struct clk_ops *mux_ops; | |
d3a1c7be | 691 | const struct clk_ops *rate_ops; |
ece70094 PG |
692 | const struct clk_ops *gate_ops; |
693 | }; | |
694 | ||
5fd9c05c GT |
695 | #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw) |
696 | ||
ece70094 | 697 | struct clk *clk_register_composite(struct device *dev, const char *name, |
2893c379 | 698 | const char * const *parent_names, int num_parents, |
ece70094 | 699 | struct clk_hw *mux_hw, const struct clk_ops *mux_ops, |
d3a1c7be | 700 | struct clk_hw *rate_hw, const struct clk_ops *rate_ops, |
ece70094 PG |
701 | struct clk_hw *gate_hw, const struct clk_ops *gate_ops, |
702 | unsigned long flags); | |
92a39d90 | 703 | void clk_unregister_composite(struct clk *clk); |
49cb392d SB |
704 | struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name, |
705 | const char * const *parent_names, int num_parents, | |
706 | struct clk_hw *mux_hw, const struct clk_ops *mux_ops, | |
707 | struct clk_hw *rate_hw, const struct clk_ops *rate_ops, | |
708 | struct clk_hw *gate_hw, const struct clk_ops *gate_ops, | |
709 | unsigned long flags); | |
710 | void clk_hw_unregister_composite(struct clk_hw *hw); | |
ece70094 | 711 | |
c873d14d JS |
712 | /*** |
713 | * struct clk_gpio_gate - gpio gated clock | |
714 | * | |
715 | * @hw: handle between common and hardware-specific interfaces | |
716 | * @gpiod: gpio descriptor | |
717 | * | |
718 | * Clock with a gpio control for enabling and disabling the parent clock. | |
719 | * Implements .enable, .disable and .is_enabled | |
720 | */ | |
721 | ||
722 | struct clk_gpio { | |
723 | struct clk_hw hw; | |
724 | struct gpio_desc *gpiod; | |
725 | }; | |
726 | ||
5fd9c05c GT |
727 | #define to_clk_gpio(_hw) container_of(_hw, struct clk_gpio, hw) |
728 | ||
c873d14d JS |
729 | extern const struct clk_ops clk_gpio_gate_ops; |
730 | struct clk *clk_register_gpio_gate(struct device *dev, const char *name, | |
908a543a | 731 | const char *parent_name, struct gpio_desc *gpiod, |
c873d14d | 732 | unsigned long flags); |
b120743a | 733 | struct clk_hw *clk_hw_register_gpio_gate(struct device *dev, const char *name, |
908a543a | 734 | const char *parent_name, struct gpio_desc *gpiod, |
b120743a SB |
735 | unsigned long flags); |
736 | void clk_hw_unregister_gpio_gate(struct clk_hw *hw); | |
c873d14d | 737 | |
80eeb1f0 SS |
738 | /** |
739 | * struct clk_gpio_mux - gpio controlled clock multiplexer | |
740 | * | |
741 | * @hw: see struct clk_gpio | |
742 | * @gpiod: gpio descriptor to select the parent of this clock multiplexer | |
743 | * | |
744 | * Clock with a gpio control for selecting the parent clock. | |
745 | * Implements .get_parent, .set_parent and .determine_rate | |
746 | */ | |
747 | ||
748 | extern const struct clk_ops clk_gpio_mux_ops; | |
749 | struct clk *clk_register_gpio_mux(struct device *dev, const char *name, | |
908a543a LW |
750 | const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod, |
751 | unsigned long flags); | |
b120743a | 752 | struct clk_hw *clk_hw_register_gpio_mux(struct device *dev, const char *name, |
908a543a LW |
753 | const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod, |
754 | unsigned long flags); | |
b120743a | 755 | void clk_hw_unregister_gpio_mux(struct clk_hw *hw); |
80eeb1f0 | 756 | |
b2476490 MT |
757 | /** |
758 | * clk_register - allocate a new clock, register it and return an opaque cookie | |
759 | * @dev: device that is registering this clock | |
b2476490 | 760 | * @hw: link to hardware-specific clock data |
b2476490 MT |
761 | * |
762 | * clk_register is the primary interface for populating the clock tree with new | |
763 | * clock nodes. It returns a pointer to the newly allocated struct clk which | |
764 | * cannot be dereferenced by driver code but may be used in conjuction with the | |
d1302a36 MT |
765 | * rest of the clock API. In the event of an error clk_register will return an |
766 | * error code; drivers must test for an error code after calling clk_register. | |
b2476490 | 767 | */ |
0197b3ea | 768 | struct clk *clk_register(struct device *dev, struct clk_hw *hw); |
46c8773a | 769 | struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw); |
b2476490 | 770 | |
4143804c SB |
771 | int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw); |
772 | int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw); | |
773 | ||
1df5c939 | 774 | void clk_unregister(struct clk *clk); |
46c8773a | 775 | void devm_clk_unregister(struct device *dev, struct clk *clk); |
1df5c939 | 776 | |
4143804c SB |
777 | void clk_hw_unregister(struct clk_hw *hw); |
778 | void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw); | |
779 | ||
b2476490 | 780 | /* helper functions */ |
b76281cb | 781 | const char *__clk_get_name(const struct clk *clk); |
e7df6f6e | 782 | const char *clk_hw_get_name(const struct clk_hw *hw); |
b2476490 | 783 | struct clk_hw *__clk_get_hw(struct clk *clk); |
e7df6f6e SB |
784 | unsigned int clk_hw_get_num_parents(const struct clk_hw *hw); |
785 | struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw); | |
786 | struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw, | |
1a9c069c | 787 | unsigned int index); |
93874681 | 788 | unsigned int __clk_get_enable_count(struct clk *clk); |
e7df6f6e | 789 | unsigned long clk_hw_get_rate(const struct clk_hw *hw); |
b2476490 | 790 | unsigned long __clk_get_flags(struct clk *clk); |
e7df6f6e SB |
791 | unsigned long clk_hw_get_flags(const struct clk_hw *hw); |
792 | bool clk_hw_is_prepared(const struct clk_hw *hw); | |
e55a839a | 793 | bool clk_hw_rate_is_protected(const struct clk_hw *hw); |
be68bf88 | 794 | bool clk_hw_is_enabled(const struct clk_hw *hw); |
2ac6b1f5 | 795 | bool __clk_is_enabled(struct clk *clk); |
b2476490 | 796 | struct clk *__clk_lookup(const char *name); |
0817b62c BB |
797 | int __clk_mux_determine_rate(struct clk_hw *hw, |
798 | struct clk_rate_request *req); | |
799 | int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req); | |
800 | int __clk_mux_determine_rate_closest(struct clk_hw *hw, | |
801 | struct clk_rate_request *req); | |
4ad69b80 JB |
802 | int clk_mux_determine_rate_flags(struct clk_hw *hw, |
803 | struct clk_rate_request *req, | |
804 | unsigned long flags); | |
42c86547 | 805 | void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent); |
9783c0d9 SB |
806 | void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate, |
807 | unsigned long max_rate); | |
b2476490 | 808 | |
2e65d8bf JMC |
809 | static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src) |
810 | { | |
811 | dst->clk = src->clk; | |
812 | dst->core = src->core; | |
813 | } | |
814 | ||
22833a91 MR |
815 | static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate, |
816 | unsigned long *prate, | |
817 | const struct clk_div_table *table, | |
818 | u8 width, unsigned long flags) | |
819 | { | |
820 | return divider_round_rate_parent(hw, clk_hw_get_parent(hw), | |
821 | rate, prate, table, width, flags); | |
822 | } | |
823 | ||
b15ee490 JB |
824 | static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate, |
825 | unsigned long *prate, | |
826 | const struct clk_div_table *table, | |
827 | u8 width, unsigned long flags, | |
828 | unsigned int val) | |
829 | { | |
830 | return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw), | |
831 | rate, prate, table, width, flags, | |
832 | val); | |
833 | } | |
834 | ||
b2476490 MT |
835 | /* |
836 | * FIXME clock api without lock protection | |
837 | */ | |
1a9c069c | 838 | unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate); |
b2476490 | 839 | |
766e6a4e GL |
840 | struct of_device_id; |
841 | ||
0b151deb SH |
842 | struct clk_onecell_data { |
843 | struct clk **clks; | |
844 | unsigned int clk_num; | |
845 | }; | |
846 | ||
0861e5b8 | 847 | struct clk_hw_onecell_data { |
5963f19c | 848 | unsigned int num; |
0861e5b8 SB |
849 | struct clk_hw *hws[]; |
850 | }; | |
851 | ||
819b4861 TK |
852 | extern struct of_device_id __clk_of_table; |
853 | ||
54196ccb | 854 | #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn) |
0b151deb | 855 | |
c7296c51 RRD |
856 | /* |
857 | * Use this macro when you have a driver that requires two initialization | |
858 | * routines, one at of_clk_init(), and one at platform device probe | |
859 | */ | |
860 | #define CLK_OF_DECLARE_DRIVER(name, compat, fn) \ | |
339e1e54 | 861 | static void __init name##_of_clk_init_driver(struct device_node *np) \ |
c7296c51 RRD |
862 | { \ |
863 | of_node_clear_flag(np, OF_POPULATED); \ | |
864 | fn(np); \ | |
865 | } \ | |
866 | OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver) | |
867 | ||
1ded879e CZ |
868 | #define CLK_HW_INIT(_name, _parent, _ops, _flags) \ |
869 | (&(struct clk_init_data) { \ | |
870 | .flags = _flags, \ | |
871 | .name = _name, \ | |
872 | .parent_names = (const char *[]) { _parent }, \ | |
873 | .num_parents = 1, \ | |
874 | .ops = _ops, \ | |
875 | }) | |
876 | ||
877 | #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \ | |
878 | (&(struct clk_init_data) { \ | |
879 | .flags = _flags, \ | |
880 | .name = _name, \ | |
881 | .parent_names = _parents, \ | |
882 | .num_parents = ARRAY_SIZE(_parents), \ | |
883 | .ops = _ops, \ | |
884 | }) | |
885 | ||
886 | #define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \ | |
887 | (&(struct clk_init_data) { \ | |
888 | .flags = _flags, \ | |
889 | .name = _name, \ | |
890 | .parent_names = NULL, \ | |
891 | .num_parents = 0, \ | |
892 | .ops = _ops, \ | |
893 | }) | |
894 | ||
895 | #define CLK_FIXED_FACTOR(_struct, _name, _parent, \ | |
896 | _div, _mult, _flags) \ | |
897 | struct clk_fixed_factor _struct = { \ | |
898 | .div = _div, \ | |
899 | .mult = _mult, \ | |
900 | .hw.init = CLK_HW_INIT(_name, \ | |
901 | _parent, \ | |
902 | &clk_fixed_factor_ops, \ | |
903 | _flags), \ | |
904 | } | |
905 | ||
0b151deb | 906 | #ifdef CONFIG_OF |
766e6a4e GL |
907 | int of_clk_add_provider(struct device_node *np, |
908 | struct clk *(*clk_src_get)(struct of_phandle_args *args, | |
909 | void *data), | |
910 | void *data); | |
0861e5b8 SB |
911 | int of_clk_add_hw_provider(struct device_node *np, |
912 | struct clk_hw *(*get)(struct of_phandle_args *clkspec, | |
913 | void *data), | |
914 | void *data); | |
aa795c41 SB |
915 | int devm_of_clk_add_hw_provider(struct device *dev, |
916 | struct clk_hw *(*get)(struct of_phandle_args *clkspec, | |
917 | void *data), | |
918 | void *data); | |
766e6a4e | 919 | void of_clk_del_provider(struct device_node *np); |
aa795c41 | 920 | void devm_of_clk_del_provider(struct device *dev); |
766e6a4e GL |
921 | struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, |
922 | void *data); | |
0861e5b8 SB |
923 | struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec, |
924 | void *data); | |
494bfec9 | 925 | struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data); |
0861e5b8 SB |
926 | struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec, |
927 | void *data); | |
2e61dfb3 DN |
928 | int of_clk_parent_fill(struct device_node *np, const char **parents, |
929 | unsigned int size); | |
d56f8994 LJ |
930 | int of_clk_detect_critical(struct device_node *np, int index, |
931 | unsigned long *flags); | |
766e6a4e | 932 | |
0b151deb | 933 | #else /* !CONFIG_OF */ |
f2f6c255 | 934 | |
0b151deb SH |
935 | static inline int of_clk_add_provider(struct device_node *np, |
936 | struct clk *(*clk_src_get)(struct of_phandle_args *args, | |
937 | void *data), | |
938 | void *data) | |
939 | { | |
940 | return 0; | |
941 | } | |
0861e5b8 SB |
942 | static inline int of_clk_add_hw_provider(struct device_node *np, |
943 | struct clk_hw *(*get)(struct of_phandle_args *clkspec, | |
944 | void *data), | |
945 | void *data) | |
946 | { | |
947 | return 0; | |
948 | } | |
aa795c41 SB |
949 | static inline int devm_of_clk_add_hw_provider(struct device *dev, |
950 | struct clk_hw *(*get)(struct of_phandle_args *clkspec, | |
951 | void *data), | |
952 | void *data) | |
953 | { | |
954 | return 0; | |
955 | } | |
20dd882a | 956 | static inline void of_clk_del_provider(struct device_node *np) {} |
aa795c41 | 957 | static inline void devm_of_clk_del_provider(struct device *dev) {} |
0b151deb SH |
958 | static inline struct clk *of_clk_src_simple_get( |
959 | struct of_phandle_args *clkspec, void *data) | |
960 | { | |
961 | return ERR_PTR(-ENOENT); | |
962 | } | |
0861e5b8 SB |
963 | static inline struct clk_hw * |
964 | of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data) | |
965 | { | |
966 | return ERR_PTR(-ENOENT); | |
967 | } | |
0b151deb SH |
968 | static inline struct clk *of_clk_src_onecell_get( |
969 | struct of_phandle_args *clkspec, void *data) | |
970 | { | |
971 | return ERR_PTR(-ENOENT); | |
972 | } | |
0861e5b8 SB |
973 | static inline struct clk_hw * |
974 | of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data) | |
975 | { | |
976 | return ERR_PTR(-ENOENT); | |
977 | } | |
679c51cf SB |
978 | static inline int of_clk_parent_fill(struct device_node *np, |
979 | const char **parents, unsigned int size) | |
980 | { | |
981 | return 0; | |
982 | } | |
d56f8994 LJ |
983 | static inline int of_clk_detect_critical(struct device_node *np, int index, |
984 | unsigned long *flags) | |
985 | { | |
986 | return 0; | |
987 | } | |
0b151deb | 988 | #endif /* CONFIG_OF */ |
aa514ce3 GS |
989 | |
990 | /* | |
991 | * wrap access to peripherals in accessor routines | |
992 | * for improved portability across platforms | |
993 | */ | |
994 | ||
6d8cdb68 GS |
995 | #if IS_ENABLED(CONFIG_PPC) |
996 | ||
997 | static inline u32 clk_readl(u32 __iomem *reg) | |
998 | { | |
999 | return ioread32be(reg); | |
1000 | } | |
1001 | ||
1002 | static inline void clk_writel(u32 val, u32 __iomem *reg) | |
1003 | { | |
1004 | iowrite32be(val, reg); | |
1005 | } | |
1006 | ||
1007 | #else /* platform dependent I/O accessors */ | |
1008 | ||
aa514ce3 GS |
1009 | static inline u32 clk_readl(u32 __iomem *reg) |
1010 | { | |
1011 | return readl(reg); | |
1012 | } | |
1013 | ||
1014 | static inline void clk_writel(u32 val, u32 __iomem *reg) | |
1015 | { | |
1016 | writel(val, reg); | |
1017 | } | |
1018 | ||
6d8cdb68 GS |
1019 | #endif /* platform dependent I/O accessors */ |
1020 | ||
43536548 K |
1021 | void clk_gate_restore_context(struct clk_hw *hw); |
1022 | ||
b2476490 MT |
1023 | #endif /* CONFIG_COMMON_CLK */ |
1024 | #endif /* CLK_PROVIDER_H */ |