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ebafb63d | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
b2476490 | 2 | /* |
b2476490 MT |
3 | * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com> |
4 | * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org> | |
b2476490 MT |
5 | */ |
6 | #ifndef __LINUX_CLK_PROVIDER_H | |
7 | #define __LINUX_CLK_PROVIDER_H | |
8 | ||
355bb165 | 9 | #include <linux/of.h> |
eb06d6bb | 10 | #include <linux/of_clk.h> |
b2476490 | 11 | |
b2476490 MT |
12 | /* |
13 | * flags used across common struct clk. these flags should only affect the | |
14 | * top-level framework. custom flags for dealing with hardware specifics | |
15 | * belong in struct clk_foo | |
a6059ab9 GU |
16 | * |
17 | * Please update clk_flags[] in drivers/clk/clk.c when making changes here! | |
b2476490 MT |
18 | */ |
19 | #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ | |
20 | #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ | |
21 | #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ | |
22 | #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ | |
b9610e74 | 23 | /* unused */ |
90b6c5c7 | 24 | /* unused */ |
a093bde2 | 25 | #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ |
819c1de3 | 26 | #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ |
5279fc40 | 27 | #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */ |
d8d91987 | 28 | #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */ |
2eb8c710 | 29 | #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */ |
32b9b109 | 30 | #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */ |
a4b3518d DA |
31 | /* parents need enable during gate/ungate, set rate and re-parent */ |
32 | #define CLK_OPS_PARENT_ENABLE BIT(12) | |
9fba738a JB |
33 | /* duty cycle call may be forwarded to the parent clock */ |
34 | #define CLK_DUTY_CYCLE_PARENT BIT(13) | |
b2476490 | 35 | |
61ae7656 | 36 | struct clk; |
0197b3ea | 37 | struct clk_hw; |
035a61c3 | 38 | struct clk_core; |
c646cbf1 | 39 | struct dentry; |
0197b3ea | 40 | |
0817b62c BB |
41 | /** |
42 | * struct clk_rate_request - Structure encoding the clk constraints that | |
43 | * a clock user might require. | |
44 | * | |
c35e84b0 MR |
45 | * Should be initialized by calling clk_hw_init_rate_request(). |
46 | * | |
ef13f8b6 | 47 | * @core: Pointer to the struct clk_core affected by this request |
0817b62c BB |
48 | * @rate: Requested clock rate. This field will be adjusted by |
49 | * clock drivers according to hardware capabilities. | |
50 | * @min_rate: Minimum rate imposed by clk users. | |
1971dfb7 | 51 | * @max_rate: Maximum rate imposed by clk users. |
0817b62c BB |
52 | * @best_parent_rate: The best parent rate a parent can provide to fulfill the |
53 | * requested constraints. | |
54 | * @best_parent_hw: The most appropriate parent clock that fulfills the | |
55 | * requested constraints. | |
56 | * | |
57 | */ | |
58 | struct clk_rate_request { | |
ef13f8b6 | 59 | struct clk_core *core; |
0817b62c BB |
60 | unsigned long rate; |
61 | unsigned long min_rate; | |
62 | unsigned long max_rate; | |
63 | unsigned long best_parent_rate; | |
64 | struct clk_hw *best_parent_hw; | |
65 | }; | |
66 | ||
c35e84b0 MR |
67 | void clk_hw_init_rate_request(const struct clk_hw *hw, |
68 | struct clk_rate_request *req, | |
69 | unsigned long rate); | |
262ca38f MR |
70 | void clk_hw_forward_rate_request(const struct clk_hw *core, |
71 | const struct clk_rate_request *old_req, | |
72 | const struct clk_hw *parent, | |
73 | struct clk_rate_request *req, | |
74 | unsigned long parent_rate); | |
c35e84b0 | 75 | |
9fba738a JB |
76 | /** |
77 | * struct clk_duty - Struture encoding the duty cycle ratio of a clock | |
78 | * | |
79 | * @num: Numerator of the duty cycle ratio | |
80 | * @den: Denominator of the duty cycle ratio | |
81 | */ | |
82 | struct clk_duty { | |
83 | unsigned int num; | |
84 | unsigned int den; | |
85 | }; | |
86 | ||
b2476490 MT |
87 | /** |
88 | * struct clk_ops - Callback operations for hardware clocks; these are to | |
89 | * be provided by the clock implementation, and will be called by drivers | |
90 | * through the clk_* api. | |
91 | * | |
92 | * @prepare: Prepare the clock for enabling. This must not return until | |
725b418b GU |
93 | * the clock is fully prepared, and it's safe to call clk_enable. |
94 | * This callback is intended to allow clock implementations to | |
95 | * do any initialisation that may sleep. Called with | |
96 | * prepare_lock held. | |
b2476490 MT |
97 | * |
98 | * @unprepare: Release the clock from its prepared state. This will typically | |
725b418b GU |
99 | * undo any work done in the @prepare callback. Called with |
100 | * prepare_lock held. | |
b2476490 | 101 | * |
3d6ee287 UH |
102 | * @is_prepared: Queries the hardware to determine if the clock is prepared. |
103 | * This function is allowed to sleep. Optional, if this op is not | |
104 | * set then the prepare count will be used. | |
105 | * | |
3cc8247f UH |
106 | * @unprepare_unused: Unprepare the clock atomically. Only called from |
107 | * clk_disable_unused for prepare clocks with special needs. | |
108 | * Called with prepare mutex held. This function may sleep. | |
109 | * | |
b2476490 | 110 | * @enable: Enable the clock atomically. This must not return until the |
725b418b GU |
111 | * clock is generating a valid clock signal, usable by consumer |
112 | * devices. Called with enable_lock held. This function must not | |
113 | * sleep. | |
b2476490 MT |
114 | * |
115 | * @disable: Disable the clock atomically. Called with enable_lock held. | |
725b418b | 116 | * This function must not sleep. |
b2476490 | 117 | * |
119c7127 | 118 | * @is_enabled: Queries the hardware to determine if the clock is enabled. |
725b418b GU |
119 | * This function must not sleep. Optional, if this op is not |
120 | * set then the enable count will be used. | |
119c7127 | 121 | * |
7c045a55 MT |
122 | * @disable_unused: Disable the clock atomically. Only called from |
123 | * clk_disable_unused for gate clocks with special needs. | |
124 | * Called with enable_lock held. This function must not | |
125 | * sleep. | |
126 | * | |
8b95d1ce RD |
127 | * @save_context: Save the context of the clock in prepration for poweroff. |
128 | * | |
129 | * @restore_context: Restore the context of the clock after a restoration | |
130 | * of power. | |
131 | * | |
7ce3e8cc | 132 | * @recalc_rate Recalculate the rate of this clock, by querying hardware. The |
725b418b | 133 | * parent rate is an input parameter. It is up to the caller to |
f24a0b1c MR |
134 | * ensure that the prepare_mutex is held across this call. If the |
135 | * driver cannot figure out a rate for this clock, it must return | |
136 | * 0. Returns the calculated rate. Optional, but recommended - if | |
725b418b | 137 | * this op is not set then clock rate will be initialized to 0. |
b2476490 MT |
138 | * |
139 | * @round_rate: Given a target rate as input, returns the closest rate actually | |
54e73016 GU |
140 | * supported by the clock. The parent rate is an input/output |
141 | * parameter. | |
b2476490 | 142 | * |
71472c0c JH |
143 | * @determine_rate: Given a target rate as input, returns the closest rate |
144 | * actually supported by the clock, and optionally the parent clock | |
145 | * that should be used to provide the clock rate. | |
146 | * | |
b2476490 | 147 | * @set_parent: Change the input source of this clock; for clocks with multiple |
54e73016 GU |
148 | * possible parents specify a new parent by passing in the index |
149 | * as a u8 corresponding to the parent in either the .parent_names | |
150 | * or .parents arrays. This function in affect translates an | |
151 | * array index into the value programmed into the hardware. | |
152 | * Returns 0 on success, -EERROR otherwise. | |
153 | * | |
b2476490 | 154 | * @get_parent: Queries the hardware to determine the parent of a clock. The |
725b418b GU |
155 | * return value is a u8 which specifies the index corresponding to |
156 | * the parent clock. This index can be applied to either the | |
157 | * .parent_names or .parents arrays. In short, this function | |
158 | * translates the parent value read from hardware into an array | |
159 | * index. Currently only called when the clock is initialized by | |
160 | * __clk_init. This callback is mandatory for clocks with | |
161 | * multiple parents. It is optional (and unnecessary) for clocks | |
162 | * with 0 or 1 parents. | |
b2476490 | 163 | * |
1c0035d7 SG |
164 | * @set_rate: Change the rate of this clock. The requested rate is specified |
165 | * by the second argument, which should typically be the return | |
166 | * of .round_rate call. The third argument gives the parent rate | |
167 | * which is likely helpful for most .set_rate implementation. | |
168 | * Returns 0 on success, -EERROR otherwise. | |
b2476490 | 169 | * |
3fa2252b SB |
170 | * @set_rate_and_parent: Change the rate and the parent of this clock. The |
171 | * requested rate is specified by the second argument, which | |
172 | * should typically be the return of .round_rate call. The | |
173 | * third argument gives the parent rate which is likely helpful | |
174 | * for most .set_rate_and_parent implementation. The fourth | |
175 | * argument gives the parent index. This callback is optional (and | |
176 | * unnecessary) for clocks with 0 or 1 parents as well as | |
177 | * for clocks that can tolerate switching the rate and the parent | |
178 | * separately via calls to .set_parent and .set_rate. | |
179 | * Returns 0 on success, -EERROR otherwise. | |
180 | * | |
54e73016 GU |
181 | * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy |
182 | * is expressed in ppb (parts per billion). The parent accuracy is | |
183 | * an input parameter. | |
184 | * Returns the calculated accuracy. Optional - if this op is not | |
185 | * set then clock accuracy will be initialized to parent accuracy | |
186 | * or 0 (perfect clock) if clock has no parent. | |
187 | * | |
9824cf73 MR |
188 | * @get_phase: Queries the hardware to get the current phase of a clock. |
189 | * Returned values are 0-359 degrees on success, negative | |
190 | * error codes on failure. | |
191 | * | |
e59c5371 MT |
192 | * @set_phase: Shift the phase this clock signal in degrees specified |
193 | * by the second argument. Valid values for degrees are | |
194 | * 0-359. Return 0 on success, otherwise -EERROR. | |
195 | * | |
9fba738a JB |
196 | * @get_duty_cycle: Queries the hardware to get the current duty cycle ratio |
197 | * of a clock. Returned values denominator cannot be 0 and must be | |
198 | * superior or equal to the numerator. | |
199 | * | |
200 | * @set_duty_cycle: Apply the duty cycle ratio to this clock signal specified by | |
201 | * the numerator (2nd argurment) and denominator (3rd argument). | |
202 | * Argument must be a valid ratio (denominator > 0 | |
203 | * and >= numerator) Return 0 on success, otherwise -EERROR. | |
204 | * | |
54e73016 | 205 | * @init: Perform platform-specific initialization magic. |
6c4411f1 | 206 | * This is not used by any of the basic clock types. |
89d079dc JB |
207 | * This callback exist for HW which needs to perform some |
208 | * initialisation magic for CCF to get an accurate view of the | |
209 | * clock. It may also be used dynamic resource allocation is | |
210 | * required. It shall not used to deal with clock parameters, | |
211 | * such as rate or parents. | |
212 | * Returns 0 on success, -EERROR otherwise. | |
54e73016 | 213 | * |
f873744c JB |
214 | * @terminate: Free any resource allocated by init. |
215 | * | |
c646cbf1 AE |
216 | * @debug_init: Set up type-specific debugfs entries for this clock. This |
217 | * is called once, after the debugfs directory entry for this | |
218 | * clock has been created. The dentry pointer representing that | |
219 | * directory is provided as an argument. Called with | |
220 | * prepare_lock held. Returns 0 on success, -EERROR otherwise. | |
221 | * | |
3fa2252b | 222 | * |
b2476490 MT |
223 | * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow |
224 | * implementations to split any work between atomic (enable) and sleepable | |
225 | * (prepare) contexts. If enabling a clock requires code that might sleep, | |
226 | * this must be done in clk_prepare. Clock enable code that will never be | |
7ce3e8cc | 227 | * called in a sleepable context may be implemented in clk_enable. |
b2476490 MT |
228 | * |
229 | * Typically, drivers will call clk_prepare when a clock may be needed later | |
230 | * (eg. when a device is opened), and clk_enable when the clock is actually | |
231 | * required (eg. from an interrupt). Note that clk_prepare MUST have been | |
232 | * called before clk_enable. | |
233 | */ | |
234 | struct clk_ops { | |
235 | int (*prepare)(struct clk_hw *hw); | |
236 | void (*unprepare)(struct clk_hw *hw); | |
3d6ee287 | 237 | int (*is_prepared)(struct clk_hw *hw); |
3cc8247f | 238 | void (*unprepare_unused)(struct clk_hw *hw); |
b2476490 MT |
239 | int (*enable)(struct clk_hw *hw); |
240 | void (*disable)(struct clk_hw *hw); | |
241 | int (*is_enabled)(struct clk_hw *hw); | |
7c045a55 | 242 | void (*disable_unused)(struct clk_hw *hw); |
8b95d1ce RD |
243 | int (*save_context)(struct clk_hw *hw); |
244 | void (*restore_context)(struct clk_hw *hw); | |
b2476490 MT |
245 | unsigned long (*recalc_rate)(struct clk_hw *hw, |
246 | unsigned long parent_rate); | |
54e73016 GU |
247 | long (*round_rate)(struct clk_hw *hw, unsigned long rate, |
248 | unsigned long *parent_rate); | |
0817b62c BB |
249 | int (*determine_rate)(struct clk_hw *hw, |
250 | struct clk_rate_request *req); | |
b2476490 MT |
251 | int (*set_parent)(struct clk_hw *hw, u8 index); |
252 | u8 (*get_parent)(struct clk_hw *hw); | |
54e73016 GU |
253 | int (*set_rate)(struct clk_hw *hw, unsigned long rate, |
254 | unsigned long parent_rate); | |
3fa2252b SB |
255 | int (*set_rate_and_parent)(struct clk_hw *hw, |
256 | unsigned long rate, | |
257 | unsigned long parent_rate, u8 index); | |
5279fc40 BB |
258 | unsigned long (*recalc_accuracy)(struct clk_hw *hw, |
259 | unsigned long parent_accuracy); | |
9824cf73 | 260 | int (*get_phase)(struct clk_hw *hw); |
e59c5371 | 261 | int (*set_phase)(struct clk_hw *hw, int degrees); |
9fba738a JB |
262 | int (*get_duty_cycle)(struct clk_hw *hw, |
263 | struct clk_duty *duty); | |
264 | int (*set_duty_cycle)(struct clk_hw *hw, | |
265 | struct clk_duty *duty); | |
89d079dc | 266 | int (*init)(struct clk_hw *hw); |
f873744c | 267 | void (*terminate)(struct clk_hw *hw); |
d75d50c0 | 268 | void (*debug_init)(struct clk_hw *hw, struct dentry *dentry); |
b2476490 MT |
269 | }; |
270 | ||
fc0c209c SB |
271 | /** |
272 | * struct clk_parent_data - clk parent information | |
273 | * @hw: parent clk_hw pointer (used for clk providers with internal clks) | |
274 | * @fw_name: parent name local to provider registering clk | |
275 | * @name: globally unique parent name (used as a fallback) | |
601b6e93 | 276 | * @index: parent index local to provider registering clk (if @fw_name absent) |
fc0c209c SB |
277 | */ |
278 | struct clk_parent_data { | |
279 | const struct clk_hw *hw; | |
280 | const char *fw_name; | |
281 | const char *name; | |
601b6e93 | 282 | int index; |
fc0c209c SB |
283 | }; |
284 | ||
0197b3ea SK |
285 | /** |
286 | * struct clk_init_data - holds init data that's common to all clocks and is | |
287 | * shared between the clock provider and the common clock framework. | |
288 | * | |
289 | * @name: clock name | |
290 | * @ops: operations this clock supports | |
291 | * @parent_names: array of string names for all possible parents | |
fc0c209c SB |
292 | * @parent_data: array of parent data for all possible parents (when some |
293 | * parents are external to the clk controller) | |
294 | * @parent_hws: array of pointers to all possible parents (when all parents | |
295 | * are internal to the clk controller) | |
0197b3ea SK |
296 | * @num_parents: number of possible parents |
297 | * @flags: framework-level hints and quirks | |
298 | */ | |
299 | struct clk_init_data { | |
300 | const char *name; | |
301 | const struct clk_ops *ops; | |
fc0c209c | 302 | /* Only one of the following three should be assigned */ |
2893c379 | 303 | const char * const *parent_names; |
fc0c209c SB |
304 | const struct clk_parent_data *parent_data; |
305 | const struct clk_hw **parent_hws; | |
0197b3ea SK |
306 | u8 num_parents; |
307 | unsigned long flags; | |
308 | }; | |
309 | ||
310 | /** | |
311 | * struct clk_hw - handle for traversing from a struct clk to its corresponding | |
312 | * hardware-specific structure. struct clk_hw should be declared within struct | |
313 | * clk_foo and then referenced by the struct clk instance that uses struct | |
314 | * clk_foo's clk_ops | |
315 | * | |
035a61c3 TV |
316 | * @core: pointer to the struct clk_core instance that points back to this |
317 | * struct clk_hw instance | |
318 | * | |
319 | * @clk: pointer to the per-user struct clk instance that can be used to call | |
320 | * into the clk API | |
0197b3ea SK |
321 | * |
322 | * @init: pointer to struct clk_init_data that contains the init data shared | |
0214f33c SB |
323 | * with the common clock framework. This pointer will be set to NULL once |
324 | * a clk_register() variant is called on this clk_hw pointer. | |
0197b3ea SK |
325 | */ |
326 | struct clk_hw { | |
035a61c3 | 327 | struct clk_core *core; |
0197b3ea | 328 | struct clk *clk; |
dc4cd941 | 329 | const struct clk_init_data *init; |
0197b3ea SK |
330 | }; |
331 | ||
9d9f78ed MT |
332 | /* |
333 | * DOC: Basic clock implementations common to many platforms | |
334 | * | |
335 | * Each basic clock hardware type is comprised of a structure describing the | |
336 | * clock hardware, implementations of the relevant callbacks in struct clk_ops, | |
337 | * unique flags for that hardware type, a registration function and an | |
338 | * alternative macro for static initialization | |
339 | */ | |
340 | ||
341 | /** | |
342 | * struct clk_fixed_rate - fixed-rate clock | |
343 | * @hw: handle between common and hardware-specific interfaces | |
344 | * @fixed_rate: constant frequency of clock | |
32205b75 | 345 | * @fixed_accuracy: constant accuracy of clock in ppb (parts per billion) |
2d34f09e | 346 | * @flags: hardware specific flags |
58f0c4ba SB |
347 | * |
348 | * Flags: | |
349 | * * CLK_FIXED_RATE_PARENT_ACCURACY - Use the accuracy of the parent clk | |
350 | * instead of what's set in @fixed_accuracy. | |
9d9f78ed MT |
351 | */ |
352 | struct clk_fixed_rate { | |
353 | struct clk_hw hw; | |
354 | unsigned long fixed_rate; | |
0903ea60 | 355 | unsigned long fixed_accuracy; |
2d34f09e | 356 | unsigned long flags; |
9d9f78ed MT |
357 | }; |
358 | ||
edfa3784 | 359 | #define CLK_FIXED_RATE_PARENT_ACCURACY BIT(0) |
5fd9c05c | 360 | |
bffad66e | 361 | extern const struct clk_ops clk_fixed_rate_ops; |
2d34f09e SB |
362 | struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev, |
363 | struct device_node *np, const char *name, | |
364 | const char *parent_name, const struct clk_hw *parent_hw, | |
365 | const struct clk_parent_data *parent_data, unsigned long flags, | |
366 | unsigned long fixed_rate, unsigned long fixed_accuracy, | |
1d7d2065 | 367 | unsigned long clk_fixed_flags, bool devm); |
9d9f78ed MT |
368 | struct clk *clk_register_fixed_rate(struct device *dev, const char *name, |
369 | const char *parent_name, unsigned long flags, | |
370 | unsigned long fixed_rate); | |
2d34f09e SB |
371 | /** |
372 | * clk_hw_register_fixed_rate - register fixed-rate clock with the clock | |
373 | * framework | |
374 | * @dev: device that is registering this clock | |
375 | * @name: name of this clock | |
376 | * @parent_name: name of clock's parent | |
377 | * @flags: framework-specific flags | |
378 | * @fixed_rate: non-adjustable clock rate | |
379 | */ | |
380 | #define clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate) \ | |
381 | __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \ | |
1d7d2065 DB |
382 | NULL, (flags), (fixed_rate), 0, 0, false) |
383 | ||
384 | /** | |
385 | * devm_clk_hw_register_fixed_rate - register fixed-rate clock with the clock | |
386 | * framework | |
387 | * @dev: device that is registering this clock | |
388 | * @name: name of this clock | |
389 | * @parent_name: name of clock's parent | |
390 | * @flags: framework-specific flags | |
391 | * @fixed_rate: non-adjustable clock rate | |
392 | */ | |
393 | #define devm_clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate) \ | |
394 | __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \ | |
395 | NULL, (flags), (fixed_rate), 0, 0, true) | |
2d34f09e SB |
396 | /** |
397 | * clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with | |
398 | * the clock framework | |
399 | * @dev: device that is registering this clock | |
400 | * @name: name of this clock | |
401 | * @parent_hw: pointer to parent clk | |
402 | * @flags: framework-specific flags | |
403 | * @fixed_rate: non-adjustable clock rate | |
404 | */ | |
405 | #define clk_hw_register_fixed_rate_parent_hw(dev, name, parent_hw, flags, \ | |
406 | fixed_rate) \ | |
407 | __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw), \ | |
1d7d2065 | 408 | NULL, (flags), (fixed_rate), 0, 0, false) |
2d34f09e SB |
409 | /** |
410 | * clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with | |
411 | * the clock framework | |
412 | * @dev: device that is registering this clock | |
413 | * @name: name of this clock | |
414 | * @parent_data: parent clk data | |
415 | * @flags: framework-specific flags | |
416 | * @fixed_rate: non-adjustable clock rate | |
417 | */ | |
418 | #define clk_hw_register_fixed_rate_parent_data(dev, name, parent_hw, flags, \ | |
419 | fixed_rate) \ | |
420 | __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \ | |
421 | (parent_data), (flags), (fixed_rate), 0, \ | |
1d7d2065 | 422 | 0, false) |
2d34f09e SB |
423 | /** |
424 | * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with | |
425 | * the clock framework | |
426 | * @dev: device that is registering this clock | |
427 | * @name: name of this clock | |
428 | * @parent_name: name of clock's parent | |
429 | * @flags: framework-specific flags | |
430 | * @fixed_rate: non-adjustable clock rate | |
1f1bb96d | 431 | * @fixed_accuracy: non-adjustable clock accuracy |
2d34f09e SB |
432 | */ |
433 | #define clk_hw_register_fixed_rate_with_accuracy(dev, name, parent_name, \ | |
434 | flags, fixed_rate, \ | |
435 | fixed_accuracy) \ | |
436 | __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), \ | |
437 | NULL, NULL, (flags), (fixed_rate), \ | |
1d7d2065 | 438 | (fixed_accuracy), 0, false) |
2d34f09e SB |
439 | /** |
440 | * clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate | |
441 | * clock with the clock framework | |
442 | * @dev: device that is registering this clock | |
443 | * @name: name of this clock | |
444 | * @parent_hw: pointer to parent clk | |
445 | * @flags: framework-specific flags | |
446 | * @fixed_rate: non-adjustable clock rate | |
447 | * @fixed_accuracy: non-adjustable clock accuracy | |
448 | */ | |
449 | #define clk_hw_register_fixed_rate_with_accuracy_parent_hw(dev, name, \ | |
450 | parent_hw, flags, fixed_rate, fixed_accuracy) \ | |
451 | __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw) \ | |
452 | NULL, NULL, (flags), (fixed_rate), \ | |
1d7d2065 | 453 | (fixed_accuracy), 0, false) |
2d34f09e SB |
454 | /** |
455 | * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate | |
456 | * clock with the clock framework | |
457 | * @dev: device that is registering this clock | |
458 | * @name: name of this clock | |
459 | * @parent_name: name of clock's parent | |
460 | * @flags: framework-specific flags | |
461 | * @fixed_rate: non-adjustable clock rate | |
462 | * @fixed_accuracy: non-adjustable clock accuracy | |
463 | */ | |
464 | #define clk_hw_register_fixed_rate_with_accuracy_parent_data(dev, name, \ | |
465 | parent_data, flags, fixed_rate, fixed_accuracy) \ | |
466 | __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \ | |
467 | (parent_data), NULL, (flags), \ | |
1d7d2065 | 468 | (fixed_rate), (fixed_accuracy), 0, false) |
f5290d8e DB |
469 | /** |
470 | * clk_hw_register_fixed_rate_parent_accuracy - register fixed-rate clock with | |
471 | * the clock framework | |
472 | * @dev: device that is registering this clock | |
473 | * @name: name of this clock | |
474 | * @parent_name: name of clock's parent | |
475 | * @flags: framework-specific flags | |
476 | * @fixed_rate: non-adjustable clock rate | |
477 | */ | |
478 | #define clk_hw_register_fixed_rate_parent_accuracy(dev, name, parent_data, \ | |
479 | flags, fixed_rate) \ | |
480 | __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \ | |
481 | (parent_data), (flags), (fixed_rate), 0, \ | |
1d7d2065 | 482 | CLK_FIXED_RATE_PARENT_ACCURACY, false) |
2d34f09e | 483 | |
0b225e41 | 484 | void clk_unregister_fixed_rate(struct clk *clk); |
52445637 | 485 | void clk_hw_unregister_fixed_rate(struct clk_hw *hw); |
26ef56be | 486 | |
015ba402 GL |
487 | void of_fixed_clk_setup(struct device_node *np); |
488 | ||
9d9f78ed MT |
489 | /** |
490 | * struct clk_gate - gating clock | |
491 | * | |
492 | * @hw: handle between common and hardware-specific interfaces | |
493 | * @reg: register controlling gate | |
494 | * @bit_idx: single bit controlling gate | |
495 | * @flags: hardware-specific flags | |
496 | * @lock: register lock | |
497 | * | |
498 | * Clock which can gate its output. Implements .enable & .disable | |
499 | * | |
500 | * Flags: | |
1f73f31a | 501 | * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to |
725b418b GU |
502 | * enable the clock. Setting this flag does the opposite: setting the bit |
503 | * disable the clock and clearing it enables the clock | |
04577994 | 504 | * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit |
725b418b GU |
505 | * of this register, and mask of gate bits are in higher 16-bit of this |
506 | * register. While setting the gate bits, higher 16-bit should also be | |
507 | * updated to indicate changing gate bits. | |
d1c8a501 JG |
508 | * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for |
509 | * the gate register. Setting this flag makes the register accesses big | |
510 | * endian. | |
9d9f78ed MT |
511 | */ |
512 | struct clk_gate { | |
513 | struct clk_hw hw; | |
514 | void __iomem *reg; | |
515 | u8 bit_idx; | |
516 | u8 flags; | |
517 | spinlock_t *lock; | |
9d9f78ed MT |
518 | }; |
519 | ||
5fd9c05c GT |
520 | #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw) |
521 | ||
9d9f78ed | 522 | #define CLK_GATE_SET_TO_DISABLE BIT(0) |
04577994 | 523 | #define CLK_GATE_HIWORD_MASK BIT(1) |
d1c8a501 | 524 | #define CLK_GATE_BIG_ENDIAN BIT(2) |
9d9f78ed | 525 | |
bffad66e | 526 | extern const struct clk_ops clk_gate_ops; |
194efb6e SB |
527 | struct clk_hw *__clk_hw_register_gate(struct device *dev, |
528 | struct device_node *np, const char *name, | |
529 | const char *parent_name, const struct clk_hw *parent_hw, | |
530 | const struct clk_parent_data *parent_data, | |
531 | unsigned long flags, | |
9d9f78ed MT |
532 | void __iomem *reg, u8 bit_idx, |
533 | u8 clk_gate_flags, spinlock_t *lock); | |
815f0e73 HV |
534 | struct clk_hw *__devm_clk_hw_register_gate(struct device *dev, |
535 | struct device_node *np, const char *name, | |
536 | const char *parent_name, const struct clk_hw *parent_hw, | |
537 | const struct clk_parent_data *parent_data, | |
538 | unsigned long flags, | |
539 | void __iomem *reg, u8 bit_idx, | |
540 | u8 clk_gate_flags, spinlock_t *lock); | |
194efb6e | 541 | struct clk *clk_register_gate(struct device *dev, const char *name, |
e270d8cb SB |
542 | const char *parent_name, unsigned long flags, |
543 | void __iomem *reg, u8 bit_idx, | |
544 | u8 clk_gate_flags, spinlock_t *lock); | |
194efb6e SB |
545 | /** |
546 | * clk_hw_register_gate - register a gate clock with the clock framework | |
547 | * @dev: device that is registering this clock | |
548 | * @name: name of this clock | |
549 | * @parent_name: name of this clock's parent | |
550 | * @flags: framework-specific flags for this clock | |
551 | * @reg: register address to control gating of this clock | |
552 | * @bit_idx: which bit in the register controls gating of this clock | |
553 | * @clk_gate_flags: gate-specific flags for this clock | |
554 | * @lock: shared register lock for this clock | |
555 | */ | |
556 | #define clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx, \ | |
557 | clk_gate_flags, lock) \ | |
558 | __clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \ | |
559 | NULL, (flags), (reg), (bit_idx), \ | |
560 | (clk_gate_flags), (lock)) | |
561 | /** | |
562 | * clk_hw_register_gate_parent_hw - register a gate clock with the clock | |
563 | * framework | |
564 | * @dev: device that is registering this clock | |
565 | * @name: name of this clock | |
566 | * @parent_hw: pointer to parent clk | |
567 | * @flags: framework-specific flags for this clock | |
568 | * @reg: register address to control gating of this clock | |
569 | * @bit_idx: which bit in the register controls gating of this clock | |
570 | * @clk_gate_flags: gate-specific flags for this clock | |
571 | * @lock: shared register lock for this clock | |
572 | */ | |
4e934301 | 573 | #define clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, reg, \ |
194efb6e | 574 | bit_idx, clk_gate_flags, lock) \ |
4e934301 | 575 | __clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw), \ |
194efb6e SB |
576 | NULL, (flags), (reg), (bit_idx), \ |
577 | (clk_gate_flags), (lock)) | |
578 | /** | |
579 | * clk_hw_register_gate_parent_data - register a gate clock with the clock | |
580 | * framework | |
581 | * @dev: device that is registering this clock | |
582 | * @name: name of this clock | |
583 | * @parent_data: parent clk data | |
584 | * @flags: framework-specific flags for this clock | |
585 | * @reg: register address to control gating of this clock | |
586 | * @bit_idx: which bit in the register controls gating of this clock | |
587 | * @clk_gate_flags: gate-specific flags for this clock | |
588 | * @lock: shared register lock for this clock | |
589 | */ | |
4e934301 | 590 | #define clk_hw_register_gate_parent_data(dev, name, parent_data, flags, reg, \ |
194efb6e | 591 | bit_idx, clk_gate_flags, lock) \ |
4e934301 SB |
592 | __clk_hw_register_gate((dev), NULL, (name), NULL, NULL, (parent_data), \ |
593 | (flags), (reg), (bit_idx), \ | |
194efb6e | 594 | (clk_gate_flags), (lock)) |
815f0e73 HV |
595 | /** |
596 | * devm_clk_hw_register_gate - register a gate clock with the clock framework | |
597 | * @dev: device that is registering this clock | |
598 | * @name: name of this clock | |
599 | * @parent_name: name of this clock's parent | |
600 | * @flags: framework-specific flags for this clock | |
601 | * @reg: register address to control gating of this clock | |
602 | * @bit_idx: which bit in the register controls gating of this clock | |
603 | * @clk_gate_flags: gate-specific flags for this clock | |
604 | * @lock: shared register lock for this clock | |
605 | */ | |
606 | #define devm_clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx,\ | |
607 | clk_gate_flags, lock) \ | |
608 | __devm_clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \ | |
609 | NULL, (flags), (reg), (bit_idx), \ | |
610 | (clk_gate_flags), (lock)) | |
d54c1fd4 QJ |
611 | /** |
612 | * devm_clk_hw_register_gate_parent_data - register a gate clock with the | |
613 | * clock framework | |
614 | * @dev: device that is registering this clock | |
615 | * @name: name of this clock | |
616 | * @parent_data: parent clk data | |
617 | * @flags: framework-specific flags for this clock | |
618 | * @reg: register address to control gating of this clock | |
619 | * @bit_idx: which bit in the register controls gating of this clock | |
620 | * @clk_gate_flags: gate-specific flags for this clock | |
621 | * @lock: shared register lock for this clock | |
622 | */ | |
623 | #define devm_clk_hw_register_gate_parent_data(dev, name, parent_data, flags, \ | |
624 | reg, bit_idx, clk_gate_flags, \ | |
27fc5ec6 | 625 | lock) \ |
d54c1fd4 QJ |
626 | __devm_clk_hw_register_gate((dev), NULL, (name), NULL, NULL, \ |
627 | (parent_data), (flags), (reg), (bit_idx), \ | |
628 | (clk_gate_flags), (lock)) | |
629 | ||
4e3c021f | 630 | void clk_unregister_gate(struct clk *clk); |
e270d8cb | 631 | void clk_hw_unregister_gate(struct clk_hw *hw); |
0a9c869d | 632 | int clk_gate_is_enabled(struct clk_hw *hw); |
9d9f78ed | 633 | |
357c3f0a RN |
634 | struct clk_div_table { |
635 | unsigned int val; | |
636 | unsigned int div; | |
637 | }; | |
638 | ||
9d9f78ed MT |
639 | /** |
640 | * struct clk_divider - adjustable divider clock | |
641 | * | |
642 | * @hw: handle between common and hardware-specific interfaces | |
643 | * @reg: register containing the divider | |
644 | * @shift: shift to the divider bit field | |
645 | * @width: width of the divider bit field | |
357c3f0a | 646 | * @table: array of value/divider pairs, last entry should have div = 0 |
9d9f78ed MT |
647 | * @lock: register lock |
648 | * | |
649 | * Clock with an adjustable divider affecting its output frequency. Implements | |
650 | * .recalc_rate, .set_rate and .round_rate | |
651 | * | |
652 | * Flags: | |
653 | * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the | |
725b418b GU |
654 | * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is |
655 | * the raw value read from the register, with the value of zero considered | |
056b2053 | 656 | * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set. |
9d9f78ed | 657 | * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from |
725b418b | 658 | * the hardware register |
056b2053 SB |
659 | * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have |
660 | * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor. | |
661 | * Some hardware implementations gracefully handle this case and allow a | |
662 | * zero divisor by not modifying their input clock | |
663 | * (divide by one / bypass). | |
d57dfe75 | 664 | * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit |
725b418b GU |
665 | * of this register, and mask of divider bits are in higher 16-bit of this |
666 | * register. While setting the divider bits, higher 16-bit should also be | |
667 | * updated to indicate changing divider bits. | |
774b5143 MC |
668 | * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded |
669 | * to the closest integer instead of the up one. | |
79c6ab50 HS |
670 | * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should |
671 | * not be changed by the clock framework. | |
afe76c8f JQ |
672 | * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED |
673 | * except when the value read from the register is zero, the divisor is | |
674 | * 2^width of the field. | |
434d69fa JG |
675 | * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used |
676 | * for the divider register. Setting this flag makes the register accesses | |
677 | * big endian. | |
9d9f78ed MT |
678 | */ |
679 | struct clk_divider { | |
680 | struct clk_hw hw; | |
681 | void __iomem *reg; | |
682 | u8 shift; | |
683 | u8 width; | |
684 | u8 flags; | |
357c3f0a | 685 | const struct clk_div_table *table; |
9d9f78ed | 686 | spinlock_t *lock; |
9d9f78ed MT |
687 | }; |
688 | ||
e6d3cc7b | 689 | #define clk_div_mask(width) ((1 << (width)) - 1) |
5fd9c05c GT |
690 | #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) |
691 | ||
9d9f78ed MT |
692 | #define CLK_DIVIDER_ONE_BASED BIT(0) |
693 | #define CLK_DIVIDER_POWER_OF_TWO BIT(1) | |
056b2053 | 694 | #define CLK_DIVIDER_ALLOW_ZERO BIT(2) |
d57dfe75 | 695 | #define CLK_DIVIDER_HIWORD_MASK BIT(3) |
774b5143 | 696 | #define CLK_DIVIDER_ROUND_CLOSEST BIT(4) |
79c6ab50 | 697 | #define CLK_DIVIDER_READ_ONLY BIT(5) |
afe76c8f | 698 | #define CLK_DIVIDER_MAX_AT_ZERO BIT(6) |
434d69fa | 699 | #define CLK_DIVIDER_BIG_ENDIAN BIT(7) |
9d9f78ed | 700 | |
bffad66e | 701 | extern const struct clk_ops clk_divider_ops; |
50359819 | 702 | extern const struct clk_ops clk_divider_ro_ops; |
bca9690b SB |
703 | |
704 | unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate, | |
705 | unsigned int val, const struct clk_div_table *table, | |
12a26c29 | 706 | unsigned long flags, unsigned long width); |
22833a91 MR |
707 | long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, |
708 | unsigned long rate, unsigned long *prate, | |
709 | const struct clk_div_table *table, | |
710 | u8 width, unsigned long flags); | |
b15ee490 JB |
711 | long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, |
712 | unsigned long rate, unsigned long *prate, | |
713 | const struct clk_div_table *table, u8 width, | |
714 | unsigned long flags, unsigned int val); | |
bbd7a6cc MB |
715 | int divider_determine_rate(struct clk_hw *hw, struct clk_rate_request *req, |
716 | const struct clk_div_table *table, u8 width, | |
717 | unsigned long flags); | |
718 | int divider_ro_determine_rate(struct clk_hw *hw, struct clk_rate_request *req, | |
719 | const struct clk_div_table *table, u8 width, | |
720 | unsigned long flags, unsigned int val); | |
bca9690b SB |
721 | int divider_get_val(unsigned long rate, unsigned long parent_rate, |
722 | const struct clk_div_table *table, u8 width, | |
723 | unsigned long flags); | |
724 | ||
ff258817 SB |
725 | struct clk_hw *__clk_hw_register_divider(struct device *dev, |
726 | struct device_node *np, const char *name, | |
727 | const char *parent_name, const struct clk_hw *parent_hw, | |
728 | const struct clk_parent_data *parent_data, unsigned long flags, | |
729 | void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, | |
730 | const struct clk_div_table *table, spinlock_t *lock); | |
26792699 MW |
731 | struct clk_hw *__devm_clk_hw_register_divider(struct device *dev, |
732 | struct device_node *np, const char *name, | |
733 | const char *parent_name, const struct clk_hw *parent_hw, | |
734 | const struct clk_parent_data *parent_data, unsigned long flags, | |
735 | void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, | |
736 | const struct clk_div_table *table, spinlock_t *lock); | |
357c3f0a RN |
737 | struct clk *clk_register_divider_table(struct device *dev, const char *name, |
738 | const char *parent_name, unsigned long flags, | |
739 | void __iomem *reg, u8 shift, u8 width, | |
740 | u8 clk_divider_flags, const struct clk_div_table *table, | |
741 | spinlock_t *lock); | |
ff258817 SB |
742 | /** |
743 | * clk_register_divider - register a divider clock with the clock framework | |
744 | * @dev: device registering this clock | |
745 | * @name: name of this clock | |
746 | * @parent_name: name of clock's parent | |
747 | * @flags: framework-specific flags | |
748 | * @reg: register address to adjust divider | |
749 | * @shift: number of bits to shift the bitfield | |
750 | * @width: width of the bitfield | |
751 | * @clk_divider_flags: divider-specific flags for this clock | |
752 | * @lock: shared register lock for this clock | |
753 | */ | |
754 | #define clk_register_divider(dev, name, parent_name, flags, reg, shift, width, \ | |
755 | clk_divider_flags, lock) \ | |
756 | clk_register_divider_table((dev), (name), (parent_name), (flags), \ | |
757 | (reg), (shift), (width), \ | |
758 | (clk_divider_flags), NULL, (lock)) | |
759 | /** | |
760 | * clk_hw_register_divider - register a divider clock with the clock framework | |
761 | * @dev: device registering this clock | |
762 | * @name: name of this clock | |
763 | * @parent_name: name of clock's parent | |
764 | * @flags: framework-specific flags | |
765 | * @reg: register address to adjust divider | |
766 | * @shift: number of bits to shift the bitfield | |
767 | * @width: width of the bitfield | |
768 | * @clk_divider_flags: divider-specific flags for this clock | |
769 | * @lock: shared register lock for this clock | |
770 | */ | |
771 | #define clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \ | |
772 | width, clk_divider_flags, lock) \ | |
773 | __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \ | |
774 | NULL, (flags), (reg), (shift), (width), \ | |
775 | (clk_divider_flags), NULL, (lock)) | |
776 | /** | |
777 | * clk_hw_register_divider_parent_hw - register a divider clock with the clock | |
778 | * framework | |
779 | * @dev: device registering this clock | |
780 | * @name: name of this clock | |
781 | * @parent_hw: pointer to parent clk | |
782 | * @flags: framework-specific flags | |
783 | * @reg: register address to adjust divider | |
784 | * @shift: number of bits to shift the bitfield | |
785 | * @width: width of the bitfield | |
786 | * @clk_divider_flags: divider-specific flags for this clock | |
787 | * @lock: shared register lock for this clock | |
788 | */ | |
789 | #define clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, reg, \ | |
790 | shift, width, clk_divider_flags, \ | |
791 | lock) \ | |
792 | __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \ | |
793 | NULL, (flags), (reg), (shift), (width), \ | |
794 | (clk_divider_flags), NULL, (lock)) | |
795 | /** | |
796 | * clk_hw_register_divider_parent_data - register a divider clock with the clock | |
797 | * framework | |
798 | * @dev: device registering this clock | |
799 | * @name: name of this clock | |
800 | * @parent_data: parent clk data | |
801 | * @flags: framework-specific flags | |
802 | * @reg: register address to adjust divider | |
803 | * @shift: number of bits to shift the bitfield | |
804 | * @width: width of the bitfield | |
805 | * @clk_divider_flags: divider-specific flags for this clock | |
806 | * @lock: shared register lock for this clock | |
807 | */ | |
808 | #define clk_hw_register_divider_parent_data(dev, name, parent_data, flags, \ | |
809 | reg, shift, width, \ | |
810 | clk_divider_flags, lock) \ | |
811 | __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \ | |
812 | (parent_data), (flags), (reg), (shift), \ | |
813 | (width), (clk_divider_flags), NULL, (lock)) | |
814 | /** | |
815 | * clk_hw_register_divider_table - register a table based divider clock with | |
816 | * the clock framework | |
817 | * @dev: device registering this clock | |
818 | * @name: name of this clock | |
819 | * @parent_name: name of clock's parent | |
820 | * @flags: framework-specific flags | |
821 | * @reg: register address to adjust divider | |
822 | * @shift: number of bits to shift the bitfield | |
823 | * @width: width of the bitfield | |
824 | * @clk_divider_flags: divider-specific flags for this clock | |
825 | * @table: array of divider/value pairs ending with a div set to 0 | |
826 | * @lock: shared register lock for this clock | |
827 | */ | |
828 | #define clk_hw_register_divider_table(dev, name, parent_name, flags, reg, \ | |
829 | shift, width, clk_divider_flags, table, \ | |
830 | lock) \ | |
831 | __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \ | |
832 | NULL, (flags), (reg), (shift), (width), \ | |
833 | (clk_divider_flags), (table), (lock)) | |
834 | /** | |
835 | * clk_hw_register_divider_table_parent_hw - register a table based divider | |
836 | * clock with the clock framework | |
837 | * @dev: device registering this clock | |
838 | * @name: name of this clock | |
839 | * @parent_hw: pointer to parent clk | |
840 | * @flags: framework-specific flags | |
841 | * @reg: register address to adjust divider | |
842 | * @shift: number of bits to shift the bitfield | |
843 | * @width: width of the bitfield | |
844 | * @clk_divider_flags: divider-specific flags for this clock | |
845 | * @table: array of divider/value pairs ending with a div set to 0 | |
846 | * @lock: shared register lock for this clock | |
847 | */ | |
848 | #define clk_hw_register_divider_table_parent_hw(dev, name, parent_hw, flags, \ | |
849 | reg, shift, width, \ | |
850 | clk_divider_flags, table, \ | |
851 | lock) \ | |
852 | __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \ | |
853 | NULL, (flags), (reg), (shift), (width), \ | |
854 | (clk_divider_flags), (table), (lock)) | |
855 | /** | |
856 | * clk_hw_register_divider_table_parent_data - register a table based divider | |
857 | * clock with the clock framework | |
858 | * @dev: device registering this clock | |
859 | * @name: name of this clock | |
860 | * @parent_data: parent clk data | |
861 | * @flags: framework-specific flags | |
862 | * @reg: register address to adjust divider | |
863 | * @shift: number of bits to shift the bitfield | |
864 | * @width: width of the bitfield | |
865 | * @clk_divider_flags: divider-specific flags for this clock | |
866 | * @table: array of divider/value pairs ending with a div set to 0 | |
867 | * @lock: shared register lock for this clock | |
868 | */ | |
869 | #define clk_hw_register_divider_table_parent_data(dev, name, parent_data, \ | |
870 | flags, reg, shift, width, \ | |
871 | clk_divider_flags, table, \ | |
872 | lock) \ | |
873 | __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \ | |
874 | (parent_data), (flags), (reg), (shift), \ | |
875 | (width), (clk_divider_flags), (table), \ | |
876 | (lock)) | |
f4b43ac0 DB |
877 | /** |
878 | * devm_clk_hw_register_divider - register a divider clock with the clock framework | |
879 | * @dev: device registering this clock | |
880 | * @name: name of this clock | |
881 | * @parent_name: name of clock's parent | |
882 | * @flags: framework-specific flags | |
883 | * @reg: register address to adjust divider | |
884 | * @shift: number of bits to shift the bitfield | |
885 | * @width: width of the bitfield | |
886 | * @clk_divider_flags: divider-specific flags for this clock | |
887 | * @lock: shared register lock for this clock | |
888 | */ | |
889 | #define devm_clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \ | |
890 | width, clk_divider_flags, lock) \ | |
891 | __devm_clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \ | |
892 | NULL, (flags), (reg), (shift), (width), \ | |
893 | (clk_divider_flags), NULL, (lock)) | |
909fcb19 MS |
894 | /** |
895 | * devm_clk_hw_register_divider_parent_hw - register a divider clock with the clock framework | |
896 | * @dev: device registering this clock | |
897 | * @name: name of this clock | |
898 | * @parent_hw: pointer to parent clk | |
899 | * @flags: framework-specific flags | |
900 | * @reg: register address to adjust divider | |
901 | * @shift: number of bits to shift the bitfield | |
902 | * @width: width of the bitfield | |
903 | * @clk_divider_flags: divider-specific flags for this clock | |
904 | * @lock: shared register lock for this clock | |
905 | */ | |
906 | #define devm_clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, \ | |
907 | reg, shift, width, \ | |
908 | clk_divider_flags, lock) \ | |
909 | __devm_clk_hw_register_divider((dev), NULL, (name), NULL, \ | |
910 | (parent_hw), NULL, (flags), (reg), \ | |
911 | (shift), (width), (clk_divider_flags), \ | |
912 | NULL, (lock)) | |
26792699 MW |
913 | /** |
914 | * devm_clk_hw_register_divider_table - register a table based divider clock | |
915 | * with the clock framework (devres variant) | |
916 | * @dev: device registering this clock | |
917 | * @name: name of this clock | |
918 | * @parent_name: name of clock's parent | |
919 | * @flags: framework-specific flags | |
920 | * @reg: register address to adjust divider | |
921 | * @shift: number of bits to shift the bitfield | |
922 | * @width: width of the bitfield | |
923 | * @clk_divider_flags: divider-specific flags for this clock | |
924 | * @table: array of divider/value pairs ending with a div set to 0 | |
925 | * @lock: shared register lock for this clock | |
926 | */ | |
927 | #define devm_clk_hw_register_divider_table(dev, name, parent_name, flags, \ | |
928 | reg, shift, width, \ | |
929 | clk_divider_flags, table, lock) \ | |
930 | __devm_clk_hw_register_divider((dev), NULL, (name), (parent_name), \ | |
931 | NULL, NULL, (flags), (reg), (shift), \ | |
932 | (width), (clk_divider_flags), (table), \ | |
933 | (lock)) | |
ff258817 | 934 | |
4e3c021f | 935 | void clk_unregister_divider(struct clk *clk); |
eb7d264f | 936 | void clk_hw_unregister_divider(struct clk_hw *hw); |
9d9f78ed MT |
937 | |
938 | /** | |
939 | * struct clk_mux - multiplexer clock | |
940 | * | |
941 | * @hw: handle between common and hardware-specific interfaces | |
942 | * @reg: register controlling multiplexer | |
fe3f338f | 943 | * @table: array of register values corresponding to the parent index |
9d9f78ed | 944 | * @shift: shift to multiplexer bit field |
fe3f338f | 945 | * @mask: mask of mutliplexer bit field |
3566d40c | 946 | * @flags: hardware-specific flags |
9d9f78ed MT |
947 | * @lock: register lock |
948 | * | |
949 | * Clock with multiple selectable parents. Implements .get_parent, .set_parent | |
950 | * and .recalc_rate | |
951 | * | |
952 | * Flags: | |
953 | * CLK_MUX_INDEX_ONE - register index starts at 1, not 0 | |
1f73f31a | 954 | * CLK_MUX_INDEX_BIT - register index is a single bit (power of two) |
ba492e90 | 955 | * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this |
725b418b GU |
956 | * register, and mask of mux bits are in higher 16-bit of this register. |
957 | * While setting the mux bits, higher 16-bit should also be updated to | |
958 | * indicate changing mux bits. | |
31f6e870 SB |
959 | * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the |
960 | * .get_parent clk_op. | |
15a02c1f SB |
961 | * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired |
962 | * frequency. | |
3a727519 JG |
963 | * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for |
964 | * the mux register. Setting this flag makes the register accesses big | |
965 | * endian. | |
9d9f78ed MT |
966 | */ |
967 | struct clk_mux { | |
968 | struct clk_hw hw; | |
969 | void __iomem *reg; | |
891b7023 | 970 | const u32 *table; |
ce4f3313 | 971 | u32 mask; |
9d9f78ed | 972 | u8 shift; |
9d9f78ed MT |
973 | u8 flags; |
974 | spinlock_t *lock; | |
975 | }; | |
976 | ||
5fd9c05c GT |
977 | #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw) |
978 | ||
9d9f78ed MT |
979 | #define CLK_MUX_INDEX_ONE BIT(0) |
980 | #define CLK_MUX_INDEX_BIT BIT(1) | |
ba492e90 | 981 | #define CLK_MUX_HIWORD_MASK BIT(2) |
15a02c1f SB |
982 | #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */ |
983 | #define CLK_MUX_ROUND_CLOSEST BIT(4) | |
3a727519 | 984 | #define CLK_MUX_BIG_ENDIAN BIT(5) |
9d9f78ed | 985 | |
bffad66e | 986 | extern const struct clk_ops clk_mux_ops; |
c57acd14 | 987 | extern const struct clk_ops clk_mux_ro_ops; |
ce4f3313 | 988 | |
9611b3aa SB |
989 | struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np, |
990 | const char *name, u8 num_parents, | |
991 | const char * const *parent_names, | |
992 | const struct clk_hw **parent_hws, | |
993 | const struct clk_parent_data *parent_data, | |
994 | unsigned long flags, void __iomem *reg, u8 shift, u32 mask, | |
891b7023 | 995 | u8 clk_mux_flags, const u32 *table, spinlock_t *lock); |
b3084079 DB |
996 | struct clk_hw *__devm_clk_hw_register_mux(struct device *dev, struct device_node *np, |
997 | const char *name, u8 num_parents, | |
998 | const char * const *parent_names, | |
999 | const struct clk_hw **parent_hws, | |
1000 | const struct clk_parent_data *parent_data, | |
1001 | unsigned long flags, void __iomem *reg, u8 shift, u32 mask, | |
891b7023 | 1002 | u8 clk_mux_flags, const u32 *table, spinlock_t *lock); |
9611b3aa | 1003 | struct clk *clk_register_mux_table(struct device *dev, const char *name, |
264b3171 | 1004 | const char * const *parent_names, u8 num_parents, |
9611b3aa | 1005 | unsigned long flags, void __iomem *reg, u8 shift, u32 mask, |
891b7023 | 1006 | u8 clk_mux_flags, const u32 *table, spinlock_t *lock); |
ce4f3313 | 1007 | |
9611b3aa SB |
1008 | #define clk_register_mux(dev, name, parent_names, num_parents, flags, reg, \ |
1009 | shift, width, clk_mux_flags, lock) \ | |
1010 | clk_register_mux_table((dev), (name), (parent_names), (num_parents), \ | |
1011 | (flags), (reg), (shift), BIT((width)) - 1, \ | |
1012 | (clk_mux_flags), NULL, (lock)) | |
1013 | #define clk_hw_register_mux_table(dev, name, parent_names, num_parents, \ | |
1014 | flags, reg, shift, mask, clk_mux_flags, \ | |
1015 | table, lock) \ | |
1016 | __clk_hw_register_mux((dev), NULL, (name), (num_parents), \ | |
1017 | (parent_names), NULL, NULL, (flags), (reg), \ | |
1018 | (shift), (mask), (clk_mux_flags), (table), \ | |
1019 | (lock)) | |
f5290d8e DB |
1020 | #define clk_hw_register_mux_table_parent_data(dev, name, parent_data, \ |
1021 | num_parents, flags, reg, shift, mask, \ | |
1022 | clk_mux_flags, table, lock) \ | |
1023 | __clk_hw_register_mux((dev), NULL, (name), (num_parents), \ | |
1024 | NULL, NULL, (parent_data), (flags), (reg), \ | |
1025 | (shift), (mask), (clk_mux_flags), (table), \ | |
1026 | (lock)) | |
9611b3aa SB |
1027 | #define clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \ |
1028 | shift, width, clk_mux_flags, lock) \ | |
1029 | __clk_hw_register_mux((dev), NULL, (name), (num_parents), \ | |
1030 | (parent_names), NULL, NULL, (flags), (reg), \ | |
1031 | (shift), BIT((width)) - 1, (clk_mux_flags), \ | |
1032 | NULL, (lock)) | |
1033 | #define clk_hw_register_mux_hws(dev, name, parent_hws, num_parents, flags, \ | |
1034 | reg, shift, width, clk_mux_flags, lock) \ | |
1035 | __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \ | |
1036 | (parent_hws), NULL, (flags), (reg), (shift), \ | |
1037 | BIT((width)) - 1, (clk_mux_flags), NULL, (lock)) | |
1038 | #define clk_hw_register_mux_parent_data(dev, name, parent_data, num_parents, \ | |
1039 | flags, reg, shift, width, \ | |
1040 | clk_mux_flags, lock) \ | |
1041 | __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \ | |
1042 | (parent_data), (flags), (reg), (shift), \ | |
1043 | BIT((width)) - 1, (clk_mux_flags), NULL, (lock)) | |
d7915651 CM |
1044 | #define clk_hw_register_mux_parent_data_table(dev, name, parent_data, \ |
1045 | num_parents, flags, reg, shift, \ | |
1046 | width, clk_mux_flags, table, \ | |
1047 | lock) \ | |
1048 | __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \ | |
1049 | (parent_data), (flags), (reg), (shift), \ | |
1050 | BIT((width)) - 1, (clk_mux_flags), table, (lock)) | |
b3084079 DB |
1051 | #define devm_clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \ |
1052 | shift, width, clk_mux_flags, lock) \ | |
1053 | __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), \ | |
1054 | (parent_names), NULL, NULL, (flags), (reg), \ | |
1055 | (shift), BIT((width)) - 1, (clk_mux_flags), \ | |
1056 | NULL, (lock)) | |
df63af17 MS |
1057 | #define devm_clk_hw_register_mux_parent_hws(dev, name, parent_hws, \ |
1058 | num_parents, flags, reg, shift, \ | |
1059 | width, clk_mux_flags, lock) \ | |
1060 | __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \ | |
1061 | (parent_hws), NULL, (flags), (reg), \ | |
1062 | (shift), BIT((width)) - 1, \ | |
1063 | (clk_mux_flags), NULL, (lock)) | |
d7915651 CM |
1064 | #define devm_clk_hw_register_mux_parent_data_table(dev, name, parent_data, \ |
1065 | num_parents, flags, reg, shift, \ | |
1066 | width, clk_mux_flags, table, \ | |
1067 | lock) \ | |
1068 | __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \ | |
1069 | NULL, (parent_data), (flags), (reg), (shift), \ | |
1070 | BIT((width)) - 1, (clk_mux_flags), table, (lock)) | |
9611b3aa | 1071 | |
891b7023 | 1072 | int clk_mux_val_to_index(struct clk_hw *hw, const u32 *table, unsigned int flags, |
77deb66d | 1073 | unsigned int val); |
891b7023 | 1074 | unsigned int clk_mux_index_to_val(const u32 *table, unsigned int flags, u8 index); |
77deb66d | 1075 | |
4e3c021f | 1076 | void clk_unregister_mux(struct clk *clk); |
264b3171 | 1077 | void clk_hw_unregister_mux(struct clk_hw *hw); |
4e3c021f | 1078 | |
79b16641 GC |
1079 | void of_fixed_factor_clk_setup(struct device_node *node); |
1080 | ||
f0948f59 SH |
1081 | /** |
1082 | * struct clk_fixed_factor - fixed multiplier and divider clock | |
1083 | * | |
1084 | * @hw: handle between common and hardware-specific interfaces | |
1085 | * @mult: multiplier | |
1086 | * @div: divider | |
1087 | * | |
1088 | * Clock with a fixed multiplier and divider. The output frequency is the | |
1089 | * parent clock rate divided by div and multiplied by mult. | |
1090 | * Implements .recalc_rate, .set_rate and .round_rate | |
1091 | */ | |
1092 | ||
1093 | struct clk_fixed_factor { | |
1094 | struct clk_hw hw; | |
1095 | unsigned int mult; | |
1096 | unsigned int div; | |
1097 | }; | |
1098 | ||
5fd9c05c GT |
1099 | #define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw) |
1100 | ||
3037e9ea | 1101 | extern const struct clk_ops clk_fixed_factor_ops; |
f0948f59 SH |
1102 | struct clk *clk_register_fixed_factor(struct device *dev, const char *name, |
1103 | const char *parent_name, unsigned long flags, | |
1104 | unsigned int mult, unsigned int div); | |
cbf9591f | 1105 | void clk_unregister_fixed_factor(struct clk *clk); |
0759ac8a SB |
1106 | struct clk_hw *clk_hw_register_fixed_factor(struct device *dev, |
1107 | const char *name, const char *parent_name, unsigned long flags, | |
1108 | unsigned int mult, unsigned int div); | |
1109 | void clk_hw_unregister_fixed_factor(struct clk_hw *hw); | |
0b9266d2 DP |
1110 | struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev, |
1111 | const char *name, const char *parent_name, unsigned long flags, | |
1112 | unsigned int mult, unsigned int div); | |
0c125f87 MV |
1113 | struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev, |
1114 | const char *name, unsigned int index, unsigned long flags, | |
1115 | unsigned int mult, unsigned int div); | |
6ebd5247 MS |
1116 | |
1117 | struct clk_hw *devm_clk_hw_register_fixed_factor_parent_hw(struct device *dev, | |
1118 | const char *name, const struct clk_hw *parent_hw, | |
1119 | unsigned long flags, unsigned int mult, unsigned int div); | |
1120 | ||
1121 | struct clk_hw *clk_hw_register_fixed_factor_parent_hw(struct device *dev, | |
1122 | const char *name, const struct clk_hw *parent_hw, | |
1123 | unsigned long flags, unsigned int mult, unsigned int div); | |
e2d0e90f HK |
1124 | /** |
1125 | * struct clk_fractional_divider - adjustable fractional divider clock | |
1126 | * | |
1127 | * @hw: handle between common and hardware-specific interfaces | |
1128 | * @reg: register containing the divider | |
1129 | * @mshift: shift to the numerator bit field | |
1130 | * @mwidth: width of the numerator bit field | |
1131 | * @nshift: shift to the denominator bit field | |
1132 | * @nwidth: width of the denominator bit field | |
1133 | * @lock: register lock | |
1134 | * | |
1135 | * Clock with adjustable fractional divider affecting its output frequency. | |
e983da27 D |
1136 | * |
1137 | * Flags: | |
1138 | * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator | |
1139 | * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED | |
1140 | * is set then the numerator and denominator are both the value read | |
1141 | * plus one. | |
58a2b4c9 JG |
1142 | * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are |
1143 | * used for the divider register. Setting this flag makes the register | |
1144 | * accesses big endian. | |
82f53f9e AS |
1145 | * CLK_FRAC_DIVIDER_POWER_OF_TWO_PS - By default the resulting fraction might |
1146 | * be saturated and the caller will get quite far from the good enough | |
1147 | * approximation. Instead the caller may require, by setting this flag, | |
1148 | * to shift left by a few bits in case, when the asked one is quite small | |
1149 | * to satisfy the desired range of denominator. It assumes that on the | |
1150 | * caller's side the power-of-two capable prescaler exists. | |
e2d0e90f | 1151 | */ |
e2d0e90f HK |
1152 | struct clk_fractional_divider { |
1153 | struct clk_hw hw; | |
1154 | void __iomem *reg; | |
1155 | u8 mshift; | |
934e2536 | 1156 | u8 mwidth; |
e2d0e90f | 1157 | u8 nshift; |
934e2536 | 1158 | u8 nwidth; |
e2d0e90f | 1159 | u8 flags; |
ec52e462 EZ |
1160 | void (*approximation)(struct clk_hw *hw, |
1161 | unsigned long rate, unsigned long *parent_rate, | |
1162 | unsigned long *m, unsigned long *n); | |
e2d0e90f HK |
1163 | spinlock_t *lock; |
1164 | }; | |
1165 | ||
5fd9c05c GT |
1166 | #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw) |
1167 | ||
e983da27 | 1168 | #define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0) |
58a2b4c9 | 1169 | #define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1) |
82f53f9e | 1170 | #define CLK_FRAC_DIVIDER_POWER_OF_TWO_PS BIT(2) |
e983da27 | 1171 | |
e2d0e90f HK |
1172 | struct clk *clk_register_fractional_divider(struct device *dev, |
1173 | const char *name, const char *parent_name, unsigned long flags, | |
1174 | void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, | |
1175 | u8 clk_divider_flags, spinlock_t *lock); | |
39b44cff SB |
1176 | struct clk_hw *clk_hw_register_fractional_divider(struct device *dev, |
1177 | const char *name, const char *parent_name, unsigned long flags, | |
1178 | void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, | |
1179 | u8 clk_divider_flags, spinlock_t *lock); | |
1180 | void clk_hw_unregister_fractional_divider(struct clk_hw *hw); | |
e2d0e90f | 1181 | |
f2e0a532 MR |
1182 | /** |
1183 | * struct clk_multiplier - adjustable multiplier clock | |
1184 | * | |
1185 | * @hw: handle between common and hardware-specific interfaces | |
1186 | * @reg: register containing the multiplier | |
1187 | * @shift: shift to the multiplier bit field | |
1188 | * @width: width of the multiplier bit field | |
1189 | * @lock: register lock | |
1190 | * | |
1191 | * Clock with an adjustable multiplier affecting its output frequency. | |
1192 | * Implements .recalc_rate, .set_rate and .round_rate | |
1193 | * | |
1194 | * Flags: | |
1195 | * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read | |
1196 | * from the register, with 0 being a valid value effectively | |
1197 | * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is | |
1198 | * set, then a null multiplier will be considered as a bypass, | |
1199 | * leaving the parent rate unmodified. | |
1200 | * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be | |
1201 | * rounded to the closest integer instead of the down one. | |
9427b71a JG |
1202 | * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are |
1203 | * used for the multiplier register. Setting this flag makes the register | |
1204 | * accesses big endian. | |
f2e0a532 MR |
1205 | */ |
1206 | struct clk_multiplier { | |
1207 | struct clk_hw hw; | |
1208 | void __iomem *reg; | |
1209 | u8 shift; | |
1210 | u8 width; | |
1211 | u8 flags; | |
1212 | spinlock_t *lock; | |
1213 | }; | |
1214 | ||
5fd9c05c GT |
1215 | #define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw) |
1216 | ||
edfa3784 | 1217 | #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0) |
f2e0a532 | 1218 | #define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1) |
edfa3784 | 1219 | #define CLK_MULTIPLIER_BIG_ENDIAN BIT(2) |
f2e0a532 MR |
1220 | |
1221 | extern const struct clk_ops clk_multiplier_ops; | |
1222 | ||
ece70094 PG |
1223 | /*** |
1224 | * struct clk_composite - aggregate clock of mux, divider and gate clocks | |
1225 | * | |
1226 | * @hw: handle between common and hardware-specific interfaces | |
d3a1c7be MT |
1227 | * @mux_hw: handle between composite and hardware-specific mux clock |
1228 | * @rate_hw: handle between composite and hardware-specific rate clock | |
1229 | * @gate_hw: handle between composite and hardware-specific gate clock | |
ece70094 | 1230 | * @mux_ops: clock ops for mux |
d3a1c7be | 1231 | * @rate_ops: clock ops for rate |
ece70094 PG |
1232 | * @gate_ops: clock ops for gate |
1233 | */ | |
1234 | struct clk_composite { | |
1235 | struct clk_hw hw; | |
1236 | struct clk_ops ops; | |
1237 | ||
1238 | struct clk_hw *mux_hw; | |
d3a1c7be | 1239 | struct clk_hw *rate_hw; |
ece70094 PG |
1240 | struct clk_hw *gate_hw; |
1241 | ||
1242 | const struct clk_ops *mux_ops; | |
d3a1c7be | 1243 | const struct clk_ops *rate_ops; |
ece70094 PG |
1244 | const struct clk_ops *gate_ops; |
1245 | }; | |
1246 | ||
5fd9c05c GT |
1247 | #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw) |
1248 | ||
ece70094 | 1249 | struct clk *clk_register_composite(struct device *dev, const char *name, |
2893c379 | 1250 | const char * const *parent_names, int num_parents, |
ece70094 | 1251 | struct clk_hw *mux_hw, const struct clk_ops *mux_ops, |
d3a1c7be | 1252 | struct clk_hw *rate_hw, const struct clk_ops *rate_ops, |
ece70094 PG |
1253 | struct clk_hw *gate_hw, const struct clk_ops *gate_ops, |
1254 | unsigned long flags); | |
73ef6572 MW |
1255 | struct clk *clk_register_composite_pdata(struct device *dev, const char *name, |
1256 | const struct clk_parent_data *parent_data, int num_parents, | |
1257 | struct clk_hw *mux_hw, const struct clk_ops *mux_ops, | |
1258 | struct clk_hw *rate_hw, const struct clk_ops *rate_ops, | |
1259 | struct clk_hw *gate_hw, const struct clk_ops *gate_ops, | |
1260 | unsigned long flags); | |
92a39d90 | 1261 | void clk_unregister_composite(struct clk *clk); |
49cb392d SB |
1262 | struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name, |
1263 | const char * const *parent_names, int num_parents, | |
1264 | struct clk_hw *mux_hw, const struct clk_ops *mux_ops, | |
1265 | struct clk_hw *rate_hw, const struct clk_ops *rate_ops, | |
1266 | struct clk_hw *gate_hw, const struct clk_ops *gate_ops, | |
1267 | unsigned long flags); | |
73ef6572 MW |
1268 | struct clk_hw *clk_hw_register_composite_pdata(struct device *dev, |
1269 | const char *name, | |
1270 | const struct clk_parent_data *parent_data, int num_parents, | |
49cb392d SB |
1271 | struct clk_hw *mux_hw, const struct clk_ops *mux_ops, |
1272 | struct clk_hw *rate_hw, const struct clk_ops *rate_ops, | |
1273 | struct clk_hw *gate_hw, const struct clk_ops *gate_ops, | |
1274 | unsigned long flags); | |
0eba7707 MW |
1275 | struct clk_hw *devm_clk_hw_register_composite_pdata(struct device *dev, |
1276 | const char *name, const struct clk_parent_data *parent_data, | |
1277 | int num_parents, | |
1278 | struct clk_hw *mux_hw, const struct clk_ops *mux_ops, | |
1279 | struct clk_hw *rate_hw, const struct clk_ops *rate_ops, | |
49cb392d SB |
1280 | struct clk_hw *gate_hw, const struct clk_ops *gate_ops, |
1281 | unsigned long flags); | |
1282 | void clk_hw_unregister_composite(struct clk_hw *hw); | |
ece70094 | 1283 | |
0197b3ea | 1284 | struct clk *clk_register(struct device *dev, struct clk_hw *hw); |
46c8773a | 1285 | struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw); |
b2476490 | 1286 | |
4143804c SB |
1287 | int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw); |
1288 | int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw); | |
89a5ddcc | 1289 | int __must_check of_clk_hw_register(struct device_node *node, struct clk_hw *hw); |
4143804c | 1290 | |
1df5c939 MB |
1291 | void clk_unregister(struct clk *clk); |
1292 | ||
4143804c | 1293 | void clk_hw_unregister(struct clk_hw *hw); |
4143804c | 1294 | |
b2476490 | 1295 | /* helper functions */ |
b76281cb | 1296 | const char *__clk_get_name(const struct clk *clk); |
e7df6f6e | 1297 | const char *clk_hw_get_name(const struct clk_hw *hw); |
1df37992 | 1298 | #ifdef CONFIG_COMMON_CLK |
b2476490 | 1299 | struct clk_hw *__clk_get_hw(struct clk *clk); |
1df37992 SR |
1300 | #else |
1301 | static inline struct clk_hw *__clk_get_hw(struct clk *clk) | |
1302 | { | |
1303 | return (struct clk_hw *)clk; | |
1304 | } | |
1305 | #endif | |
30d6f8c1 JB |
1306 | |
1307 | struct clk *clk_hw_get_clk(struct clk_hw *hw, const char *con_id); | |
1308 | struct clk *devm_clk_hw_get_clk(struct device *dev, struct clk_hw *hw, | |
1309 | const char *con_id); | |
1310 | ||
e7df6f6e SB |
1311 | unsigned int clk_hw_get_num_parents(const struct clk_hw *hw); |
1312 | struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw); | |
1313 | struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw, | |
1a9c069c | 1314 | unsigned int index); |
d9b86cc4 | 1315 | int clk_hw_get_parent_index(struct clk_hw *hw); |
3567894b | 1316 | int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *new_parent); |
93874681 | 1317 | unsigned int __clk_get_enable_count(struct clk *clk); |
e7df6f6e | 1318 | unsigned long clk_hw_get_rate(const struct clk_hw *hw); |
e7df6f6e | 1319 | unsigned long clk_hw_get_flags(const struct clk_hw *hw); |
d13501a2 KS |
1320 | #define clk_hw_can_set_rate_parent(hw) \ |
1321 | (clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT) | |
1322 | ||
e7df6f6e | 1323 | bool clk_hw_is_prepared(const struct clk_hw *hw); |
e55a839a | 1324 | bool clk_hw_rate_is_protected(const struct clk_hw *hw); |
be68bf88 | 1325 | bool clk_hw_is_enabled(const struct clk_hw *hw); |
2ac6b1f5 | 1326 | bool __clk_is_enabled(struct clk *clk); |
b2476490 | 1327 | struct clk *__clk_lookup(const char *name); |
0817b62c BB |
1328 | int __clk_mux_determine_rate(struct clk_hw *hw, |
1329 | struct clk_rate_request *req); | |
1330 | int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req); | |
1331 | int __clk_mux_determine_rate_closest(struct clk_hw *hw, | |
1332 | struct clk_rate_request *req); | |
4ad69b80 JB |
1333 | int clk_mux_determine_rate_flags(struct clk_hw *hw, |
1334 | struct clk_rate_request *req, | |
1335 | unsigned long flags); | |
42c86547 | 1336 | void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent); |
25399325 MR |
1337 | void clk_hw_get_rate_range(struct clk_hw *hw, unsigned long *min_rate, |
1338 | unsigned long *max_rate); | |
9783c0d9 SB |
1339 | void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate, |
1340 | unsigned long max_rate); | |
b2476490 | 1341 | |
2e65d8bf JMC |
1342 | static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src) |
1343 | { | |
1344 | dst->clk = src->clk; | |
1345 | dst->core = src->core; | |
1346 | } | |
1347 | ||
22833a91 MR |
1348 | static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate, |
1349 | unsigned long *prate, | |
1350 | const struct clk_div_table *table, | |
1351 | u8 width, unsigned long flags) | |
1352 | { | |
1353 | return divider_round_rate_parent(hw, clk_hw_get_parent(hw), | |
1354 | rate, prate, table, width, flags); | |
1355 | } | |
1356 | ||
b15ee490 JB |
1357 | static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate, |
1358 | unsigned long *prate, | |
1359 | const struct clk_div_table *table, | |
1360 | u8 width, unsigned long flags, | |
1361 | unsigned int val) | |
1362 | { | |
1363 | return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw), | |
1364 | rate, prate, table, width, flags, | |
1365 | val); | |
1366 | } | |
1367 | ||
b2476490 MT |
1368 | /* |
1369 | * FIXME clock api without lock protection | |
1370 | */ | |
1a9c069c | 1371 | unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate); |
b2476490 | 1372 | |
0b151deb SH |
1373 | struct clk_onecell_data { |
1374 | struct clk **clks; | |
1375 | unsigned int clk_num; | |
1376 | }; | |
1377 | ||
0861e5b8 | 1378 | struct clk_hw_onecell_data { |
5963f19c | 1379 | unsigned int num; |
0861e5b8 SB |
1380 | struct clk_hw *hws[]; |
1381 | }; | |
1382 | ||
c28cd1f3 | 1383 | #define CLK_OF_DECLARE(name, compat, fn) \ |
5cf9d015 | 1384 | static void __init __##name##_of_clk_init_declare(struct device_node *np) \ |
c28cd1f3 SK |
1385 | { \ |
1386 | fn(np); \ | |
1387 | fwnode_dev_initialized(of_fwnode_handle(np), true); \ | |
1388 | } \ | |
5cf9d015 | 1389 | OF_DECLARE_1(clk, name, compat, __##name##_of_clk_init_declare) |
0b151deb | 1390 | |
c7296c51 RRD |
1391 | /* |
1392 | * Use this macro when you have a driver that requires two initialization | |
1393 | * routines, one at of_clk_init(), and one at platform device probe | |
1394 | */ | |
1395 | #define CLK_OF_DECLARE_DRIVER(name, compat, fn) \ | |
339e1e54 | 1396 | static void __init name##_of_clk_init_driver(struct device_node *np) \ |
c7296c51 RRD |
1397 | { \ |
1398 | of_node_clear_flag(np, OF_POPULATED); \ | |
1399 | fn(np); \ | |
1400 | } \ | |
1401 | OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver) | |
1402 | ||
1ded879e CZ |
1403 | #define CLK_HW_INIT(_name, _parent, _ops, _flags) \ |
1404 | (&(struct clk_init_data) { \ | |
1405 | .flags = _flags, \ | |
1406 | .name = _name, \ | |
1407 | .parent_names = (const char *[]) { _parent }, \ | |
1408 | .num_parents = 1, \ | |
1409 | .ops = _ops, \ | |
1410 | }) | |
1411 | ||
99600fd4 CYT |
1412 | #define CLK_HW_INIT_HW(_name, _parent, _ops, _flags) \ |
1413 | (&(struct clk_init_data) { \ | |
1414 | .flags = _flags, \ | |
1415 | .name = _name, \ | |
1416 | .parent_hws = (const struct clk_hw*[]) { _parent }, \ | |
1417 | .num_parents = 1, \ | |
1418 | .ops = _ops, \ | |
1419 | }) | |
1420 | ||
1421 | /* | |
1422 | * This macro is intended for drivers to be able to share the otherwise | |
1423 | * individual struct clk_hw[] compound literals created by the compiler | |
1424 | * when using CLK_HW_INIT_HW. It does NOT support multiple parents. | |
1425 | */ | |
1426 | #define CLK_HW_INIT_HWS(_name, _parent, _ops, _flags) \ | |
1427 | (&(struct clk_init_data) { \ | |
1428 | .flags = _flags, \ | |
1429 | .name = _name, \ | |
1430 | .parent_hws = _parent, \ | |
1431 | .num_parents = 1, \ | |
1432 | .ops = _ops, \ | |
1433 | }) | |
1434 | ||
2d6b4f33 CYT |
1435 | #define CLK_HW_INIT_FW_NAME(_name, _parent, _ops, _flags) \ |
1436 | (&(struct clk_init_data) { \ | |
1437 | .flags = _flags, \ | |
1438 | .name = _name, \ | |
1439 | .parent_data = (const struct clk_parent_data[]) { \ | |
1440 | { .fw_name = _parent }, \ | |
1441 | }, \ | |
1442 | .num_parents = 1, \ | |
1443 | .ops = _ops, \ | |
1444 | }) | |
1445 | ||
1ded879e CZ |
1446 | #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \ |
1447 | (&(struct clk_init_data) { \ | |
1448 | .flags = _flags, \ | |
1449 | .name = _name, \ | |
1450 | .parent_names = _parents, \ | |
1451 | .num_parents = ARRAY_SIZE(_parents), \ | |
1452 | .ops = _ops, \ | |
1453 | }) | |
1454 | ||
99600fd4 CYT |
1455 | #define CLK_HW_INIT_PARENTS_HW(_name, _parents, _ops, _flags) \ |
1456 | (&(struct clk_init_data) { \ | |
1457 | .flags = _flags, \ | |
1458 | .name = _name, \ | |
1459 | .parent_hws = _parents, \ | |
1460 | .num_parents = ARRAY_SIZE(_parents), \ | |
1461 | .ops = _ops, \ | |
1462 | }) | |
1463 | ||
13933109 CYT |
1464 | #define CLK_HW_INIT_PARENTS_DATA(_name, _parents, _ops, _flags) \ |
1465 | (&(struct clk_init_data) { \ | |
1466 | .flags = _flags, \ | |
1467 | .name = _name, \ | |
1468 | .parent_data = _parents, \ | |
1469 | .num_parents = ARRAY_SIZE(_parents), \ | |
1470 | .ops = _ops, \ | |
1471 | }) | |
1472 | ||
1ded879e CZ |
1473 | #define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \ |
1474 | (&(struct clk_init_data) { \ | |
1475 | .flags = _flags, \ | |
1476 | .name = _name, \ | |
1477 | .parent_names = NULL, \ | |
1478 | .num_parents = 0, \ | |
1479 | .ops = _ops, \ | |
1480 | }) | |
1481 | ||
1482 | #define CLK_FIXED_FACTOR(_struct, _name, _parent, \ | |
1483 | _div, _mult, _flags) \ | |
1484 | struct clk_fixed_factor _struct = { \ | |
1485 | .div = _div, \ | |
1486 | .mult = _mult, \ | |
1487 | .hw.init = CLK_HW_INIT(_name, \ | |
1488 | _parent, \ | |
1489 | &clk_fixed_factor_ops, \ | |
1490 | _flags), \ | |
1491 | } | |
1492 | ||
d7b15114 CYT |
1493 | #define CLK_FIXED_FACTOR_HW(_struct, _name, _parent, \ |
1494 | _div, _mult, _flags) \ | |
1495 | struct clk_fixed_factor _struct = { \ | |
1496 | .div = _div, \ | |
1497 | .mult = _mult, \ | |
1498 | .hw.init = CLK_HW_INIT_HW(_name, \ | |
1499 | _parent, \ | |
1500 | &clk_fixed_factor_ops, \ | |
1501 | _flags), \ | |
1502 | } | |
1503 | ||
1bef004e CYT |
1504 | /* |
1505 | * This macro allows the driver to reuse the _parent array for multiple | |
1506 | * fixed factor clk declarations. | |
1507 | */ | |
1508 | #define CLK_FIXED_FACTOR_HWS(_struct, _name, _parent, \ | |
1509 | _div, _mult, _flags) \ | |
1510 | struct clk_fixed_factor _struct = { \ | |
1511 | .div = _div, \ | |
1512 | .mult = _mult, \ | |
1513 | .hw.init = CLK_HW_INIT_HWS(_name, \ | |
1514 | _parent, \ | |
1515 | &clk_fixed_factor_ops, \ | |
1516 | _flags), \ | |
1517 | } | |
1518 | ||
8b13a48b CYT |
1519 | #define CLK_FIXED_FACTOR_FW_NAME(_struct, _name, _parent, \ |
1520 | _div, _mult, _flags) \ | |
1521 | struct clk_fixed_factor _struct = { \ | |
1522 | .div = _div, \ | |
1523 | .mult = _mult, \ | |
1524 | .hw.init = CLK_HW_INIT_FW_NAME(_name, \ | |
1525 | _parent, \ | |
1526 | &clk_fixed_factor_ops, \ | |
1527 | _flags), \ | |
1528 | } | |
1529 | ||
0b151deb | 1530 | #ifdef CONFIG_OF |
766e6a4e GL |
1531 | int of_clk_add_provider(struct device_node *np, |
1532 | struct clk *(*clk_src_get)(struct of_phandle_args *args, | |
1533 | void *data), | |
1534 | void *data); | |
0861e5b8 SB |
1535 | int of_clk_add_hw_provider(struct device_node *np, |
1536 | struct clk_hw *(*get)(struct of_phandle_args *clkspec, | |
1537 | void *data), | |
1538 | void *data); | |
aa795c41 SB |
1539 | int devm_of_clk_add_hw_provider(struct device *dev, |
1540 | struct clk_hw *(*get)(struct of_phandle_args *clkspec, | |
1541 | void *data), | |
1542 | void *data); | |
766e6a4e | 1543 | void of_clk_del_provider(struct device_node *np); |
1c8934b4 | 1544 | |
766e6a4e GL |
1545 | struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, |
1546 | void *data); | |
0861e5b8 SB |
1547 | struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec, |
1548 | void *data); | |
494bfec9 | 1549 | struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data); |
0861e5b8 SB |
1550 | struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec, |
1551 | void *data); | |
2e61dfb3 DN |
1552 | int of_clk_parent_fill(struct device_node *np, const char **parents, |
1553 | unsigned int size); | |
d56f8994 LJ |
1554 | int of_clk_detect_critical(struct device_node *np, int index, |
1555 | unsigned long *flags); | |
766e6a4e | 1556 | |
0b151deb | 1557 | #else /* !CONFIG_OF */ |
f2f6c255 | 1558 | |
0b151deb SH |
1559 | static inline int of_clk_add_provider(struct device_node *np, |
1560 | struct clk *(*clk_src_get)(struct of_phandle_args *args, | |
1561 | void *data), | |
1562 | void *data) | |
1563 | { | |
1564 | return 0; | |
1565 | } | |
0861e5b8 SB |
1566 | static inline int of_clk_add_hw_provider(struct device_node *np, |
1567 | struct clk_hw *(*get)(struct of_phandle_args *clkspec, | |
1568 | void *data), | |
1569 | void *data) | |
1570 | { | |
1571 | return 0; | |
1572 | } | |
aa795c41 SB |
1573 | static inline int devm_of_clk_add_hw_provider(struct device *dev, |
1574 | struct clk_hw *(*get)(struct of_phandle_args *clkspec, | |
1575 | void *data), | |
1576 | void *data) | |
1577 | { | |
1578 | return 0; | |
1579 | } | |
20dd882a | 1580 | static inline void of_clk_del_provider(struct device_node *np) {} |
1c8934b4 | 1581 | |
0b151deb SH |
1582 | static inline struct clk *of_clk_src_simple_get( |
1583 | struct of_phandle_args *clkspec, void *data) | |
1584 | { | |
1585 | return ERR_PTR(-ENOENT); | |
1586 | } | |
0861e5b8 SB |
1587 | static inline struct clk_hw * |
1588 | of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data) | |
1589 | { | |
1590 | return ERR_PTR(-ENOENT); | |
1591 | } | |
0b151deb SH |
1592 | static inline struct clk *of_clk_src_onecell_get( |
1593 | struct of_phandle_args *clkspec, void *data) | |
1594 | { | |
1595 | return ERR_PTR(-ENOENT); | |
1596 | } | |
0861e5b8 SB |
1597 | static inline struct clk_hw * |
1598 | of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data) | |
1599 | { | |
1600 | return ERR_PTR(-ENOENT); | |
1601 | } | |
679c51cf SB |
1602 | static inline int of_clk_parent_fill(struct device_node *np, |
1603 | const char **parents, unsigned int size) | |
1604 | { | |
1605 | return 0; | |
1606 | } | |
d56f8994 LJ |
1607 | static inline int of_clk_detect_critical(struct device_node *np, int index, |
1608 | unsigned long *flags) | |
1609 | { | |
1610 | return 0; | |
1611 | } | |
0b151deb | 1612 | #endif /* CONFIG_OF */ |
aa514ce3 | 1613 | |
43536548 K |
1614 | void clk_gate_restore_context(struct clk_hw *hw); |
1615 | ||
b2476490 | 1616 | #endif /* CLK_PROVIDER_H */ |