Commit | Line | Data |
---|---|---|
ebafb63d | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
b2476490 | 2 | /* |
b2476490 MT |
3 | * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com> |
4 | * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org> | |
b2476490 MT |
5 | */ |
6 | #ifndef __LINUX_CLK_PROVIDER_H | |
7 | #define __LINUX_CLK_PROVIDER_H | |
8 | ||
355bb165 | 9 | #include <linux/of.h> |
eb06d6bb | 10 | #include <linux/of_clk.h> |
b2476490 | 11 | |
b2476490 MT |
12 | /* |
13 | * flags used across common struct clk. these flags should only affect the | |
14 | * top-level framework. custom flags for dealing with hardware specifics | |
15 | * belong in struct clk_foo | |
a6059ab9 GU |
16 | * |
17 | * Please update clk_flags[] in drivers/clk/clk.c when making changes here! | |
b2476490 MT |
18 | */ |
19 | #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ | |
20 | #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ | |
21 | #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ | |
22 | #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ | |
b9610e74 | 23 | /* unused */ |
90b6c5c7 | 24 | /* unused */ |
a093bde2 | 25 | #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ |
819c1de3 | 26 | #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ |
5279fc40 | 27 | #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */ |
d8d91987 | 28 | #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */ |
2eb8c710 | 29 | #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */ |
32b9b109 | 30 | #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */ |
a4b3518d DA |
31 | /* parents need enable during gate/ungate, set rate and re-parent */ |
32 | #define CLK_OPS_PARENT_ENABLE BIT(12) | |
9fba738a JB |
33 | /* duty cycle call may be forwarded to the parent clock */ |
34 | #define CLK_DUTY_CYCLE_PARENT BIT(13) | |
b2476490 | 35 | |
61ae7656 | 36 | struct clk; |
0197b3ea | 37 | struct clk_hw; |
035a61c3 | 38 | struct clk_core; |
c646cbf1 | 39 | struct dentry; |
0197b3ea | 40 | |
0817b62c BB |
41 | /** |
42 | * struct clk_rate_request - Structure encoding the clk constraints that | |
43 | * a clock user might require. | |
44 | * | |
45 | * @rate: Requested clock rate. This field will be adjusted by | |
46 | * clock drivers according to hardware capabilities. | |
47 | * @min_rate: Minimum rate imposed by clk users. | |
1971dfb7 | 48 | * @max_rate: Maximum rate imposed by clk users. |
0817b62c BB |
49 | * @best_parent_rate: The best parent rate a parent can provide to fulfill the |
50 | * requested constraints. | |
51 | * @best_parent_hw: The most appropriate parent clock that fulfills the | |
52 | * requested constraints. | |
53 | * | |
54 | */ | |
55 | struct clk_rate_request { | |
56 | unsigned long rate; | |
57 | unsigned long min_rate; | |
58 | unsigned long max_rate; | |
59 | unsigned long best_parent_rate; | |
60 | struct clk_hw *best_parent_hw; | |
61 | }; | |
62 | ||
9fba738a JB |
63 | /** |
64 | * struct clk_duty - Struture encoding the duty cycle ratio of a clock | |
65 | * | |
66 | * @num: Numerator of the duty cycle ratio | |
67 | * @den: Denominator of the duty cycle ratio | |
68 | */ | |
69 | struct clk_duty { | |
70 | unsigned int num; | |
71 | unsigned int den; | |
72 | }; | |
73 | ||
b2476490 MT |
74 | /** |
75 | * struct clk_ops - Callback operations for hardware clocks; these are to | |
76 | * be provided by the clock implementation, and will be called by drivers | |
77 | * through the clk_* api. | |
78 | * | |
79 | * @prepare: Prepare the clock for enabling. This must not return until | |
725b418b GU |
80 | * the clock is fully prepared, and it's safe to call clk_enable. |
81 | * This callback is intended to allow clock implementations to | |
82 | * do any initialisation that may sleep. Called with | |
83 | * prepare_lock held. | |
b2476490 MT |
84 | * |
85 | * @unprepare: Release the clock from its prepared state. This will typically | |
725b418b GU |
86 | * undo any work done in the @prepare callback. Called with |
87 | * prepare_lock held. | |
b2476490 | 88 | * |
3d6ee287 UH |
89 | * @is_prepared: Queries the hardware to determine if the clock is prepared. |
90 | * This function is allowed to sleep. Optional, if this op is not | |
91 | * set then the prepare count will be used. | |
92 | * | |
3cc8247f UH |
93 | * @unprepare_unused: Unprepare the clock atomically. Only called from |
94 | * clk_disable_unused for prepare clocks with special needs. | |
95 | * Called with prepare mutex held. This function may sleep. | |
96 | * | |
b2476490 | 97 | * @enable: Enable the clock atomically. This must not return until the |
725b418b GU |
98 | * clock is generating a valid clock signal, usable by consumer |
99 | * devices. Called with enable_lock held. This function must not | |
100 | * sleep. | |
b2476490 MT |
101 | * |
102 | * @disable: Disable the clock atomically. Called with enable_lock held. | |
725b418b | 103 | * This function must not sleep. |
b2476490 | 104 | * |
119c7127 | 105 | * @is_enabled: Queries the hardware to determine if the clock is enabled. |
725b418b GU |
106 | * This function must not sleep. Optional, if this op is not |
107 | * set then the enable count will be used. | |
119c7127 | 108 | * |
7c045a55 MT |
109 | * @disable_unused: Disable the clock atomically. Only called from |
110 | * clk_disable_unused for gate clocks with special needs. | |
111 | * Called with enable_lock held. This function must not | |
112 | * sleep. | |
113 | * | |
8b95d1ce RD |
114 | * @save_context: Save the context of the clock in prepration for poweroff. |
115 | * | |
116 | * @restore_context: Restore the context of the clock after a restoration | |
117 | * of power. | |
118 | * | |
7ce3e8cc | 119 | * @recalc_rate Recalculate the rate of this clock, by querying hardware. The |
725b418b GU |
120 | * parent rate is an input parameter. It is up to the caller to |
121 | * ensure that the prepare_mutex is held across this call. | |
122 | * Returns the calculated rate. Optional, but recommended - if | |
123 | * this op is not set then clock rate will be initialized to 0. | |
b2476490 MT |
124 | * |
125 | * @round_rate: Given a target rate as input, returns the closest rate actually | |
54e73016 GU |
126 | * supported by the clock. The parent rate is an input/output |
127 | * parameter. | |
b2476490 | 128 | * |
71472c0c JH |
129 | * @determine_rate: Given a target rate as input, returns the closest rate |
130 | * actually supported by the clock, and optionally the parent clock | |
131 | * that should be used to provide the clock rate. | |
132 | * | |
b2476490 | 133 | * @set_parent: Change the input source of this clock; for clocks with multiple |
54e73016 GU |
134 | * possible parents specify a new parent by passing in the index |
135 | * as a u8 corresponding to the parent in either the .parent_names | |
136 | * or .parents arrays. This function in affect translates an | |
137 | * array index into the value programmed into the hardware. | |
138 | * Returns 0 on success, -EERROR otherwise. | |
139 | * | |
b2476490 | 140 | * @get_parent: Queries the hardware to determine the parent of a clock. The |
725b418b GU |
141 | * return value is a u8 which specifies the index corresponding to |
142 | * the parent clock. This index can be applied to either the | |
143 | * .parent_names or .parents arrays. In short, this function | |
144 | * translates the parent value read from hardware into an array | |
145 | * index. Currently only called when the clock is initialized by | |
146 | * __clk_init. This callback is mandatory for clocks with | |
147 | * multiple parents. It is optional (and unnecessary) for clocks | |
148 | * with 0 or 1 parents. | |
b2476490 | 149 | * |
1c0035d7 SG |
150 | * @set_rate: Change the rate of this clock. The requested rate is specified |
151 | * by the second argument, which should typically be the return | |
152 | * of .round_rate call. The third argument gives the parent rate | |
153 | * which is likely helpful for most .set_rate implementation. | |
154 | * Returns 0 on success, -EERROR otherwise. | |
b2476490 | 155 | * |
3fa2252b SB |
156 | * @set_rate_and_parent: Change the rate and the parent of this clock. The |
157 | * requested rate is specified by the second argument, which | |
158 | * should typically be the return of .round_rate call. The | |
159 | * third argument gives the parent rate which is likely helpful | |
160 | * for most .set_rate_and_parent implementation. The fourth | |
161 | * argument gives the parent index. This callback is optional (and | |
162 | * unnecessary) for clocks with 0 or 1 parents as well as | |
163 | * for clocks that can tolerate switching the rate and the parent | |
164 | * separately via calls to .set_parent and .set_rate. | |
165 | * Returns 0 on success, -EERROR otherwise. | |
166 | * | |
54e73016 GU |
167 | * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy |
168 | * is expressed in ppb (parts per billion). The parent accuracy is | |
169 | * an input parameter. | |
170 | * Returns the calculated accuracy. Optional - if this op is not | |
171 | * set then clock accuracy will be initialized to parent accuracy | |
172 | * or 0 (perfect clock) if clock has no parent. | |
173 | * | |
9824cf73 MR |
174 | * @get_phase: Queries the hardware to get the current phase of a clock. |
175 | * Returned values are 0-359 degrees on success, negative | |
176 | * error codes on failure. | |
177 | * | |
e59c5371 MT |
178 | * @set_phase: Shift the phase this clock signal in degrees specified |
179 | * by the second argument. Valid values for degrees are | |
180 | * 0-359. Return 0 on success, otherwise -EERROR. | |
181 | * | |
9fba738a JB |
182 | * @get_duty_cycle: Queries the hardware to get the current duty cycle ratio |
183 | * of a clock. Returned values denominator cannot be 0 and must be | |
184 | * superior or equal to the numerator. | |
185 | * | |
186 | * @set_duty_cycle: Apply the duty cycle ratio to this clock signal specified by | |
187 | * the numerator (2nd argurment) and denominator (3rd argument). | |
188 | * Argument must be a valid ratio (denominator > 0 | |
189 | * and >= numerator) Return 0 on success, otherwise -EERROR. | |
190 | * | |
54e73016 | 191 | * @init: Perform platform-specific initialization magic. |
6c4411f1 | 192 | * This is not used by any of the basic clock types. |
89d079dc JB |
193 | * This callback exist for HW which needs to perform some |
194 | * initialisation magic for CCF to get an accurate view of the | |
195 | * clock. It may also be used dynamic resource allocation is | |
196 | * required. It shall not used to deal with clock parameters, | |
197 | * such as rate or parents. | |
198 | * Returns 0 on success, -EERROR otherwise. | |
54e73016 | 199 | * |
f873744c JB |
200 | * @terminate: Free any resource allocated by init. |
201 | * | |
c646cbf1 AE |
202 | * @debug_init: Set up type-specific debugfs entries for this clock. This |
203 | * is called once, after the debugfs directory entry for this | |
204 | * clock has been created. The dentry pointer representing that | |
205 | * directory is provided as an argument. Called with | |
206 | * prepare_lock held. Returns 0 on success, -EERROR otherwise. | |
207 | * | |
3fa2252b | 208 | * |
b2476490 MT |
209 | * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow |
210 | * implementations to split any work between atomic (enable) and sleepable | |
211 | * (prepare) contexts. If enabling a clock requires code that might sleep, | |
212 | * this must be done in clk_prepare. Clock enable code that will never be | |
7ce3e8cc | 213 | * called in a sleepable context may be implemented in clk_enable. |
b2476490 MT |
214 | * |
215 | * Typically, drivers will call clk_prepare when a clock may be needed later | |
216 | * (eg. when a device is opened), and clk_enable when the clock is actually | |
217 | * required (eg. from an interrupt). Note that clk_prepare MUST have been | |
218 | * called before clk_enable. | |
219 | */ | |
220 | struct clk_ops { | |
221 | int (*prepare)(struct clk_hw *hw); | |
222 | void (*unprepare)(struct clk_hw *hw); | |
3d6ee287 | 223 | int (*is_prepared)(struct clk_hw *hw); |
3cc8247f | 224 | void (*unprepare_unused)(struct clk_hw *hw); |
b2476490 MT |
225 | int (*enable)(struct clk_hw *hw); |
226 | void (*disable)(struct clk_hw *hw); | |
227 | int (*is_enabled)(struct clk_hw *hw); | |
7c045a55 | 228 | void (*disable_unused)(struct clk_hw *hw); |
8b95d1ce RD |
229 | int (*save_context)(struct clk_hw *hw); |
230 | void (*restore_context)(struct clk_hw *hw); | |
b2476490 MT |
231 | unsigned long (*recalc_rate)(struct clk_hw *hw, |
232 | unsigned long parent_rate); | |
54e73016 GU |
233 | long (*round_rate)(struct clk_hw *hw, unsigned long rate, |
234 | unsigned long *parent_rate); | |
0817b62c BB |
235 | int (*determine_rate)(struct clk_hw *hw, |
236 | struct clk_rate_request *req); | |
b2476490 MT |
237 | int (*set_parent)(struct clk_hw *hw, u8 index); |
238 | u8 (*get_parent)(struct clk_hw *hw); | |
54e73016 GU |
239 | int (*set_rate)(struct clk_hw *hw, unsigned long rate, |
240 | unsigned long parent_rate); | |
3fa2252b SB |
241 | int (*set_rate_and_parent)(struct clk_hw *hw, |
242 | unsigned long rate, | |
243 | unsigned long parent_rate, u8 index); | |
5279fc40 BB |
244 | unsigned long (*recalc_accuracy)(struct clk_hw *hw, |
245 | unsigned long parent_accuracy); | |
9824cf73 | 246 | int (*get_phase)(struct clk_hw *hw); |
e59c5371 | 247 | int (*set_phase)(struct clk_hw *hw, int degrees); |
9fba738a JB |
248 | int (*get_duty_cycle)(struct clk_hw *hw, |
249 | struct clk_duty *duty); | |
250 | int (*set_duty_cycle)(struct clk_hw *hw, | |
251 | struct clk_duty *duty); | |
89d079dc | 252 | int (*init)(struct clk_hw *hw); |
f873744c | 253 | void (*terminate)(struct clk_hw *hw); |
d75d50c0 | 254 | void (*debug_init)(struct clk_hw *hw, struct dentry *dentry); |
b2476490 MT |
255 | }; |
256 | ||
fc0c209c SB |
257 | /** |
258 | * struct clk_parent_data - clk parent information | |
259 | * @hw: parent clk_hw pointer (used for clk providers with internal clks) | |
260 | * @fw_name: parent name local to provider registering clk | |
261 | * @name: globally unique parent name (used as a fallback) | |
601b6e93 | 262 | * @index: parent index local to provider registering clk (if @fw_name absent) |
fc0c209c SB |
263 | */ |
264 | struct clk_parent_data { | |
265 | const struct clk_hw *hw; | |
266 | const char *fw_name; | |
267 | const char *name; | |
601b6e93 | 268 | int index; |
fc0c209c SB |
269 | }; |
270 | ||
0197b3ea SK |
271 | /** |
272 | * struct clk_init_data - holds init data that's common to all clocks and is | |
273 | * shared between the clock provider and the common clock framework. | |
274 | * | |
275 | * @name: clock name | |
276 | * @ops: operations this clock supports | |
277 | * @parent_names: array of string names for all possible parents | |
fc0c209c SB |
278 | * @parent_data: array of parent data for all possible parents (when some |
279 | * parents are external to the clk controller) | |
280 | * @parent_hws: array of pointers to all possible parents (when all parents | |
281 | * are internal to the clk controller) | |
0197b3ea SK |
282 | * @num_parents: number of possible parents |
283 | * @flags: framework-level hints and quirks | |
284 | */ | |
285 | struct clk_init_data { | |
286 | const char *name; | |
287 | const struct clk_ops *ops; | |
fc0c209c | 288 | /* Only one of the following three should be assigned */ |
2893c379 | 289 | const char * const *parent_names; |
fc0c209c SB |
290 | const struct clk_parent_data *parent_data; |
291 | const struct clk_hw **parent_hws; | |
0197b3ea SK |
292 | u8 num_parents; |
293 | unsigned long flags; | |
294 | }; | |
295 | ||
296 | /** | |
297 | * struct clk_hw - handle for traversing from a struct clk to its corresponding | |
298 | * hardware-specific structure. struct clk_hw should be declared within struct | |
299 | * clk_foo and then referenced by the struct clk instance that uses struct | |
300 | * clk_foo's clk_ops | |
301 | * | |
035a61c3 TV |
302 | * @core: pointer to the struct clk_core instance that points back to this |
303 | * struct clk_hw instance | |
304 | * | |
305 | * @clk: pointer to the per-user struct clk instance that can be used to call | |
306 | * into the clk API | |
0197b3ea SK |
307 | * |
308 | * @init: pointer to struct clk_init_data that contains the init data shared | |
0214f33c SB |
309 | * with the common clock framework. This pointer will be set to NULL once |
310 | * a clk_register() variant is called on this clk_hw pointer. | |
0197b3ea SK |
311 | */ |
312 | struct clk_hw { | |
035a61c3 | 313 | struct clk_core *core; |
0197b3ea | 314 | struct clk *clk; |
dc4cd941 | 315 | const struct clk_init_data *init; |
0197b3ea SK |
316 | }; |
317 | ||
9d9f78ed MT |
318 | /* |
319 | * DOC: Basic clock implementations common to many platforms | |
320 | * | |
321 | * Each basic clock hardware type is comprised of a structure describing the | |
322 | * clock hardware, implementations of the relevant callbacks in struct clk_ops, | |
323 | * unique flags for that hardware type, a registration function and an | |
324 | * alternative macro for static initialization | |
325 | */ | |
326 | ||
327 | /** | |
328 | * struct clk_fixed_rate - fixed-rate clock | |
329 | * @hw: handle between common and hardware-specific interfaces | |
330 | * @fixed_rate: constant frequency of clock | |
32205b75 | 331 | * @fixed_accuracy: constant accuracy of clock in ppb (parts per billion) |
2d34f09e | 332 | * @flags: hardware specific flags |
58f0c4ba SB |
333 | * |
334 | * Flags: | |
335 | * * CLK_FIXED_RATE_PARENT_ACCURACY - Use the accuracy of the parent clk | |
336 | * instead of what's set in @fixed_accuracy. | |
9d9f78ed MT |
337 | */ |
338 | struct clk_fixed_rate { | |
339 | struct clk_hw hw; | |
340 | unsigned long fixed_rate; | |
0903ea60 | 341 | unsigned long fixed_accuracy; |
2d34f09e | 342 | unsigned long flags; |
9d9f78ed MT |
343 | }; |
344 | ||
edfa3784 | 345 | #define CLK_FIXED_RATE_PARENT_ACCURACY BIT(0) |
5fd9c05c | 346 | |
bffad66e | 347 | extern const struct clk_ops clk_fixed_rate_ops; |
2d34f09e SB |
348 | struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev, |
349 | struct device_node *np, const char *name, | |
350 | const char *parent_name, const struct clk_hw *parent_hw, | |
351 | const struct clk_parent_data *parent_data, unsigned long flags, | |
352 | unsigned long fixed_rate, unsigned long fixed_accuracy, | |
353 | unsigned long clk_fixed_flags); | |
9d9f78ed MT |
354 | struct clk *clk_register_fixed_rate(struct device *dev, const char *name, |
355 | const char *parent_name, unsigned long flags, | |
356 | unsigned long fixed_rate); | |
2d34f09e SB |
357 | /** |
358 | * clk_hw_register_fixed_rate - register fixed-rate clock with the clock | |
359 | * framework | |
360 | * @dev: device that is registering this clock | |
361 | * @name: name of this clock | |
362 | * @parent_name: name of clock's parent | |
363 | * @flags: framework-specific flags | |
364 | * @fixed_rate: non-adjustable clock rate | |
365 | */ | |
366 | #define clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate) \ | |
367 | __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \ | |
368 | NULL, (flags), (fixed_rate), 0, 0) | |
369 | /** | |
370 | * clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with | |
371 | * the clock framework | |
372 | * @dev: device that is registering this clock | |
373 | * @name: name of this clock | |
374 | * @parent_hw: pointer to parent clk | |
375 | * @flags: framework-specific flags | |
376 | * @fixed_rate: non-adjustable clock rate | |
377 | */ | |
378 | #define clk_hw_register_fixed_rate_parent_hw(dev, name, parent_hw, flags, \ | |
379 | fixed_rate) \ | |
380 | __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw), \ | |
381 | NULL, (flags), (fixed_rate), 0, 0) | |
382 | /** | |
383 | * clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with | |
384 | * the clock framework | |
385 | * @dev: device that is registering this clock | |
386 | * @name: name of this clock | |
387 | * @parent_data: parent clk data | |
388 | * @flags: framework-specific flags | |
389 | * @fixed_rate: non-adjustable clock rate | |
390 | */ | |
391 | #define clk_hw_register_fixed_rate_parent_data(dev, name, parent_hw, flags, \ | |
392 | fixed_rate) \ | |
393 | __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \ | |
394 | (parent_data), (flags), (fixed_rate), 0, \ | |
395 | 0) | |
396 | /** | |
397 | * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with | |
398 | * the clock framework | |
399 | * @dev: device that is registering this clock | |
400 | * @name: name of this clock | |
401 | * @parent_name: name of clock's parent | |
402 | * @flags: framework-specific flags | |
403 | * @fixed_rate: non-adjustable clock rate | |
1f1bb96d | 404 | * @fixed_accuracy: non-adjustable clock accuracy |
2d34f09e SB |
405 | */ |
406 | #define clk_hw_register_fixed_rate_with_accuracy(dev, name, parent_name, \ | |
407 | flags, fixed_rate, \ | |
408 | fixed_accuracy) \ | |
409 | __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), \ | |
410 | NULL, NULL, (flags), (fixed_rate), \ | |
411 | (fixed_accuracy), 0) | |
412 | /** | |
413 | * clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate | |
414 | * clock with the clock framework | |
415 | * @dev: device that is registering this clock | |
416 | * @name: name of this clock | |
417 | * @parent_hw: pointer to parent clk | |
418 | * @flags: framework-specific flags | |
419 | * @fixed_rate: non-adjustable clock rate | |
420 | * @fixed_accuracy: non-adjustable clock accuracy | |
421 | */ | |
422 | #define clk_hw_register_fixed_rate_with_accuracy_parent_hw(dev, name, \ | |
423 | parent_hw, flags, fixed_rate, fixed_accuracy) \ | |
424 | __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw) \ | |
425 | NULL, NULL, (flags), (fixed_rate), \ | |
426 | (fixed_accuracy), 0) | |
427 | /** | |
428 | * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate | |
429 | * clock with the clock framework | |
430 | * @dev: device that is registering this clock | |
431 | * @name: name of this clock | |
432 | * @parent_name: name of clock's parent | |
433 | * @flags: framework-specific flags | |
434 | * @fixed_rate: non-adjustable clock rate | |
435 | * @fixed_accuracy: non-adjustable clock accuracy | |
436 | */ | |
437 | #define clk_hw_register_fixed_rate_with_accuracy_parent_data(dev, name, \ | |
438 | parent_data, flags, fixed_rate, fixed_accuracy) \ | |
439 | __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \ | |
440 | (parent_data), NULL, (flags), \ | |
441 | (fixed_rate), (fixed_accuracy), 0) | |
442 | ||
0b225e41 | 443 | void clk_unregister_fixed_rate(struct clk *clk); |
52445637 | 444 | void clk_hw_unregister_fixed_rate(struct clk_hw *hw); |
26ef56be | 445 | |
015ba402 GL |
446 | void of_fixed_clk_setup(struct device_node *np); |
447 | ||
9d9f78ed MT |
448 | /** |
449 | * struct clk_gate - gating clock | |
450 | * | |
451 | * @hw: handle between common and hardware-specific interfaces | |
452 | * @reg: register controlling gate | |
453 | * @bit_idx: single bit controlling gate | |
454 | * @flags: hardware-specific flags | |
455 | * @lock: register lock | |
456 | * | |
457 | * Clock which can gate its output. Implements .enable & .disable | |
458 | * | |
459 | * Flags: | |
1f73f31a | 460 | * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to |
725b418b GU |
461 | * enable the clock. Setting this flag does the opposite: setting the bit |
462 | * disable the clock and clearing it enables the clock | |
04577994 | 463 | * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit |
725b418b GU |
464 | * of this register, and mask of gate bits are in higher 16-bit of this |
465 | * register. While setting the gate bits, higher 16-bit should also be | |
466 | * updated to indicate changing gate bits. | |
d1c8a501 JG |
467 | * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for |
468 | * the gate register. Setting this flag makes the register accesses big | |
469 | * endian. | |
9d9f78ed MT |
470 | */ |
471 | struct clk_gate { | |
472 | struct clk_hw hw; | |
473 | void __iomem *reg; | |
474 | u8 bit_idx; | |
475 | u8 flags; | |
476 | spinlock_t *lock; | |
9d9f78ed MT |
477 | }; |
478 | ||
5fd9c05c GT |
479 | #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw) |
480 | ||
9d9f78ed | 481 | #define CLK_GATE_SET_TO_DISABLE BIT(0) |
04577994 | 482 | #define CLK_GATE_HIWORD_MASK BIT(1) |
d1c8a501 | 483 | #define CLK_GATE_BIG_ENDIAN BIT(2) |
9d9f78ed | 484 | |
bffad66e | 485 | extern const struct clk_ops clk_gate_ops; |
194efb6e SB |
486 | struct clk_hw *__clk_hw_register_gate(struct device *dev, |
487 | struct device_node *np, const char *name, | |
488 | const char *parent_name, const struct clk_hw *parent_hw, | |
489 | const struct clk_parent_data *parent_data, | |
490 | unsigned long flags, | |
9d9f78ed MT |
491 | void __iomem *reg, u8 bit_idx, |
492 | u8 clk_gate_flags, spinlock_t *lock); | |
815f0e73 HV |
493 | struct clk_hw *__devm_clk_hw_register_gate(struct device *dev, |
494 | struct device_node *np, const char *name, | |
495 | const char *parent_name, const struct clk_hw *parent_hw, | |
496 | const struct clk_parent_data *parent_data, | |
497 | unsigned long flags, | |
498 | void __iomem *reg, u8 bit_idx, | |
499 | u8 clk_gate_flags, spinlock_t *lock); | |
194efb6e | 500 | struct clk *clk_register_gate(struct device *dev, const char *name, |
e270d8cb SB |
501 | const char *parent_name, unsigned long flags, |
502 | void __iomem *reg, u8 bit_idx, | |
503 | u8 clk_gate_flags, spinlock_t *lock); | |
194efb6e SB |
504 | /** |
505 | * clk_hw_register_gate - register a gate clock with the clock framework | |
506 | * @dev: device that is registering this clock | |
507 | * @name: name of this clock | |
508 | * @parent_name: name of this clock's parent | |
509 | * @flags: framework-specific flags for this clock | |
510 | * @reg: register address to control gating of this clock | |
511 | * @bit_idx: which bit in the register controls gating of this clock | |
512 | * @clk_gate_flags: gate-specific flags for this clock | |
513 | * @lock: shared register lock for this clock | |
514 | */ | |
515 | #define clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx, \ | |
516 | clk_gate_flags, lock) \ | |
517 | __clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \ | |
518 | NULL, (flags), (reg), (bit_idx), \ | |
519 | (clk_gate_flags), (lock)) | |
520 | /** | |
521 | * clk_hw_register_gate_parent_hw - register a gate clock with the clock | |
522 | * framework | |
523 | * @dev: device that is registering this clock | |
524 | * @name: name of this clock | |
525 | * @parent_hw: pointer to parent clk | |
526 | * @flags: framework-specific flags for this clock | |
527 | * @reg: register address to control gating of this clock | |
528 | * @bit_idx: which bit in the register controls gating of this clock | |
529 | * @clk_gate_flags: gate-specific flags for this clock | |
530 | * @lock: shared register lock for this clock | |
531 | */ | |
4e934301 | 532 | #define clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, reg, \ |
194efb6e | 533 | bit_idx, clk_gate_flags, lock) \ |
4e934301 | 534 | __clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw), \ |
194efb6e SB |
535 | NULL, (flags), (reg), (bit_idx), \ |
536 | (clk_gate_flags), (lock)) | |
537 | /** | |
538 | * clk_hw_register_gate_parent_data - register a gate clock with the clock | |
539 | * framework | |
540 | * @dev: device that is registering this clock | |
541 | * @name: name of this clock | |
542 | * @parent_data: parent clk data | |
543 | * @flags: framework-specific flags for this clock | |
544 | * @reg: register address to control gating of this clock | |
545 | * @bit_idx: which bit in the register controls gating of this clock | |
546 | * @clk_gate_flags: gate-specific flags for this clock | |
547 | * @lock: shared register lock for this clock | |
548 | */ | |
4e934301 | 549 | #define clk_hw_register_gate_parent_data(dev, name, parent_data, flags, reg, \ |
194efb6e | 550 | bit_idx, clk_gate_flags, lock) \ |
4e934301 SB |
551 | __clk_hw_register_gate((dev), NULL, (name), NULL, NULL, (parent_data), \ |
552 | (flags), (reg), (bit_idx), \ | |
194efb6e | 553 | (clk_gate_flags), (lock)) |
815f0e73 HV |
554 | /** |
555 | * devm_clk_hw_register_gate - register a gate clock with the clock framework | |
556 | * @dev: device that is registering this clock | |
557 | * @name: name of this clock | |
558 | * @parent_name: name of this clock's parent | |
559 | * @flags: framework-specific flags for this clock | |
560 | * @reg: register address to control gating of this clock | |
561 | * @bit_idx: which bit in the register controls gating of this clock | |
562 | * @clk_gate_flags: gate-specific flags for this clock | |
563 | * @lock: shared register lock for this clock | |
564 | */ | |
565 | #define devm_clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx,\ | |
566 | clk_gate_flags, lock) \ | |
567 | __devm_clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \ | |
568 | NULL, (flags), (reg), (bit_idx), \ | |
569 | (clk_gate_flags), (lock)) | |
4e3c021f | 570 | void clk_unregister_gate(struct clk *clk); |
e270d8cb | 571 | void clk_hw_unregister_gate(struct clk_hw *hw); |
0a9c869d | 572 | int clk_gate_is_enabled(struct clk_hw *hw); |
9d9f78ed | 573 | |
357c3f0a RN |
574 | struct clk_div_table { |
575 | unsigned int val; | |
576 | unsigned int div; | |
577 | }; | |
578 | ||
9d9f78ed MT |
579 | /** |
580 | * struct clk_divider - adjustable divider clock | |
581 | * | |
582 | * @hw: handle between common and hardware-specific interfaces | |
583 | * @reg: register containing the divider | |
584 | * @shift: shift to the divider bit field | |
585 | * @width: width of the divider bit field | |
357c3f0a | 586 | * @table: array of value/divider pairs, last entry should have div = 0 |
9d9f78ed MT |
587 | * @lock: register lock |
588 | * | |
589 | * Clock with an adjustable divider affecting its output frequency. Implements | |
590 | * .recalc_rate, .set_rate and .round_rate | |
591 | * | |
592 | * Flags: | |
593 | * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the | |
725b418b GU |
594 | * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is |
595 | * the raw value read from the register, with the value of zero considered | |
056b2053 | 596 | * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set. |
9d9f78ed | 597 | * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from |
725b418b | 598 | * the hardware register |
056b2053 SB |
599 | * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have |
600 | * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor. | |
601 | * Some hardware implementations gracefully handle this case and allow a | |
602 | * zero divisor by not modifying their input clock | |
603 | * (divide by one / bypass). | |
d57dfe75 | 604 | * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit |
725b418b GU |
605 | * of this register, and mask of divider bits are in higher 16-bit of this |
606 | * register. While setting the divider bits, higher 16-bit should also be | |
607 | * updated to indicate changing divider bits. | |
774b5143 MC |
608 | * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded |
609 | * to the closest integer instead of the up one. | |
79c6ab50 HS |
610 | * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should |
611 | * not be changed by the clock framework. | |
afe76c8f JQ |
612 | * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED |
613 | * except when the value read from the register is zero, the divisor is | |
614 | * 2^width of the field. | |
434d69fa JG |
615 | * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used |
616 | * for the divider register. Setting this flag makes the register accesses | |
617 | * big endian. | |
9d9f78ed MT |
618 | */ |
619 | struct clk_divider { | |
620 | struct clk_hw hw; | |
621 | void __iomem *reg; | |
622 | u8 shift; | |
623 | u8 width; | |
624 | u8 flags; | |
357c3f0a | 625 | const struct clk_div_table *table; |
9d9f78ed | 626 | spinlock_t *lock; |
9d9f78ed MT |
627 | }; |
628 | ||
e6d3cc7b | 629 | #define clk_div_mask(width) ((1 << (width)) - 1) |
5fd9c05c GT |
630 | #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) |
631 | ||
9d9f78ed MT |
632 | #define CLK_DIVIDER_ONE_BASED BIT(0) |
633 | #define CLK_DIVIDER_POWER_OF_TWO BIT(1) | |
056b2053 | 634 | #define CLK_DIVIDER_ALLOW_ZERO BIT(2) |
d57dfe75 | 635 | #define CLK_DIVIDER_HIWORD_MASK BIT(3) |
774b5143 | 636 | #define CLK_DIVIDER_ROUND_CLOSEST BIT(4) |
79c6ab50 | 637 | #define CLK_DIVIDER_READ_ONLY BIT(5) |
afe76c8f | 638 | #define CLK_DIVIDER_MAX_AT_ZERO BIT(6) |
434d69fa | 639 | #define CLK_DIVIDER_BIG_ENDIAN BIT(7) |
9d9f78ed | 640 | |
bffad66e | 641 | extern const struct clk_ops clk_divider_ops; |
50359819 | 642 | extern const struct clk_ops clk_divider_ro_ops; |
bca9690b SB |
643 | |
644 | unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate, | |
645 | unsigned int val, const struct clk_div_table *table, | |
12a26c29 | 646 | unsigned long flags, unsigned long width); |
22833a91 MR |
647 | long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, |
648 | unsigned long rate, unsigned long *prate, | |
649 | const struct clk_div_table *table, | |
650 | u8 width, unsigned long flags); | |
b15ee490 JB |
651 | long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, |
652 | unsigned long rate, unsigned long *prate, | |
653 | const struct clk_div_table *table, u8 width, | |
654 | unsigned long flags, unsigned int val); | |
bbd7a6cc MB |
655 | int divider_determine_rate(struct clk_hw *hw, struct clk_rate_request *req, |
656 | const struct clk_div_table *table, u8 width, | |
657 | unsigned long flags); | |
658 | int divider_ro_determine_rate(struct clk_hw *hw, struct clk_rate_request *req, | |
659 | const struct clk_div_table *table, u8 width, | |
660 | unsigned long flags, unsigned int val); | |
bca9690b SB |
661 | int divider_get_val(unsigned long rate, unsigned long parent_rate, |
662 | const struct clk_div_table *table, u8 width, | |
663 | unsigned long flags); | |
664 | ||
ff258817 SB |
665 | struct clk_hw *__clk_hw_register_divider(struct device *dev, |
666 | struct device_node *np, const char *name, | |
667 | const char *parent_name, const struct clk_hw *parent_hw, | |
668 | const struct clk_parent_data *parent_data, unsigned long flags, | |
669 | void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, | |
670 | const struct clk_div_table *table, spinlock_t *lock); | |
26792699 MW |
671 | struct clk_hw *__devm_clk_hw_register_divider(struct device *dev, |
672 | struct device_node *np, const char *name, | |
673 | const char *parent_name, const struct clk_hw *parent_hw, | |
674 | const struct clk_parent_data *parent_data, unsigned long flags, | |
675 | void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, | |
676 | const struct clk_div_table *table, spinlock_t *lock); | |
357c3f0a RN |
677 | struct clk *clk_register_divider_table(struct device *dev, const char *name, |
678 | const char *parent_name, unsigned long flags, | |
679 | void __iomem *reg, u8 shift, u8 width, | |
680 | u8 clk_divider_flags, const struct clk_div_table *table, | |
681 | spinlock_t *lock); | |
ff258817 SB |
682 | /** |
683 | * clk_register_divider - register a divider clock with the clock framework | |
684 | * @dev: device registering this clock | |
685 | * @name: name of this clock | |
686 | * @parent_name: name of clock's parent | |
687 | * @flags: framework-specific flags | |
688 | * @reg: register address to adjust divider | |
689 | * @shift: number of bits to shift the bitfield | |
690 | * @width: width of the bitfield | |
691 | * @clk_divider_flags: divider-specific flags for this clock | |
692 | * @lock: shared register lock for this clock | |
693 | */ | |
694 | #define clk_register_divider(dev, name, parent_name, flags, reg, shift, width, \ | |
695 | clk_divider_flags, lock) \ | |
696 | clk_register_divider_table((dev), (name), (parent_name), (flags), \ | |
697 | (reg), (shift), (width), \ | |
698 | (clk_divider_flags), NULL, (lock)) | |
699 | /** | |
700 | * clk_hw_register_divider - register a divider clock with the clock framework | |
701 | * @dev: device registering this clock | |
702 | * @name: name of this clock | |
703 | * @parent_name: name of clock's parent | |
704 | * @flags: framework-specific flags | |
705 | * @reg: register address to adjust divider | |
706 | * @shift: number of bits to shift the bitfield | |
707 | * @width: width of the bitfield | |
708 | * @clk_divider_flags: divider-specific flags for this clock | |
709 | * @lock: shared register lock for this clock | |
710 | */ | |
711 | #define clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \ | |
712 | width, clk_divider_flags, lock) \ | |
713 | __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \ | |
714 | NULL, (flags), (reg), (shift), (width), \ | |
715 | (clk_divider_flags), NULL, (lock)) | |
716 | /** | |
717 | * clk_hw_register_divider_parent_hw - register a divider clock with the clock | |
718 | * framework | |
719 | * @dev: device registering this clock | |
720 | * @name: name of this clock | |
721 | * @parent_hw: pointer to parent clk | |
722 | * @flags: framework-specific flags | |
723 | * @reg: register address to adjust divider | |
724 | * @shift: number of bits to shift the bitfield | |
725 | * @width: width of the bitfield | |
726 | * @clk_divider_flags: divider-specific flags for this clock | |
727 | * @lock: shared register lock for this clock | |
728 | */ | |
729 | #define clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, reg, \ | |
730 | shift, width, clk_divider_flags, \ | |
731 | lock) \ | |
732 | __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \ | |
733 | NULL, (flags), (reg), (shift), (width), \ | |
734 | (clk_divider_flags), NULL, (lock)) | |
735 | /** | |
736 | * clk_hw_register_divider_parent_data - register a divider clock with the clock | |
737 | * framework | |
738 | * @dev: device registering this clock | |
739 | * @name: name of this clock | |
740 | * @parent_data: parent clk data | |
741 | * @flags: framework-specific flags | |
742 | * @reg: register address to adjust divider | |
743 | * @shift: number of bits to shift the bitfield | |
744 | * @width: width of the bitfield | |
745 | * @clk_divider_flags: divider-specific flags for this clock | |
746 | * @lock: shared register lock for this clock | |
747 | */ | |
748 | #define clk_hw_register_divider_parent_data(dev, name, parent_data, flags, \ | |
749 | reg, shift, width, \ | |
750 | clk_divider_flags, lock) \ | |
751 | __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \ | |
752 | (parent_data), (flags), (reg), (shift), \ | |
753 | (width), (clk_divider_flags), NULL, (lock)) | |
754 | /** | |
755 | * clk_hw_register_divider_table - register a table based divider clock with | |
756 | * the clock framework | |
757 | * @dev: device registering this clock | |
758 | * @name: name of this clock | |
759 | * @parent_name: name of clock's parent | |
760 | * @flags: framework-specific flags | |
761 | * @reg: register address to adjust divider | |
762 | * @shift: number of bits to shift the bitfield | |
763 | * @width: width of the bitfield | |
764 | * @clk_divider_flags: divider-specific flags for this clock | |
765 | * @table: array of divider/value pairs ending with a div set to 0 | |
766 | * @lock: shared register lock for this clock | |
767 | */ | |
768 | #define clk_hw_register_divider_table(dev, name, parent_name, flags, reg, \ | |
769 | shift, width, clk_divider_flags, table, \ | |
770 | lock) \ | |
771 | __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \ | |
772 | NULL, (flags), (reg), (shift), (width), \ | |
773 | (clk_divider_flags), (table), (lock)) | |
774 | /** | |
775 | * clk_hw_register_divider_table_parent_hw - register a table based divider | |
776 | * clock with the clock framework | |
777 | * @dev: device registering this clock | |
778 | * @name: name of this clock | |
779 | * @parent_hw: pointer to parent clk | |
780 | * @flags: framework-specific flags | |
781 | * @reg: register address to adjust divider | |
782 | * @shift: number of bits to shift the bitfield | |
783 | * @width: width of the bitfield | |
784 | * @clk_divider_flags: divider-specific flags for this clock | |
785 | * @table: array of divider/value pairs ending with a div set to 0 | |
786 | * @lock: shared register lock for this clock | |
787 | */ | |
788 | #define clk_hw_register_divider_table_parent_hw(dev, name, parent_hw, flags, \ | |
789 | reg, shift, width, \ | |
790 | clk_divider_flags, table, \ | |
791 | lock) \ | |
792 | __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \ | |
793 | NULL, (flags), (reg), (shift), (width), \ | |
794 | (clk_divider_flags), (table), (lock)) | |
795 | /** | |
796 | * clk_hw_register_divider_table_parent_data - register a table based divider | |
797 | * clock with the clock framework | |
798 | * @dev: device registering this clock | |
799 | * @name: name of this clock | |
800 | * @parent_data: parent clk data | |
801 | * @flags: framework-specific flags | |
802 | * @reg: register address to adjust divider | |
803 | * @shift: number of bits to shift the bitfield | |
804 | * @width: width of the bitfield | |
805 | * @clk_divider_flags: divider-specific flags for this clock | |
806 | * @table: array of divider/value pairs ending with a div set to 0 | |
807 | * @lock: shared register lock for this clock | |
808 | */ | |
809 | #define clk_hw_register_divider_table_parent_data(dev, name, parent_data, \ | |
810 | flags, reg, shift, width, \ | |
811 | clk_divider_flags, table, \ | |
812 | lock) \ | |
813 | __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \ | |
814 | (parent_data), (flags), (reg), (shift), \ | |
815 | (width), (clk_divider_flags), (table), \ | |
816 | (lock)) | |
f4b43ac0 DB |
817 | /** |
818 | * devm_clk_hw_register_divider - register a divider clock with the clock framework | |
819 | * @dev: device registering this clock | |
820 | * @name: name of this clock | |
821 | * @parent_name: name of clock's parent | |
822 | * @flags: framework-specific flags | |
823 | * @reg: register address to adjust divider | |
824 | * @shift: number of bits to shift the bitfield | |
825 | * @width: width of the bitfield | |
826 | * @clk_divider_flags: divider-specific flags for this clock | |
827 | * @lock: shared register lock for this clock | |
828 | */ | |
829 | #define devm_clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \ | |
830 | width, clk_divider_flags, lock) \ | |
831 | __devm_clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \ | |
832 | NULL, (flags), (reg), (shift), (width), \ | |
833 | (clk_divider_flags), NULL, (lock)) | |
909fcb19 MS |
834 | /** |
835 | * devm_clk_hw_register_divider_parent_hw - register a divider clock with the clock framework | |
836 | * @dev: device registering this clock | |
837 | * @name: name of this clock | |
838 | * @parent_hw: pointer to parent clk | |
839 | * @flags: framework-specific flags | |
840 | * @reg: register address to adjust divider | |
841 | * @shift: number of bits to shift the bitfield | |
842 | * @width: width of the bitfield | |
843 | * @clk_divider_flags: divider-specific flags for this clock | |
844 | * @lock: shared register lock for this clock | |
845 | */ | |
846 | #define devm_clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, \ | |
847 | reg, shift, width, \ | |
848 | clk_divider_flags, lock) \ | |
849 | __devm_clk_hw_register_divider((dev), NULL, (name), NULL, \ | |
850 | (parent_hw), NULL, (flags), (reg), \ | |
851 | (shift), (width), (clk_divider_flags), \ | |
852 | NULL, (lock)) | |
26792699 MW |
853 | /** |
854 | * devm_clk_hw_register_divider_table - register a table based divider clock | |
855 | * with the clock framework (devres variant) | |
856 | * @dev: device registering this clock | |
857 | * @name: name of this clock | |
858 | * @parent_name: name of clock's parent | |
859 | * @flags: framework-specific flags | |
860 | * @reg: register address to adjust divider | |
861 | * @shift: number of bits to shift the bitfield | |
862 | * @width: width of the bitfield | |
863 | * @clk_divider_flags: divider-specific flags for this clock | |
864 | * @table: array of divider/value pairs ending with a div set to 0 | |
865 | * @lock: shared register lock for this clock | |
866 | */ | |
867 | #define devm_clk_hw_register_divider_table(dev, name, parent_name, flags, \ | |
868 | reg, shift, width, \ | |
869 | clk_divider_flags, table, lock) \ | |
870 | __devm_clk_hw_register_divider((dev), NULL, (name), (parent_name), \ | |
871 | NULL, NULL, (flags), (reg), (shift), \ | |
872 | (width), (clk_divider_flags), (table), \ | |
873 | (lock)) | |
ff258817 | 874 | |
4e3c021f | 875 | void clk_unregister_divider(struct clk *clk); |
eb7d264f | 876 | void clk_hw_unregister_divider(struct clk_hw *hw); |
9d9f78ed MT |
877 | |
878 | /** | |
879 | * struct clk_mux - multiplexer clock | |
880 | * | |
881 | * @hw: handle between common and hardware-specific interfaces | |
882 | * @reg: register controlling multiplexer | |
fe3f338f | 883 | * @table: array of register values corresponding to the parent index |
9d9f78ed | 884 | * @shift: shift to multiplexer bit field |
fe3f338f | 885 | * @mask: mask of mutliplexer bit field |
3566d40c | 886 | * @flags: hardware-specific flags |
9d9f78ed MT |
887 | * @lock: register lock |
888 | * | |
889 | * Clock with multiple selectable parents. Implements .get_parent, .set_parent | |
890 | * and .recalc_rate | |
891 | * | |
892 | * Flags: | |
893 | * CLK_MUX_INDEX_ONE - register index starts at 1, not 0 | |
1f73f31a | 894 | * CLK_MUX_INDEX_BIT - register index is a single bit (power of two) |
ba492e90 | 895 | * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this |
725b418b GU |
896 | * register, and mask of mux bits are in higher 16-bit of this register. |
897 | * While setting the mux bits, higher 16-bit should also be updated to | |
898 | * indicate changing mux bits. | |
31f6e870 SB |
899 | * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the |
900 | * .get_parent clk_op. | |
15a02c1f SB |
901 | * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired |
902 | * frequency. | |
3a727519 JG |
903 | * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for |
904 | * the mux register. Setting this flag makes the register accesses big | |
905 | * endian. | |
9d9f78ed MT |
906 | */ |
907 | struct clk_mux { | |
908 | struct clk_hw hw; | |
909 | void __iomem *reg; | |
891b7023 | 910 | const u32 *table; |
ce4f3313 | 911 | u32 mask; |
9d9f78ed | 912 | u8 shift; |
9d9f78ed MT |
913 | u8 flags; |
914 | spinlock_t *lock; | |
915 | }; | |
916 | ||
5fd9c05c GT |
917 | #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw) |
918 | ||
9d9f78ed MT |
919 | #define CLK_MUX_INDEX_ONE BIT(0) |
920 | #define CLK_MUX_INDEX_BIT BIT(1) | |
ba492e90 | 921 | #define CLK_MUX_HIWORD_MASK BIT(2) |
15a02c1f SB |
922 | #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */ |
923 | #define CLK_MUX_ROUND_CLOSEST BIT(4) | |
3a727519 | 924 | #define CLK_MUX_BIG_ENDIAN BIT(5) |
9d9f78ed | 925 | |
bffad66e | 926 | extern const struct clk_ops clk_mux_ops; |
c57acd14 | 927 | extern const struct clk_ops clk_mux_ro_ops; |
ce4f3313 | 928 | |
9611b3aa SB |
929 | struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np, |
930 | const char *name, u8 num_parents, | |
931 | const char * const *parent_names, | |
932 | const struct clk_hw **parent_hws, | |
933 | const struct clk_parent_data *parent_data, | |
934 | unsigned long flags, void __iomem *reg, u8 shift, u32 mask, | |
891b7023 | 935 | u8 clk_mux_flags, const u32 *table, spinlock_t *lock); |
b3084079 DB |
936 | struct clk_hw *__devm_clk_hw_register_mux(struct device *dev, struct device_node *np, |
937 | const char *name, u8 num_parents, | |
938 | const char * const *parent_names, | |
939 | const struct clk_hw **parent_hws, | |
940 | const struct clk_parent_data *parent_data, | |
941 | unsigned long flags, void __iomem *reg, u8 shift, u32 mask, | |
891b7023 | 942 | u8 clk_mux_flags, const u32 *table, spinlock_t *lock); |
9611b3aa | 943 | struct clk *clk_register_mux_table(struct device *dev, const char *name, |
264b3171 | 944 | const char * const *parent_names, u8 num_parents, |
9611b3aa | 945 | unsigned long flags, void __iomem *reg, u8 shift, u32 mask, |
891b7023 | 946 | u8 clk_mux_flags, const u32 *table, spinlock_t *lock); |
ce4f3313 | 947 | |
9611b3aa SB |
948 | #define clk_register_mux(dev, name, parent_names, num_parents, flags, reg, \ |
949 | shift, width, clk_mux_flags, lock) \ | |
950 | clk_register_mux_table((dev), (name), (parent_names), (num_parents), \ | |
951 | (flags), (reg), (shift), BIT((width)) - 1, \ | |
952 | (clk_mux_flags), NULL, (lock)) | |
953 | #define clk_hw_register_mux_table(dev, name, parent_names, num_parents, \ | |
954 | flags, reg, shift, mask, clk_mux_flags, \ | |
955 | table, lock) \ | |
956 | __clk_hw_register_mux((dev), NULL, (name), (num_parents), \ | |
957 | (parent_names), NULL, NULL, (flags), (reg), \ | |
958 | (shift), (mask), (clk_mux_flags), (table), \ | |
959 | (lock)) | |
960 | #define clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \ | |
961 | shift, width, clk_mux_flags, lock) \ | |
962 | __clk_hw_register_mux((dev), NULL, (name), (num_parents), \ | |
963 | (parent_names), NULL, NULL, (flags), (reg), \ | |
964 | (shift), BIT((width)) - 1, (clk_mux_flags), \ | |
965 | NULL, (lock)) | |
966 | #define clk_hw_register_mux_hws(dev, name, parent_hws, num_parents, flags, \ | |
967 | reg, shift, width, clk_mux_flags, lock) \ | |
968 | __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \ | |
969 | (parent_hws), NULL, (flags), (reg), (shift), \ | |
970 | BIT((width)) - 1, (clk_mux_flags), NULL, (lock)) | |
971 | #define clk_hw_register_mux_parent_data(dev, name, parent_data, num_parents, \ | |
972 | flags, reg, shift, width, \ | |
973 | clk_mux_flags, lock) \ | |
974 | __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \ | |
975 | (parent_data), (flags), (reg), (shift), \ | |
976 | BIT((width)) - 1, (clk_mux_flags), NULL, (lock)) | |
b3084079 DB |
977 | #define devm_clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \ |
978 | shift, width, clk_mux_flags, lock) \ | |
979 | __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), \ | |
980 | (parent_names), NULL, NULL, (flags), (reg), \ | |
981 | (shift), BIT((width)) - 1, (clk_mux_flags), \ | |
982 | NULL, (lock)) | |
df63af17 MS |
983 | #define devm_clk_hw_register_mux_parent_hws(dev, name, parent_hws, \ |
984 | num_parents, flags, reg, shift, \ | |
985 | width, clk_mux_flags, lock) \ | |
986 | __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \ | |
987 | (parent_hws), NULL, (flags), (reg), \ | |
988 | (shift), BIT((width)) - 1, \ | |
989 | (clk_mux_flags), NULL, (lock)) | |
9611b3aa | 990 | |
891b7023 | 991 | int clk_mux_val_to_index(struct clk_hw *hw, const u32 *table, unsigned int flags, |
77deb66d | 992 | unsigned int val); |
891b7023 | 993 | unsigned int clk_mux_index_to_val(const u32 *table, unsigned int flags, u8 index); |
77deb66d | 994 | |
4e3c021f | 995 | void clk_unregister_mux(struct clk *clk); |
264b3171 | 996 | void clk_hw_unregister_mux(struct clk_hw *hw); |
4e3c021f | 997 | |
79b16641 GC |
998 | void of_fixed_factor_clk_setup(struct device_node *node); |
999 | ||
f0948f59 SH |
1000 | /** |
1001 | * struct clk_fixed_factor - fixed multiplier and divider clock | |
1002 | * | |
1003 | * @hw: handle between common and hardware-specific interfaces | |
1004 | * @mult: multiplier | |
1005 | * @div: divider | |
1006 | * | |
1007 | * Clock with a fixed multiplier and divider. The output frequency is the | |
1008 | * parent clock rate divided by div and multiplied by mult. | |
1009 | * Implements .recalc_rate, .set_rate and .round_rate | |
1010 | */ | |
1011 | ||
1012 | struct clk_fixed_factor { | |
1013 | struct clk_hw hw; | |
1014 | unsigned int mult; | |
1015 | unsigned int div; | |
1016 | }; | |
1017 | ||
5fd9c05c GT |
1018 | #define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw) |
1019 | ||
3037e9ea | 1020 | extern const struct clk_ops clk_fixed_factor_ops; |
f0948f59 SH |
1021 | struct clk *clk_register_fixed_factor(struct device *dev, const char *name, |
1022 | const char *parent_name, unsigned long flags, | |
1023 | unsigned int mult, unsigned int div); | |
cbf9591f | 1024 | void clk_unregister_fixed_factor(struct clk *clk); |
0759ac8a SB |
1025 | struct clk_hw *clk_hw_register_fixed_factor(struct device *dev, |
1026 | const char *name, const char *parent_name, unsigned long flags, | |
1027 | unsigned int mult, unsigned int div); | |
1028 | void clk_hw_unregister_fixed_factor(struct clk_hw *hw); | |
0b9266d2 DP |
1029 | struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev, |
1030 | const char *name, const char *parent_name, unsigned long flags, | |
1031 | unsigned int mult, unsigned int div); | |
0c125f87 MV |
1032 | struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev, |
1033 | const char *name, unsigned int index, unsigned long flags, | |
1034 | unsigned int mult, unsigned int div); | |
6ebd5247 MS |
1035 | |
1036 | struct clk_hw *devm_clk_hw_register_fixed_factor_parent_hw(struct device *dev, | |
1037 | const char *name, const struct clk_hw *parent_hw, | |
1038 | unsigned long flags, unsigned int mult, unsigned int div); | |
1039 | ||
1040 | struct clk_hw *clk_hw_register_fixed_factor_parent_hw(struct device *dev, | |
1041 | const char *name, const struct clk_hw *parent_hw, | |
1042 | unsigned long flags, unsigned int mult, unsigned int div); | |
e2d0e90f HK |
1043 | /** |
1044 | * struct clk_fractional_divider - adjustable fractional divider clock | |
1045 | * | |
1046 | * @hw: handle between common and hardware-specific interfaces | |
1047 | * @reg: register containing the divider | |
1048 | * @mshift: shift to the numerator bit field | |
1049 | * @mwidth: width of the numerator bit field | |
1050 | * @nshift: shift to the denominator bit field | |
1051 | * @nwidth: width of the denominator bit field | |
1052 | * @lock: register lock | |
1053 | * | |
1054 | * Clock with adjustable fractional divider affecting its output frequency. | |
e983da27 D |
1055 | * |
1056 | * Flags: | |
1057 | * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator | |
1058 | * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED | |
1059 | * is set then the numerator and denominator are both the value read | |
1060 | * plus one. | |
58a2b4c9 JG |
1061 | * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are |
1062 | * used for the divider register. Setting this flag makes the register | |
1063 | * accesses big endian. | |
82f53f9e AS |
1064 | * CLK_FRAC_DIVIDER_POWER_OF_TWO_PS - By default the resulting fraction might |
1065 | * be saturated and the caller will get quite far from the good enough | |
1066 | * approximation. Instead the caller may require, by setting this flag, | |
1067 | * to shift left by a few bits in case, when the asked one is quite small | |
1068 | * to satisfy the desired range of denominator. It assumes that on the | |
1069 | * caller's side the power-of-two capable prescaler exists. | |
e2d0e90f | 1070 | */ |
e2d0e90f HK |
1071 | struct clk_fractional_divider { |
1072 | struct clk_hw hw; | |
1073 | void __iomem *reg; | |
1074 | u8 mshift; | |
934e2536 | 1075 | u8 mwidth; |
e2d0e90f HK |
1076 | u32 mmask; |
1077 | u8 nshift; | |
934e2536 | 1078 | u8 nwidth; |
e2d0e90f HK |
1079 | u32 nmask; |
1080 | u8 flags; | |
ec52e462 EZ |
1081 | void (*approximation)(struct clk_hw *hw, |
1082 | unsigned long rate, unsigned long *parent_rate, | |
1083 | unsigned long *m, unsigned long *n); | |
e2d0e90f HK |
1084 | spinlock_t *lock; |
1085 | }; | |
1086 | ||
5fd9c05c GT |
1087 | #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw) |
1088 | ||
e983da27 | 1089 | #define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0) |
58a2b4c9 | 1090 | #define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1) |
82f53f9e | 1091 | #define CLK_FRAC_DIVIDER_POWER_OF_TWO_PS BIT(2) |
e983da27 | 1092 | |
e2d0e90f HK |
1093 | struct clk *clk_register_fractional_divider(struct device *dev, |
1094 | const char *name, const char *parent_name, unsigned long flags, | |
1095 | void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, | |
1096 | u8 clk_divider_flags, spinlock_t *lock); | |
39b44cff SB |
1097 | struct clk_hw *clk_hw_register_fractional_divider(struct device *dev, |
1098 | const char *name, const char *parent_name, unsigned long flags, | |
1099 | void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, | |
1100 | u8 clk_divider_flags, spinlock_t *lock); | |
1101 | void clk_hw_unregister_fractional_divider(struct clk_hw *hw); | |
e2d0e90f | 1102 | |
f2e0a532 MR |
1103 | /** |
1104 | * struct clk_multiplier - adjustable multiplier clock | |
1105 | * | |
1106 | * @hw: handle between common and hardware-specific interfaces | |
1107 | * @reg: register containing the multiplier | |
1108 | * @shift: shift to the multiplier bit field | |
1109 | * @width: width of the multiplier bit field | |
1110 | * @lock: register lock | |
1111 | * | |
1112 | * Clock with an adjustable multiplier affecting its output frequency. | |
1113 | * Implements .recalc_rate, .set_rate and .round_rate | |
1114 | * | |
1115 | * Flags: | |
1116 | * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read | |
1117 | * from the register, with 0 being a valid value effectively | |
1118 | * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is | |
1119 | * set, then a null multiplier will be considered as a bypass, | |
1120 | * leaving the parent rate unmodified. | |
1121 | * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be | |
1122 | * rounded to the closest integer instead of the down one. | |
9427b71a JG |
1123 | * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are |
1124 | * used for the multiplier register. Setting this flag makes the register | |
1125 | * accesses big endian. | |
f2e0a532 MR |
1126 | */ |
1127 | struct clk_multiplier { | |
1128 | struct clk_hw hw; | |
1129 | void __iomem *reg; | |
1130 | u8 shift; | |
1131 | u8 width; | |
1132 | u8 flags; | |
1133 | spinlock_t *lock; | |
1134 | }; | |
1135 | ||
5fd9c05c GT |
1136 | #define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw) |
1137 | ||
edfa3784 | 1138 | #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0) |
f2e0a532 | 1139 | #define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1) |
edfa3784 | 1140 | #define CLK_MULTIPLIER_BIG_ENDIAN BIT(2) |
f2e0a532 MR |
1141 | |
1142 | extern const struct clk_ops clk_multiplier_ops; | |
1143 | ||
ece70094 PG |
1144 | /*** |
1145 | * struct clk_composite - aggregate clock of mux, divider and gate clocks | |
1146 | * | |
1147 | * @hw: handle between common and hardware-specific interfaces | |
d3a1c7be MT |
1148 | * @mux_hw: handle between composite and hardware-specific mux clock |
1149 | * @rate_hw: handle between composite and hardware-specific rate clock | |
1150 | * @gate_hw: handle between composite and hardware-specific gate clock | |
ece70094 | 1151 | * @mux_ops: clock ops for mux |
d3a1c7be | 1152 | * @rate_ops: clock ops for rate |
ece70094 PG |
1153 | * @gate_ops: clock ops for gate |
1154 | */ | |
1155 | struct clk_composite { | |
1156 | struct clk_hw hw; | |
1157 | struct clk_ops ops; | |
1158 | ||
1159 | struct clk_hw *mux_hw; | |
d3a1c7be | 1160 | struct clk_hw *rate_hw; |
ece70094 PG |
1161 | struct clk_hw *gate_hw; |
1162 | ||
1163 | const struct clk_ops *mux_ops; | |
d3a1c7be | 1164 | const struct clk_ops *rate_ops; |
ece70094 PG |
1165 | const struct clk_ops *gate_ops; |
1166 | }; | |
1167 | ||
5fd9c05c GT |
1168 | #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw) |
1169 | ||
ece70094 | 1170 | struct clk *clk_register_composite(struct device *dev, const char *name, |
2893c379 | 1171 | const char * const *parent_names, int num_parents, |
ece70094 | 1172 | struct clk_hw *mux_hw, const struct clk_ops *mux_ops, |
d3a1c7be | 1173 | struct clk_hw *rate_hw, const struct clk_ops *rate_ops, |
ece70094 PG |
1174 | struct clk_hw *gate_hw, const struct clk_ops *gate_ops, |
1175 | unsigned long flags); | |
73ef6572 MW |
1176 | struct clk *clk_register_composite_pdata(struct device *dev, const char *name, |
1177 | const struct clk_parent_data *parent_data, int num_parents, | |
1178 | struct clk_hw *mux_hw, const struct clk_ops *mux_ops, | |
1179 | struct clk_hw *rate_hw, const struct clk_ops *rate_ops, | |
1180 | struct clk_hw *gate_hw, const struct clk_ops *gate_ops, | |
1181 | unsigned long flags); | |
92a39d90 | 1182 | void clk_unregister_composite(struct clk *clk); |
49cb392d SB |
1183 | struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name, |
1184 | const char * const *parent_names, int num_parents, | |
1185 | struct clk_hw *mux_hw, const struct clk_ops *mux_ops, | |
1186 | struct clk_hw *rate_hw, const struct clk_ops *rate_ops, | |
1187 | struct clk_hw *gate_hw, const struct clk_ops *gate_ops, | |
1188 | unsigned long flags); | |
73ef6572 MW |
1189 | struct clk_hw *clk_hw_register_composite_pdata(struct device *dev, |
1190 | const char *name, | |
1191 | const struct clk_parent_data *parent_data, int num_parents, | |
49cb392d SB |
1192 | struct clk_hw *mux_hw, const struct clk_ops *mux_ops, |
1193 | struct clk_hw *rate_hw, const struct clk_ops *rate_ops, | |
1194 | struct clk_hw *gate_hw, const struct clk_ops *gate_ops, | |
1195 | unsigned long flags); | |
0eba7707 MW |
1196 | struct clk_hw *devm_clk_hw_register_composite_pdata(struct device *dev, |
1197 | const char *name, const struct clk_parent_data *parent_data, | |
1198 | int num_parents, | |
1199 | struct clk_hw *mux_hw, const struct clk_ops *mux_ops, | |
1200 | struct clk_hw *rate_hw, const struct clk_ops *rate_ops, | |
49cb392d SB |
1201 | struct clk_hw *gate_hw, const struct clk_ops *gate_ops, |
1202 | unsigned long flags); | |
1203 | void clk_hw_unregister_composite(struct clk_hw *hw); | |
ece70094 | 1204 | |
0197b3ea | 1205 | struct clk *clk_register(struct device *dev, struct clk_hw *hw); |
46c8773a | 1206 | struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw); |
b2476490 | 1207 | |
4143804c SB |
1208 | int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw); |
1209 | int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw); | |
89a5ddcc | 1210 | int __must_check of_clk_hw_register(struct device_node *node, struct clk_hw *hw); |
4143804c | 1211 | |
1df5c939 MB |
1212 | void clk_unregister(struct clk *clk); |
1213 | ||
4143804c | 1214 | void clk_hw_unregister(struct clk_hw *hw); |
4143804c | 1215 | |
b2476490 | 1216 | /* helper functions */ |
b76281cb | 1217 | const char *__clk_get_name(const struct clk *clk); |
e7df6f6e | 1218 | const char *clk_hw_get_name(const struct clk_hw *hw); |
1df37992 | 1219 | #ifdef CONFIG_COMMON_CLK |
b2476490 | 1220 | struct clk_hw *__clk_get_hw(struct clk *clk); |
1df37992 SR |
1221 | #else |
1222 | static inline struct clk_hw *__clk_get_hw(struct clk *clk) | |
1223 | { | |
1224 | return (struct clk_hw *)clk; | |
1225 | } | |
1226 | #endif | |
30d6f8c1 JB |
1227 | |
1228 | struct clk *clk_hw_get_clk(struct clk_hw *hw, const char *con_id); | |
1229 | struct clk *devm_clk_hw_get_clk(struct device *dev, struct clk_hw *hw, | |
1230 | const char *con_id); | |
1231 | ||
e7df6f6e SB |
1232 | unsigned int clk_hw_get_num_parents(const struct clk_hw *hw); |
1233 | struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw); | |
1234 | struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw, | |
1a9c069c | 1235 | unsigned int index); |
d9b86cc4 | 1236 | int clk_hw_get_parent_index(struct clk_hw *hw); |
3567894b | 1237 | int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *new_parent); |
93874681 | 1238 | unsigned int __clk_get_enable_count(struct clk *clk); |
e7df6f6e | 1239 | unsigned long clk_hw_get_rate(const struct clk_hw *hw); |
e7df6f6e | 1240 | unsigned long clk_hw_get_flags(const struct clk_hw *hw); |
d13501a2 KS |
1241 | #define clk_hw_can_set_rate_parent(hw) \ |
1242 | (clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT) | |
1243 | ||
e7df6f6e | 1244 | bool clk_hw_is_prepared(const struct clk_hw *hw); |
e55a839a | 1245 | bool clk_hw_rate_is_protected(const struct clk_hw *hw); |
be68bf88 | 1246 | bool clk_hw_is_enabled(const struct clk_hw *hw); |
2ac6b1f5 | 1247 | bool __clk_is_enabled(struct clk *clk); |
b2476490 | 1248 | struct clk *__clk_lookup(const char *name); |
0817b62c BB |
1249 | int __clk_mux_determine_rate(struct clk_hw *hw, |
1250 | struct clk_rate_request *req); | |
1251 | int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req); | |
1252 | int __clk_mux_determine_rate_closest(struct clk_hw *hw, | |
1253 | struct clk_rate_request *req); | |
4ad69b80 JB |
1254 | int clk_mux_determine_rate_flags(struct clk_hw *hw, |
1255 | struct clk_rate_request *req, | |
1256 | unsigned long flags); | |
42c86547 | 1257 | void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent); |
9783c0d9 SB |
1258 | void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate, |
1259 | unsigned long max_rate); | |
b2476490 | 1260 | |
2e65d8bf JMC |
1261 | static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src) |
1262 | { | |
1263 | dst->clk = src->clk; | |
1264 | dst->core = src->core; | |
1265 | } | |
1266 | ||
22833a91 MR |
1267 | static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate, |
1268 | unsigned long *prate, | |
1269 | const struct clk_div_table *table, | |
1270 | u8 width, unsigned long flags) | |
1271 | { | |
1272 | return divider_round_rate_parent(hw, clk_hw_get_parent(hw), | |
1273 | rate, prate, table, width, flags); | |
1274 | } | |
1275 | ||
b15ee490 JB |
1276 | static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate, |
1277 | unsigned long *prate, | |
1278 | const struct clk_div_table *table, | |
1279 | u8 width, unsigned long flags, | |
1280 | unsigned int val) | |
1281 | { | |
1282 | return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw), | |
1283 | rate, prate, table, width, flags, | |
1284 | val); | |
1285 | } | |
1286 | ||
b2476490 MT |
1287 | /* |
1288 | * FIXME clock api without lock protection | |
1289 | */ | |
1a9c069c | 1290 | unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate); |
b2476490 | 1291 | |
0b151deb SH |
1292 | struct clk_onecell_data { |
1293 | struct clk **clks; | |
1294 | unsigned int clk_num; | |
1295 | }; | |
1296 | ||
0861e5b8 | 1297 | struct clk_hw_onecell_data { |
5963f19c | 1298 | unsigned int num; |
0861e5b8 SB |
1299 | struct clk_hw *hws[]; |
1300 | }; | |
1301 | ||
54196ccb | 1302 | #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn) |
0b151deb | 1303 | |
c7296c51 RRD |
1304 | /* |
1305 | * Use this macro when you have a driver that requires two initialization | |
1306 | * routines, one at of_clk_init(), and one at platform device probe | |
1307 | */ | |
1308 | #define CLK_OF_DECLARE_DRIVER(name, compat, fn) \ | |
339e1e54 | 1309 | static void __init name##_of_clk_init_driver(struct device_node *np) \ |
c7296c51 RRD |
1310 | { \ |
1311 | of_node_clear_flag(np, OF_POPULATED); \ | |
1312 | fn(np); \ | |
1313 | } \ | |
1314 | OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver) | |
1315 | ||
1ded879e CZ |
1316 | #define CLK_HW_INIT(_name, _parent, _ops, _flags) \ |
1317 | (&(struct clk_init_data) { \ | |
1318 | .flags = _flags, \ | |
1319 | .name = _name, \ | |
1320 | .parent_names = (const char *[]) { _parent }, \ | |
1321 | .num_parents = 1, \ | |
1322 | .ops = _ops, \ | |
1323 | }) | |
1324 | ||
99600fd4 CYT |
1325 | #define CLK_HW_INIT_HW(_name, _parent, _ops, _flags) \ |
1326 | (&(struct clk_init_data) { \ | |
1327 | .flags = _flags, \ | |
1328 | .name = _name, \ | |
1329 | .parent_hws = (const struct clk_hw*[]) { _parent }, \ | |
1330 | .num_parents = 1, \ | |
1331 | .ops = _ops, \ | |
1332 | }) | |
1333 | ||
1334 | /* | |
1335 | * This macro is intended for drivers to be able to share the otherwise | |
1336 | * individual struct clk_hw[] compound literals created by the compiler | |
1337 | * when using CLK_HW_INIT_HW. It does NOT support multiple parents. | |
1338 | */ | |
1339 | #define CLK_HW_INIT_HWS(_name, _parent, _ops, _flags) \ | |
1340 | (&(struct clk_init_data) { \ | |
1341 | .flags = _flags, \ | |
1342 | .name = _name, \ | |
1343 | .parent_hws = _parent, \ | |
1344 | .num_parents = 1, \ | |
1345 | .ops = _ops, \ | |
1346 | }) | |
1347 | ||
2d6b4f33 CYT |
1348 | #define CLK_HW_INIT_FW_NAME(_name, _parent, _ops, _flags) \ |
1349 | (&(struct clk_init_data) { \ | |
1350 | .flags = _flags, \ | |
1351 | .name = _name, \ | |
1352 | .parent_data = (const struct clk_parent_data[]) { \ | |
1353 | { .fw_name = _parent }, \ | |
1354 | }, \ | |
1355 | .num_parents = 1, \ | |
1356 | .ops = _ops, \ | |
1357 | }) | |
1358 | ||
1ded879e CZ |
1359 | #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \ |
1360 | (&(struct clk_init_data) { \ | |
1361 | .flags = _flags, \ | |
1362 | .name = _name, \ | |
1363 | .parent_names = _parents, \ | |
1364 | .num_parents = ARRAY_SIZE(_parents), \ | |
1365 | .ops = _ops, \ | |
1366 | }) | |
1367 | ||
99600fd4 CYT |
1368 | #define CLK_HW_INIT_PARENTS_HW(_name, _parents, _ops, _flags) \ |
1369 | (&(struct clk_init_data) { \ | |
1370 | .flags = _flags, \ | |
1371 | .name = _name, \ | |
1372 | .parent_hws = _parents, \ | |
1373 | .num_parents = ARRAY_SIZE(_parents), \ | |
1374 | .ops = _ops, \ | |
1375 | }) | |
1376 | ||
13933109 CYT |
1377 | #define CLK_HW_INIT_PARENTS_DATA(_name, _parents, _ops, _flags) \ |
1378 | (&(struct clk_init_data) { \ | |
1379 | .flags = _flags, \ | |
1380 | .name = _name, \ | |
1381 | .parent_data = _parents, \ | |
1382 | .num_parents = ARRAY_SIZE(_parents), \ | |
1383 | .ops = _ops, \ | |
1384 | }) | |
1385 | ||
1ded879e CZ |
1386 | #define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \ |
1387 | (&(struct clk_init_data) { \ | |
1388 | .flags = _flags, \ | |
1389 | .name = _name, \ | |
1390 | .parent_names = NULL, \ | |
1391 | .num_parents = 0, \ | |
1392 | .ops = _ops, \ | |
1393 | }) | |
1394 | ||
1395 | #define CLK_FIXED_FACTOR(_struct, _name, _parent, \ | |
1396 | _div, _mult, _flags) \ | |
1397 | struct clk_fixed_factor _struct = { \ | |
1398 | .div = _div, \ | |
1399 | .mult = _mult, \ | |
1400 | .hw.init = CLK_HW_INIT(_name, \ | |
1401 | _parent, \ | |
1402 | &clk_fixed_factor_ops, \ | |
1403 | _flags), \ | |
1404 | } | |
1405 | ||
d7b15114 CYT |
1406 | #define CLK_FIXED_FACTOR_HW(_struct, _name, _parent, \ |
1407 | _div, _mult, _flags) \ | |
1408 | struct clk_fixed_factor _struct = { \ | |
1409 | .div = _div, \ | |
1410 | .mult = _mult, \ | |
1411 | .hw.init = CLK_HW_INIT_HW(_name, \ | |
1412 | _parent, \ | |
1413 | &clk_fixed_factor_ops, \ | |
1414 | _flags), \ | |
1415 | } | |
1416 | ||
1bef004e CYT |
1417 | /* |
1418 | * This macro allows the driver to reuse the _parent array for multiple | |
1419 | * fixed factor clk declarations. | |
1420 | */ | |
1421 | #define CLK_FIXED_FACTOR_HWS(_struct, _name, _parent, \ | |
1422 | _div, _mult, _flags) \ | |
1423 | struct clk_fixed_factor _struct = { \ | |
1424 | .div = _div, \ | |
1425 | .mult = _mult, \ | |
1426 | .hw.init = CLK_HW_INIT_HWS(_name, \ | |
1427 | _parent, \ | |
1428 | &clk_fixed_factor_ops, \ | |
1429 | _flags), \ | |
1430 | } | |
1431 | ||
8b13a48b CYT |
1432 | #define CLK_FIXED_FACTOR_FW_NAME(_struct, _name, _parent, \ |
1433 | _div, _mult, _flags) \ | |
1434 | struct clk_fixed_factor _struct = { \ | |
1435 | .div = _div, \ | |
1436 | .mult = _mult, \ | |
1437 | .hw.init = CLK_HW_INIT_FW_NAME(_name, \ | |
1438 | _parent, \ | |
1439 | &clk_fixed_factor_ops, \ | |
1440 | _flags), \ | |
1441 | } | |
1442 | ||
0b151deb | 1443 | #ifdef CONFIG_OF |
766e6a4e GL |
1444 | int of_clk_add_provider(struct device_node *np, |
1445 | struct clk *(*clk_src_get)(struct of_phandle_args *args, | |
1446 | void *data), | |
1447 | void *data); | |
0861e5b8 SB |
1448 | int of_clk_add_hw_provider(struct device_node *np, |
1449 | struct clk_hw *(*get)(struct of_phandle_args *clkspec, | |
1450 | void *data), | |
1451 | void *data); | |
aa795c41 SB |
1452 | int devm_of_clk_add_hw_provider(struct device *dev, |
1453 | struct clk_hw *(*get)(struct of_phandle_args *clkspec, | |
1454 | void *data), | |
1455 | void *data); | |
766e6a4e | 1456 | void of_clk_del_provider(struct device_node *np); |
aa795c41 | 1457 | void devm_of_clk_del_provider(struct device *dev); |
766e6a4e GL |
1458 | struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, |
1459 | void *data); | |
0861e5b8 SB |
1460 | struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec, |
1461 | void *data); | |
494bfec9 | 1462 | struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data); |
0861e5b8 SB |
1463 | struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec, |
1464 | void *data); | |
2e61dfb3 DN |
1465 | int of_clk_parent_fill(struct device_node *np, const char **parents, |
1466 | unsigned int size); | |
d56f8994 LJ |
1467 | int of_clk_detect_critical(struct device_node *np, int index, |
1468 | unsigned long *flags); | |
766e6a4e | 1469 | |
0b151deb | 1470 | #else /* !CONFIG_OF */ |
f2f6c255 | 1471 | |
0b151deb SH |
1472 | static inline int of_clk_add_provider(struct device_node *np, |
1473 | struct clk *(*clk_src_get)(struct of_phandle_args *args, | |
1474 | void *data), | |
1475 | void *data) | |
1476 | { | |
1477 | return 0; | |
1478 | } | |
0861e5b8 SB |
1479 | static inline int of_clk_add_hw_provider(struct device_node *np, |
1480 | struct clk_hw *(*get)(struct of_phandle_args *clkspec, | |
1481 | void *data), | |
1482 | void *data) | |
1483 | { | |
1484 | return 0; | |
1485 | } | |
aa795c41 SB |
1486 | static inline int devm_of_clk_add_hw_provider(struct device *dev, |
1487 | struct clk_hw *(*get)(struct of_phandle_args *clkspec, | |
1488 | void *data), | |
1489 | void *data) | |
1490 | { | |
1491 | return 0; | |
1492 | } | |
20dd882a | 1493 | static inline void of_clk_del_provider(struct device_node *np) {} |
aa795c41 | 1494 | static inline void devm_of_clk_del_provider(struct device *dev) {} |
0b151deb SH |
1495 | static inline struct clk *of_clk_src_simple_get( |
1496 | struct of_phandle_args *clkspec, void *data) | |
1497 | { | |
1498 | return ERR_PTR(-ENOENT); | |
1499 | } | |
0861e5b8 SB |
1500 | static inline struct clk_hw * |
1501 | of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data) | |
1502 | { | |
1503 | return ERR_PTR(-ENOENT); | |
1504 | } | |
0b151deb SH |
1505 | static inline struct clk *of_clk_src_onecell_get( |
1506 | struct of_phandle_args *clkspec, void *data) | |
1507 | { | |
1508 | return ERR_PTR(-ENOENT); | |
1509 | } | |
0861e5b8 SB |
1510 | static inline struct clk_hw * |
1511 | of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data) | |
1512 | { | |
1513 | return ERR_PTR(-ENOENT); | |
1514 | } | |
679c51cf SB |
1515 | static inline int of_clk_parent_fill(struct device_node *np, |
1516 | const char **parents, unsigned int size) | |
1517 | { | |
1518 | return 0; | |
1519 | } | |
d56f8994 LJ |
1520 | static inline int of_clk_detect_critical(struct device_node *np, int index, |
1521 | unsigned long *flags) | |
1522 | { | |
1523 | return 0; | |
1524 | } | |
0b151deb | 1525 | #endif /* CONFIG_OF */ |
aa514ce3 | 1526 | |
43536548 K |
1527 | void clk_gate_restore_context(struct clk_hw *hw); |
1528 | ||
b2476490 | 1529 | #endif /* CLK_PROVIDER_H */ |