[linux-2.6-block.git] / include / linux / clk / at91_pmc.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * include/linux/clk/at91_pmc.h
 *
 * Copyright (C) 2005 Ivan Kokshaysky
 * Copyright (C) SAN People
 *
 * Power Management Controller (PMC) - System peripherals registers.
 * Based on AT91RM9200 datasheet revision E.
 */

#ifndef AT91_PMC_H
#define AT91_PMC_H

#define AT91_PMC_V1		(1)			/* PMC version 1 */
#define AT91_PMC_V2		(2)			/* PMC version 2 [SAM9X60] */

#define	AT91_PMC_SCER		0x00			/* System Clock Enable Register */
#define	AT91_PMC_SCDR		0x04			/* System Clock Disable Register */

#define	AT91_PMC_SCSR		0x08			/* System Clock Status Register */
#define		AT91_PMC_PCK		(1 <<  0)		/* Processor Clock */
#define		AT91RM9200_PMC_UDP	(1 <<  1)		/* USB Devcice Port Clock [AT91RM9200 only] */
#define		AT91RM9200_PMC_MCKUDP	(1 <<  2)		/* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
#define		AT91RM9200_PMC_UHP	(1 <<  4)		/* USB Host Port Clock [AT91RM9200 only] */
#define		AT91SAM926x_PMC_UHP	(1 <<  6)		/* USB Host Port Clock [AT91SAM926x only] */
#define		AT91SAM926x_PMC_UDP	(1 <<  7)		/* USB Devcice Port Clock [AT91SAM926x only] */
#define		AT91_PMC_PCK0		(1 <<  8)		/* Programmable Clock 0 */
#define		AT91_PMC_PCK1		(1 <<  9)		/* Programmable Clock 1 */
#define		AT91_PMC_PCK2		(1 << 10)		/* Programmable Clock 2 */
#define		AT91_PMC_PCK3		(1 << 11)		/* Programmable Clock 3 */
#define		AT91_PMC_PCK4		(1 << 12)		/* Programmable Clock 4 [AT572D940HF only] */
#define		AT91_PMC_HCK0		(1 << 16)		/* AHB Clock (USB host) [AT91SAM9261 only] */
#define		AT91_PMC_HCK1		(1 << 17)		/* AHB Clock (LCD) [AT91SAM9261 only] */

#define AT91_PMC_PLL_CTRL0		0x0C		/* PLL Control Register 0 [for SAM9X60] */
#define		AT91_PMC_PLL_CTRL0_ENPLL	(1 << 28)	/* Enable PLL */
#define		AT91_PMC_PLL_CTRL0_ENPLLCK	(1 << 29)	/* Enable PLL clock for PMC */
#define		AT91_PMC_PLL_CTRL0_ENLOCK	(1 << 31)	/* Enable PLL lock */

#define AT91_PMC_PLL_CTRL1		0x10		/* PLL Control Register 1 [for SAM9X60] */

#define	AT91_PMC_PCER		0x10			/* Peripheral Clock Enable Register */
#define	AT91_PMC_PCDR		0x14			/* Peripheral Clock Disable Register */
#define	AT91_PMC_PCSR		0x18			/* Peripheral Clock Status Register */

#define AT91_PMC_PLL_ACR	0x18			/* PLL Analog Control Register [for SAM9X60] */
#define		AT91_PMC_PLL_ACR_DEFAULT_UPLL	0x12020010UL	/* Default PLL ACR value for UPLL */
#define		AT91_PMC_PLL_ACR_DEFAULT_PLLA	0x00020010UL	/* Default PLL ACR value for PLLA */
#define		AT91_PMC_PLL_ACR_UTMIVR		(1 << 12)	/* UPLL Voltage regulator Control */
#define		AT91_PMC_PLL_ACR_UTMIBG		(1 << 13)	/* UPLL Bandgap Control */

#define	AT91_CKGR_UCKR		0x1C			/* UTMI Clock Register [some SAM9] */
#define		AT91_PMC_UPLLEN		(1   << 16)		/* UTMI PLL Enable */
#define		AT91_PMC_UPLLCOUNT	(0xf << 20)		/* UTMI PLL Start-up Time */
#define		AT91_PMC_BIASEN		(1   << 24)		/* UTMI BIAS Enable */
#define		AT91_PMC_BIASCOUNT	(0xf << 28)		/* UTMI BIAS Start-up Time */

#define AT91_PMC_PLL_UPDT		0x1C		/* PMC PLL update register [for SAM9X60] */
#define		AT91_PMC_PLL_UPDT_UPDATE	(1 << 8)	/* Update PLL settings */
#define		AT91_PMC_PLL_UPDT_ID		(1 << 0)	/* PLL ID */
#define		AT91_PMC_PLL_UPDT_ID_MSK	(0xf)		/* PLL ID mask */
#define		AT91_PMC_PLL_UPDT_STUPTIM	(0xff << 16)	/* Startup time */

#define	AT91_CKGR_MOR		0x20			/* Main Oscillator Register [not on SAM9RL] */
#define		AT91_PMC_MOSCEN		(1    <<  0)		/* Main Oscillator Enable */
#define		AT91_PMC_OSCBYPASS	(1    <<  1)		/* Oscillator Bypass */
#define		AT91_PMC_WAITMODE	(1    <<  2)		/* Wait Mode Command */
#define		AT91_PMC_MOSCRCEN	(1    <<  3)		/* Main On-Chip RC Oscillator Enable [some SAM9] */
#define		AT91_PMC_OSCOUNT	(0xff <<  8)		/* Main Oscillator Start-up Time */
#define		AT91_PMC_KEY_MASK	(0xff << 16)
#define		AT91_PMC_KEY		(0x37 << 16)		/* MOR Writing Key */
#define		AT91_PMC_MOSCSEL	(1    << 24)		/* Main Oscillator Selection [some SAM9] */
#define		AT91_PMC_CFDEN		(1    << 25)		/* Clock Failure Detector Enable [some SAM9] */

#define	AT91_CKGR_MCFR		0x24			/* Main Clock Frequency Register */
#define		AT91_PMC_MAINF		(0xffff <<  0)		/* Main Clock Frequency */
#define		AT91_PMC_MAINRDY	(1	<< 16)		/* Main Clock Ready */

#define	AT91_CKGR_PLLAR		0x28			/* PLL A Register */

#define	AT91_PMC_RATIO		0x2c			/* Processor clock ratio register [SAMA7G5 only] */
#define		AT91_PMC_RATIO_RATIO	(0xf)		/* CPU clock ratio. */

#define	AT91_CKGR_PLLBR		0x2c			/* PLL B Register */
#define		AT91_PMC_DIV		(0xff  <<  0)		/* Divider */
#define		AT91_PMC_PLLCOUNT	(0x3f  <<  8)		/* PLL Counter */
#define		AT91_PMC_OUT		(3     << 14)		/* PLL Clock Frequency Range */
#define		AT91_PMC_MUL		(0x7ff << 16)		/* PLL Multiplier */
#define		AT91_PMC_MUL_GET(n)	((n) >> 16 & 0x7ff)
#define		AT91_PMC3_MUL		(0x7f  << 18)		/* PLL Multiplier [SAMA5 only] */
#define		AT91_PMC3_MUL_GET(n)	((n) >> 18 & 0x7f)
#define		AT91_PMC_USBDIV		(3     << 28)		/* USB Divisor (PLLB only) */
#define			AT91_PMC_USBDIV_1		(0 << 28)
#define			AT91_PMC_USBDIV_2		(1 << 28)
#define			AT91_PMC_USBDIV_4		(2 << 28)
#define		AT91_PMC_USB96M		(1     << 28)		/* Divider by 2 Enable (PLLB only) */

#define AT91_PMC_CPU_CKR	0x28			/* CPU Clock Register */

#define	AT91_PMC_MCKR		0x30			/* Master Clock Register */
#define		AT91_PMC_CSS		(3 <<  0)		/* Master Clock Selection */
#define			AT91_PMC_CSS_SLOW		(0 << 0)
#define			AT91_PMC_CSS_MAIN		(1 << 0)
#define			AT91_PMC_CSS_PLLA		(2 << 0)
#define			AT91_PMC_CSS_PLLB		(3 << 0)
#define			AT91_PMC_CSS_UPLL		(3 << 0)	/* [some SAM9 only] */
#define		PMC_PRES_OFFSET		2
#define		AT91_PMC_PRES		(7 <<  PMC_PRES_OFFSET)		/* Master Clock Prescaler */
#define			AT91_PMC_PRES_1			(0 << PMC_PRES_OFFSET)
#define			AT91_PMC_PRES_2			(1 << PMC_PRES_OFFSET)
#define			AT91_PMC_PRES_4			(2 << PMC_PRES_OFFSET)
#define			AT91_PMC_PRES_8			(3 << PMC_PRES_OFFSET)
#define			AT91_PMC_PRES_16		(4 << PMC_PRES_OFFSET)
#define			AT91_PMC_PRES_32		(5 << PMC_PRES_OFFSET)
#define			AT91_PMC_PRES_64		(6 << PMC_PRES_OFFSET)
#define		PMC_ALT_PRES_OFFSET	4
#define		AT91_PMC_ALT_PRES	(7 <<  PMC_ALT_PRES_OFFSET)		/* Master Clock Prescaler [alternate location] */
#define			AT91_PMC_ALT_PRES_1		(0 << PMC_ALT_PRES_OFFSET)
#define			AT91_PMC_ALT_PRES_2		(1 << PMC_ALT_PRES_OFFSET)
#define			AT91_PMC_ALT_PRES_4		(2 << PMC_ALT_PRES_OFFSET)
#define			AT91_PMC_ALT_PRES_8		(3 << PMC_ALT_PRES_OFFSET)
#define			AT91_PMC_ALT_PRES_16		(4 << PMC_ALT_PRES_OFFSET)
#define			AT91_PMC_ALT_PRES_32		(5 << PMC_ALT_PRES_OFFSET)
#define			AT91_PMC_ALT_PRES_64		(6 << PMC_ALT_PRES_OFFSET)
#define		AT91_PMC_MDIV		(3 <<  8)		/* Master Clock Division */
#define			AT91RM9200_PMC_MDIV_1		(0 << 8)	/* [AT91RM9200 only] */
#define			AT91RM9200_PMC_MDIV_2		(1 << 8)
#define			AT91RM9200_PMC_MDIV_3		(2 << 8)
#define			AT91RM9200_PMC_MDIV_4		(3 << 8)
#define			AT91SAM9_PMC_MDIV_1		(0 << 8)	/* [SAM9 only] */
#define			AT91SAM9_PMC_MDIV_2		(1 << 8)
#define			AT91SAM9_PMC_MDIV_4		(2 << 8)
#define			AT91SAM9_PMC_MDIV_6		(3 << 8)	/* [some SAM9 only] */
#define			AT91SAM9_PMC_MDIV_3		(3 << 8)	/* [some SAM9 only] */
#define		AT91_PMC_PDIV		(1 << 12)		/* Processor Clock Division [some SAM9 only] */
#define			AT91_PMC_PDIV_1			(0 << 12)
#define			AT91_PMC_PDIV_2			(1 << 12)
#define		AT91_PMC_PLLADIV2	(1 << 12)		/* PLLA divisor by 2 [some SAM9 only] */
#define			AT91_PMC_PLLADIV2_OFF		(0 << 12)
#define			AT91_PMC_PLLADIV2_ON		(1 << 12)
#define		AT91_PMC_H32MXDIV	BIT(24)

#define	AT91_PMC_MCR_V2		0x30				/* Master Clock Register [SAMA7G5 only] */
#define		AT91_PMC_MCR_V2_ID_MSK	(0xF)
#define			AT91_PMC_MCR_V2_ID(_id)		((_id) & AT91_PMC_MCR_V2_ID_MSK)
#define		AT91_PMC_MCR_V2_CMD	(1 << 7)
#define		AT91_PMC_MCR_V2_DIV	(7 << 8)
#define			AT91_PMC_MCR_V2_DIV1		(0 << 8)
#define			AT91_PMC_MCR_V2_DIV2		(1 << 8)
#define			AT91_PMC_MCR_V2_DIV4		(2 << 8)
#define			AT91_PMC_MCR_V2_DIV8		(3 << 8)
#define			AT91_PMC_MCR_V2_DIV16		(4 << 8)
#define			AT91_PMC_MCR_V2_DIV32		(5 << 8)
#define			AT91_PMC_MCR_V2_DIV64		(6 << 8)
#define			AT91_PMC_MCR_V2_DIV3		(7 << 8)
#define		AT91_PMC_MCR_V2_CSS	(0x1F << 16)
#define			AT91_PMC_MCR_V2_CSS_MD_SLCK	(0 << 16)
#define			AT91_PMC_MCR_V2_CSS_TD_SLCK	(1 << 16)
#define			AT91_PMC_MCR_V2_CSS_MAINCK	(2 << 16)
#define			AT91_PMC_MCR_V2_CSS_MCK0	(3 << 16)
#define			AT91_PMC_MCR_V2_CSS_SYSPLL	(5 << 16)
#define			AT91_PMC_MCR_V2_CSS_DDRPLL	(6 << 16)
#define			AT91_PMC_MCR_V2_CSS_IMGPLL	(7 << 16)
#define			AT91_PMC_MCR_V2_CSS_BAUDPLL	(8 << 16)
#define			AT91_PMC_MCR_V2_CSS_AUDIOPLL	(9 << 16)
#define			AT91_PMC_MCR_V2_CSS_ETHPLL	(10 << 16)
#define		AT91_PMC_MCR_V2_EN	(1 << 28)

#define AT91_PMC_XTALF		0x34			/* Main XTAL Frequency Register [SAMA7G5 only] */

#define	AT91_PMC_USB		0x38			/* USB Clock Register [some SAM9 only] */
#define		AT91_PMC_USBS		(0x1 <<  0)		/* USB OHCI Input clock selection */
#define			AT91_PMC_USBS_PLLA		(0 << 0)
#define			AT91_PMC_USBS_UPLL		(1 << 0)
#define			AT91_PMC_USBS_PLLB		(1 << 0)	/* [AT91SAMN12 only] */
#define		AT91_PMC_OHCIUSBDIV	(0xF <<  8)		/* Divider for USB OHCI Clock */
#define			AT91_PMC_OHCIUSBDIV_1	(0x0 <<  8)
#define			AT91_PMC_OHCIUSBDIV_2	(0x1 <<  8)

#define	AT91_PMC_SMD		0x3c			/* Soft Modem Clock Register [some SAM9 only] */
#define		AT91_PMC_SMDS		(0x1  <<  0)		/* SMD input clock selection */
#define		AT91_PMC_SMD_DIV	(0x1f <<  8)		/* SMD input clock divider */
#define		AT91_PMC_SMDDIV(n)	(((n) <<  8) & AT91_PMC_SMD_DIV)

#define	AT91_PMC_PCKR(n)	(0x40 + ((n) * 4))	/* Programmable Clock 0-N Registers */
#define		AT91_PMC_ALT_PCKR_CSS	(0x7 <<  0)		/* Programmable Clock Source Selection [alternate length] */
#define			AT91_PMC_CSS_MASTER		(4 << 0)	/* [some SAM9 only] */
#define		AT91_PMC_CSSMCK		(0x1 <<  8)		/* CSS or Master Clock Selection */
#define			AT91_PMC_CSSMCK_CSS		(0 << 8)
#define			AT91_PMC_CSSMCK_MCK		(1 << 8)

#define	AT91_PMC_IER		0x60			/* Interrupt Enable Register */
#define	AT91_PMC_IDR		0x64			/* Interrupt Disable Register */
#define	AT91_PMC_SR		0x68			/* Status Register */
#define		AT91_PMC_MOSCS		(1 <<  0)		/* MOSCS Flag */
#define		AT91_PMC_LOCKA		(1 <<  1)		/* PLLA Lock */
#define		AT91_PMC_LOCKB		(1 <<  2)		/* PLLB Lock */
#define		AT91_PMC_MCKRDY		(1 <<  3)		/* Master Clock */
#define		AT91_PMC_LOCKU		(1 <<  6)		/* UPLL Lock [some SAM9] */
#define		AT91_PMC_OSCSEL		(1 <<  7)		/* Slow Oscillator Selection [some SAM9] */
#define		AT91_PMC_PCK0RDY	(1 <<  8)		/* Programmable Clock 0 */
#define		AT91_PMC_PCK1RDY	(1 <<  9)		/* Programmable Clock 1 */
#define		AT91_PMC_PCK2RDY	(1 << 10)		/* Programmable Clock 2 */
#define		AT91_PMC_PCK3RDY	(1 << 11)		/* Programmable Clock 3 */
#define		AT91_PMC_MOSCSELS	(1 << 16)		/* Main Oscillator Selection [some SAM9] */
#define		AT91_PMC_MOSCRCS	(1 << 17)		/* Main On-Chip RC [some SAM9] */
#define		AT91_PMC_CFDEV		(1 << 18)		/* Clock Failure Detector Event [some SAM9] */
#define		AT91_PMC_GCKRDY		(1 << 24)		/* Generated Clocks */
#define		AT91_PMC_MCKXRDY	(1 << 26)		/* Master Clock x [x=1..4] Ready Status */
#define	AT91_PMC_IMR		0x6c			/* Interrupt Mask Register */

#define AT91_PMC_FSMR		0x70		/* Fast Startup Mode Register */
#define AT91_PMC_FSTT(n)	BIT(n)
#define AT91_PMC_RTTAL		BIT(16)
#define AT91_PMC_RTCAL		BIT(17)		/* RTC Alarm Enable */
#define AT91_PMC_USBAL		BIT(18)		/* USB Resume Enable */
#define AT91_PMC_SDMMC_CD	BIT(19)		/* SDMMC Card Detect Enable */
#define AT91_PMC_LPM		BIT(20)		/* Low-power Mode */
#define AT91_PMC_RXLP_MCE	BIT(24)		/* Backup UART Receive Enable */
#define AT91_PMC_ACC_CE		BIT(25)		/* ACC Enable */

#define AT91_PMC_FSPR		0x74		/* Fast Startup Polarity Reg */

#define AT91_PMC_FS_INPUT_MASK  0x7ff

#define AT91_PMC_PLLICPR	0x80			/* PLL Charge Pump Current Register */

#define AT91_PMC_PROT		0xe4			/* Write Protect Mode Register [some SAM9] */
#define		AT91_PMC_WPEN		(0x1  <<  0)		/* Write Protect Enable */
#define		AT91_PMC_WPKEY		(0xffffff << 8)		/* Write Protect Key */
#define		AT91_PMC_PROTKEY	(0x504d43 << 8)		/* Activation Code */

#define AT91_PMC_WPSR		0xe8			/* Write Protect Status Register [some SAM9] */
#define		AT91_PMC_WPVS		(0x1  <<  0)		/* Write Protect Violation Status */
#define		AT91_PMC_WPVSRC		(0xffff  <<  8)		/* Write Protect Violation Source */

#define AT91_PMC_PLL_ISR0	0xEC			/* PLL Interrupt Status Register 0 [SAM9X60 only] */

#define AT91_PMC_PCER1		0x100			/* Peripheral Clock Enable Register 1 [SAMA5 only]*/
#define AT91_PMC_PCDR1		0x104			/* Peripheral Clock Enable Register 1 */
#define AT91_PMC_PCSR1		0x108			/* Peripheral Clock Enable Register 1 */

#define AT91_PMC_PCR		0x10c			/* Peripheral Control Register [some SAM9 and SAMA5] */
#define		AT91_PMC_PCR_PID_MASK		0x3f
#define		AT91_PMC_PCR_CMD		(0x1  <<  12)				/* Command (read=0, write=1) */
#define		AT91_PMC_PCR_GCKDIV_MASK	GENMASK(27, 20)
#define		AT91_PMC_PCR_EN			(0x1  <<  28)				/* Enable */
#define		AT91_PMC_PCR_GCKEN		(0x1  <<  29)				/* GCK Enable */

#define AT91_PMC_AUDIO_PLL0	0x14c
#define		AT91_PMC_AUDIO_PLL_PLLEN	(1  <<  0)
#define		AT91_PMC_AUDIO_PLL_PADEN	(1  <<  1)
#define		AT91_PMC_AUDIO_PLL_PMCEN	(1  <<  2)
#define		AT91_PMC_AUDIO_PLL_RESETN	(1  <<  3)
#define		AT91_PMC_AUDIO_PLL_ND_OFFSET	8
#define		AT91_PMC_AUDIO_PLL_ND_MASK	(0x7f << AT91_PMC_AUDIO_PLL_ND_OFFSET)
#define		AT91_PMC_AUDIO_PLL_ND(n)	((n)  << AT91_PMC_AUDIO_PLL_ND_OFFSET)
#define		AT91_PMC_AUDIO_PLL_QDPMC_OFFSET	16
#define		AT91_PMC_AUDIO_PLL_QDPMC_MASK	(0x7f << AT91_PMC_AUDIO_PLL_QDPMC_OFFSET)
#define		AT91_PMC_AUDIO_PLL_QDPMC(n)	((n)  << AT91_PMC_AUDIO_PLL_QDPMC_OFFSET)

#define AT91_PMC_AUDIO_PLL1	0x150
#define		AT91_PMC_AUDIO_PLL_FRACR_MASK		0x3fffff
#define		AT91_PMC_AUDIO_PLL_QDPAD_OFFSET		24
#define		AT91_PMC_AUDIO_PLL_QDPAD_MASK		(0x7f << AT91_PMC_AUDIO_PLL_QDPAD_OFFSET)
#define		AT91_PMC_AUDIO_PLL_QDPAD(n)		((n)  << AT91_PMC_AUDIO_PLL_QDPAD_OFFSET)
#define		AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET	AT91_PMC_AUDIO_PLL_QDPAD_OFFSET
#define		AT91_PMC_AUDIO_PLL_QDPAD_DIV_MASK	(0x3  << AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET)
#define		AT91_PMC_AUDIO_PLL_QDPAD_DIV(n)		((n)  << AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET)
#define		AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET	26
#define		AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MAX	0x1f
#define		AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MASK	(AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MAX << AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET)
#define		AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV(n)	((n)  << AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET)

#endif
Commit	Line	Data
2874c5fd	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
6171de8f	2	/*
2edb90ae	3	* include/linux/clk/at91_pmc.h
6171de8f AV	4	*
	5	* Copyright (C) 2005 Ivan Kokshaysky
	6	* Copyright (C) SAN People
	7	*
	8	* Power Management Controller (PMC) - System peripherals registers.
	9	* Based on AT91RM9200 datasheet revision E.
6171de8f AV	10	*/
	11
	12	#ifndef AT91_PMC_H
	13	#define AT91_PMC_H
	14
0be298a9 CB	15	#define AT91_PMC_V1 (1) /* PMC version 1 */
	16	#define AT91_PMC_V2 (2) /* PMC version 2 [SAM9X60] */
	17
b5514952 JCPV	18	#define AT91_PMC_SCER 0x00 /* System Clock Enable Register */
	19	#define AT91_PMC_SCDR 0x04 /* System Clock Disable Register */
	20
	21	#define AT91_PMC_SCSR 0x08 /* System Clock Status Register */
6171de8f AV	22	#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
	23	#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
	24	#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
	25	#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
	26	#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
	27	#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */
	28	#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */
	29	#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
	30	#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */
	31	#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */
5e38efae	32	#define AT91_PMC_PCK4 (1 << 12) /* Programmable Clock 4 [AT572D940HF only] */
6171de8f AV	33	#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */
	34	#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */
	35
e13208ab CB	36	#define AT91_PMC_PLL_CTRL0 0x0C /* PLL Control Register 0 [for SAM9X60] */
	37	#define AT91_PMC_PLL_CTRL0_ENPLL (1 << 28) /* Enable PLL */
	38	#define AT91_PMC_PLL_CTRL0_ENPLLCK (1 << 29) /* Enable PLL clock for PMC */
	39	#define AT91_PMC_PLL_CTRL0_ENLOCK (1 << 31) /* Enable PLL lock */
	40
	41	#define AT91_PMC_PLL_CTRL1 0x10 /* PLL Control Register 1 [for SAM9X60] */
	42
b5514952 JCPV	43	#define AT91_PMC_PCER 0x10 /* Peripheral Clock Enable Register */
	44	#define AT91_PMC_PCDR 0x14 /* Peripheral Clock Disable Register */
	45	#define AT91_PMC_PCSR 0x18 /* Peripheral Clock Status Register */
6171de8f	46
e13208ab CB	47	#define AT91_PMC_PLL_ACR 0x18 /* PLL Analog Control Register [for SAM9X60] */
	48	#define AT91_PMC_PLL_ACR_DEFAULT_UPLL 0x12020010UL /* Default PLL ACR value for UPLL */
	49	#define AT91_PMC_PLL_ACR_DEFAULT_PLLA 0x00020010UL /* Default PLL ACR value for PLLA */
	50	#define AT91_PMC_PLL_ACR_UTMIVR (1 << 12) /* UPLL Voltage regulator Control */
	51	#define AT91_PMC_PLL_ACR_UTMIBG (1 << 13) /* UPLL Bandgap Control */
	52
b5514952	53	#define AT91_CKGR_UCKR 0x1C /* UTMI Clock Register [some SAM9] */
53d71680 SP	54	#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */
	55	#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */
	56	#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */
6d0485a9	57	#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */
9ebbec27	58
e13208ab CB	59	#define AT91_PMC_PLL_UPDT 0x1C /* PMC PLL update register [for SAM9X60] */
	60	#define AT91_PMC_PLL_UPDT_UPDATE (1 << 8) /* Update PLL settings */
	61	#define AT91_PMC_PLL_UPDT_ID (1 << 0) /* PLL ID */
0416824e	62	#define AT91_PMC_PLL_UPDT_ID_MSK (0xf) /* PLL ID mask */
e13208ab CB	63	#define AT91_PMC_PLL_UPDT_STUPTIM (0xff << 16) /* Startup time */
e13208ab CB	64
b5514952	65	#define AT91_CKGR_MOR 0x20 /* Main Oscillator Register [not on SAM9RL] */
cbd5c78e NF	66	#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
cbd5c78e NF	67	#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass */
5b56c182	68	#define AT91_PMC_WAITMODE (1 << 2) /* Wait Mode Command */
cbd5c78e NF	69	#define AT91_PMC_MOSCRCEN (1 << 3) /* Main On-Chip RC Oscillator Enable [some SAM9] */
cbd5c78e NF	70	#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
5b56c182	71	#define AT91_PMC_KEY_MASK (0xff << 16)
cbd5c78e NF	72	#define AT91_PMC_KEY (0x37 << 16) /* MOR Writing Key */
	73	#define AT91_PMC_MOSCSEL (1 << 24) /* Main Oscillator Selection [some SAM9] */
	74	#define AT91_PMC_CFDEN (1 << 25) /* Clock Failure Detector Enable [some SAM9] */
6171de8f	75
b5514952	76	#define AT91_CKGR_MCFR 0x24 /* Main Clock Frequency Register */
6171de8f AV	77	#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
	78	#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */
	79
b5514952	80	#define AT91_CKGR_PLLAR 0x28 /* PLL A Register */
9584e726 CB	81
	82	#define AT91_PMC_RATIO 0x2c /* Processor clock ratio register [SAMA7G5 only] */
	83	#define AT91_PMC_RATIO_RATIO (0xf) /* CPU clock ratio. */
	84
b5514952	85	#define AT91_CKGR_PLLBR 0x2c /* PLL B Register */
6171de8f AV	86	#define AT91_PMC_DIV (0xff << 0) /* Divider */
	87	#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
	88	#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
	89	#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */
8f4b4794 LD	90	#define AT91_PMC_MUL_GET(n) ((n) >> 16 & 0x7ff)
	91	#define AT91_PMC3_MUL (0x7f << 18) /* PLL Multiplier [SAMA5 only] */
	92	#define AT91_PMC3_MUL_GET(n) ((n) >> 18 & 0x7f)
2b3b3516 AV	93	#define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */
	94	#define AT91_PMC_USBDIV_1 (0 << 28)
	95	#define AT91_PMC_USBDIV_2 (1 << 28)
	96	#define AT91_PMC_USBDIV_4 (2 << 28)
6171de8f AV	97	#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
6171de8f AV	98
e5be5370 AB	99	#define AT91_PMC_CPU_CKR 0x28 /* CPU Clock Register */
e5be5370 AB	100
b5514952	101	#define AT91_PMC_MCKR 0x30 /* Master Clock Register */
6171de8f AV	102	#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */
	103	#define AT91_PMC_CSS_SLOW (0 << 0)
	104	#define AT91_PMC_CSS_MAIN (1 << 0)
	105	#define AT91_PMC_CSS_PLLA (2 << 0)
	106	#define AT91_PMC_CSS_PLLB (3 << 0)
6d0485a9	107	#define AT91_PMC_CSS_UPLL (3 << 0) /* [some SAM9 only] */
cbd5c78e NF	108	#define PMC_PRES_OFFSET 2
	109	#define AT91_PMC_PRES (7 << PMC_PRES_OFFSET) /* Master Clock Prescaler */
	110	#define AT91_PMC_PRES_1 (0 << PMC_PRES_OFFSET)
	111	#define AT91_PMC_PRES_2 (1 << PMC_PRES_OFFSET)
	112	#define AT91_PMC_PRES_4 (2 << PMC_PRES_OFFSET)
	113	#define AT91_PMC_PRES_8 (3 << PMC_PRES_OFFSET)
	114	#define AT91_PMC_PRES_16 (4 << PMC_PRES_OFFSET)
	115	#define AT91_PMC_PRES_32 (5 << PMC_PRES_OFFSET)
	116	#define AT91_PMC_PRES_64 (6 << PMC_PRES_OFFSET)
	117	#define PMC_ALT_PRES_OFFSET 4
	118	#define AT91_PMC_ALT_PRES (7 << PMC_ALT_PRES_OFFSET) /* Master Clock Prescaler [alternate location] */
	119	#define AT91_PMC_ALT_PRES_1 (0 << PMC_ALT_PRES_OFFSET)
	120	#define AT91_PMC_ALT_PRES_2 (1 << PMC_ALT_PRES_OFFSET)
	121	#define AT91_PMC_ALT_PRES_4 (2 << PMC_ALT_PRES_OFFSET)
	122	#define AT91_PMC_ALT_PRES_8 (3 << PMC_ALT_PRES_OFFSET)
	123	#define AT91_PMC_ALT_PRES_16 (4 << PMC_ALT_PRES_OFFSET)
	124	#define AT91_PMC_ALT_PRES_32 (5 << PMC_ALT_PRES_OFFSET)
	125	#define AT91_PMC_ALT_PRES_64 (6 << PMC_ALT_PRES_OFFSET)
6171de8f	126	#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */
32b1216d AV	127	#define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */
	128	#define AT91RM9200_PMC_MDIV_2 (1 << 8)
	129	#define AT91RM9200_PMC_MDIV_3 (2 << 8)
	130	#define AT91RM9200_PMC_MDIV_4 (3 << 8)
9918ceaf	131	#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9 only] */
32b1216d AV	132	#define AT91SAM9_PMC_MDIV_2 (1 << 8)
32b1216d AV	133	#define AT91SAM9_PMC_MDIV_4 (2 << 8)
6d0485a9 NF	134	#define AT91SAM9_PMC_MDIV_6 (3 << 8) /* [some SAM9 only] */
6d0485a9 NF	135	#define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */
32b1216d AV	136	#define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */
	137	#define AT91_PMC_PDIV_1 (0 << 12)
	138	#define AT91_PMC_PDIV_2 (1 << 12)
6d0485a9 NF	139	#define AT91_PMC_PLLADIV2 (1 << 12) /* PLLA divisor by 2 [some SAM9 only] */
	140	#define AT91_PMC_PLLADIV2_OFF (0 << 12)
	141	#define AT91_PMC_PLLADIV2_ON (1 << 12)
bcc5fd49	142	#define AT91_PMC_H32MXDIV BIT(24)
6171de8f	143
ec03f18c CB	144	#define AT91_PMC_MCR_V2 0x30 /* Master Clock Register [SAMA7G5 only] */
	145	#define AT91_PMC_MCR_V2_ID_MSK (0xF)
	146	#define AT91_PMC_MCR_V2_ID(_id) ((_id) & AT91_PMC_MCR_V2_ID_MSK)
	147	#define AT91_PMC_MCR_V2_CMD (1 << 7)
	148	#define AT91_PMC_MCR_V2_DIV (7 << 8)
	149	#define AT91_PMC_MCR_V2_DIV1 (0 << 8)
	150	#define AT91_PMC_MCR_V2_DIV2 (1 << 8)
	151	#define AT91_PMC_MCR_V2_DIV4 (2 << 8)
	152	#define AT91_PMC_MCR_V2_DIV8 (3 << 8)
	153	#define AT91_PMC_MCR_V2_DIV16 (4 << 8)
	154	#define AT91_PMC_MCR_V2_DIV32 (5 << 8)
	155	#define AT91_PMC_MCR_V2_DIV64 (6 << 8)
	156	#define AT91_PMC_MCR_V2_DIV3 (7 << 8)
	157	#define AT91_PMC_MCR_V2_CSS (0x1F << 16)
	158	#define AT91_PMC_MCR_V2_CSS_MD_SLCK (0 << 16)
	159	#define AT91_PMC_MCR_V2_CSS_TD_SLCK (1 << 16)
	160	#define AT91_PMC_MCR_V2_CSS_MAINCK (2 << 16)
	161	#define AT91_PMC_MCR_V2_CSS_MCK0 (3 << 16)
	162	#define AT91_PMC_MCR_V2_CSS_SYSPLL (5 << 16)
	163	#define AT91_PMC_MCR_V2_CSS_DDRPLL (6 << 16)
	164	#define AT91_PMC_MCR_V2_CSS_IMGPLL (7 << 16)
	165	#define AT91_PMC_MCR_V2_CSS_BAUDPLL (8 << 16)
	166	#define AT91_PMC_MCR_V2_CSS_AUDIOPLL (9 << 16)
	167	#define AT91_PMC_MCR_V2_CSS_ETHPLL (10 << 16)
	168	#define AT91_PMC_MCR_V2_EN (1 << 28)
	169
ef396df9 CB	170	#define AT91_PMC_XTALF 0x34 /* Main XTAL Frequency Register [SAMA7G5 only] */
ef396df9 CB	171
b5514952	172	#define AT91_PMC_USB 0x38 /* USB Clock Register [some SAM9 only] */
6d0485a9 NF	173	#define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */
	174	#define AT91_PMC_USBS_PLLA (0 << 0)
	175	#define AT91_PMC_USBS_UPLL (1 << 0)
d04e5b69	176	#define AT91_PMC_USBS_PLLB (1 << 0) /* [AT91SAMN12 only] */
6d0485a9	177	#define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */
d04e5b69 NF	178	#define AT91_PMC_OHCIUSBDIV_1 (0x0 << 8)
d04e5b69 NF	179	#define AT91_PMC_OHCIUSBDIV_2 (0x1 << 8)
6d0485a9	180
b5514952	181	#define AT91_PMC_SMD 0x3c /* Soft Modem Clock Register [some SAM9 only] */
cbd5c78e NF	182	#define AT91_PMC_SMDS (0x1 << 0) /* SMD input clock selection */
	183	#define AT91_PMC_SMD_DIV (0x1f << 8) /* SMD input clock divider */
	184	#define AT91_PMC_SMDDIV(n) (((n) << 8) & AT91_PMC_SMD_DIV)
	185
b5514952	186	#define AT91_PMC_PCKR(n) (0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */
cbd5c78e NF	187	#define AT91_PMC_ALT_PCKR_CSS (0x7 << 0) /* Programmable Clock Source Selection [alternate length] */
cbd5c78e NF	188	#define AT91_PMC_CSS_MASTER (4 << 0) /* [some SAM9 only] */
6d0485a9 NF	189	#define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */
	190	#define AT91_PMC_CSSMCK_CSS (0 << 8)
	191	#define AT91_PMC_CSSMCK_MCK (1 << 8)
6171de8f	192
b5514952 JCPV	193	#define AT91_PMC_IER 0x60 /* Interrupt Enable Register */
	194	#define AT91_PMC_IDR 0x64 /* Interrupt Disable Register */
	195	#define AT91_PMC_SR 0x68 /* Status Register */
6171de8f AV	196	#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */
	197	#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
	198	#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
	199	#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
9918ceaf	200	#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [some SAM9] */
80eded6c	201	#define AT91_PMC_OSCSEL (1 << 7) /* Slow Oscillator Selection [some SAM9] */
6171de8f AV	202	#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
	203	#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
	204	#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
	205	#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
cbd5c78e NF	206	#define AT91_PMC_MOSCSELS (1 << 16) /* Main Oscillator Selection [some SAM9] */
	207	#define AT91_PMC_MOSCRCS (1 << 17) /* Main On-Chip RC [some SAM9] */
	208	#define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */
a5752e57	209	#define AT91_PMC_GCKRDY (1 << 24) /* Generated Clocks */
75c88143	210	#define AT91_PMC_MCKXRDY (1 << 26) /* Master Clock x [x=1..4] Ready Status */
b5514952	211	#define AT91_PMC_IMR 0x6c /* Interrupt Mask Register */
6171de8f	212
3abd729a CB	213	#define AT91_PMC_FSMR 0x70 /* Fast Startup Mode Register */
3abd729a CB	214	#define AT91_PMC_FSTT(n) BIT(n)
eaedc0d3	215	#define AT91_PMC_RTTAL BIT(16)
3abd729a CB	216	#define AT91_PMC_RTCAL BIT(17) /* RTC Alarm Enable */
	217	#define AT91_PMC_USBAL BIT(18) /* USB Resume Enable */
	218	#define AT91_PMC_SDMMC_CD BIT(19) /* SDMMC Card Detect Enable */
	219	#define AT91_PMC_LPM BIT(20) /* Low-power Mode */
	220	#define AT91_PMC_RXLP_MCE BIT(24) /* Backup UART Receive Enable */
	221	#define AT91_PMC_ACC_CE BIT(25) /* ACC Enable */
	222
	223	#define AT91_PMC_FSPR 0x74 /* Fast Startup Polarity Reg */
	224
	225	#define AT91_PMC_FS_INPUT_MASK 0x7ff
	226
1a748d2b BB	227	#define AT91_PMC_PLLICPR 0x80 /* PLL Charge Pump Current Register */
1a748d2b BB	228
b5514952	229	#define AT91_PMC_PROT 0xe4 /* Write Protect Mode Register [some SAM9] */
cbd5c78e NF	230	#define AT91_PMC_WPEN (0x1 << 0) /* Write Protect Enable */
	231	#define AT91_PMC_WPKEY (0xffffff << 8) /* Write Protect Key */
	232	#define AT91_PMC_PROTKEY (0x504d43 << 8) /* Activation Code */
	233
b5514952	234	#define AT91_PMC_WPSR 0xe8 /* Write Protect Status Register [some SAM9] */
cbd5c78e NF	235	#define AT91_PMC_WPVS (0x1 << 0) /* Write Protect Violation Status */
cbd5c78e NF	236	#define AT91_PMC_WPVSRC (0xffff << 8) /* Write Protect Violation Source */
7be90a6b	237
e13208ab CB	238	#define AT91_PMC_PLL_ISR0 0xEC /* PLL Interrupt Status Register 0 [SAM9X60 only] */
e13208ab CB	239
8f4b4794 LD	240	#define AT91_PMC_PCER1 0x100 /* Peripheral Clock Enable Register 1 [SAMA5 only]*/
	241	#define AT91_PMC_PCDR1 0x104 /* Peripheral Clock Enable Register 1 */
	242	#define AT91_PMC_PCSR1 0x108 /* Peripheral Clock Enable Register 1 */
	243
	244	#define AT91_PMC_PCR 0x10c /* Peripheral Control Register [some SAM9 and SAMA5] */
96ef36e9 NF	245	#define AT91_PMC_PCR_PID_MASK 0x3f
96ef36e9 NF	246	#define AT91_PMC_PCR_CMD (0x1 << 12) /* Command (read=0, write=1) */
e4cfb823	247	#define AT91_PMC_PCR_GCKDIV_MASK GENMASK(27, 20)
96ef36e9	248	#define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */
df70aeef	249	#define AT91_PMC_PCR_GCKEN (0x1 << 29) /* GCK Enable */
7be90a6b	250
0865805d QS	251	#define AT91_PMC_AUDIO_PLL0 0x14c
	252	#define AT91_PMC_AUDIO_PLL_PLLEN (1 << 0)
	253	#define AT91_PMC_AUDIO_PLL_PADEN (1 << 1)
	254	#define AT91_PMC_AUDIO_PLL_PMCEN (1 << 2)
	255	#define AT91_PMC_AUDIO_PLL_RESETN (1 << 3)
	256	#define AT91_PMC_AUDIO_PLL_ND_OFFSET 8
	257	#define AT91_PMC_AUDIO_PLL_ND_MASK (0x7f << AT91_PMC_AUDIO_PLL_ND_OFFSET)
	258	#define AT91_PMC_AUDIO_PLL_ND(n) ((n) << AT91_PMC_AUDIO_PLL_ND_OFFSET)
	259	#define AT91_PMC_AUDIO_PLL_QDPMC_OFFSET 16
	260	#define AT91_PMC_AUDIO_PLL_QDPMC_MASK (0x7f << AT91_PMC_AUDIO_PLL_QDPMC_OFFSET)
	261	#define AT91_PMC_AUDIO_PLL_QDPMC(n) ((n) << AT91_PMC_AUDIO_PLL_QDPMC_OFFSET)
	262
	263	#define AT91_PMC_AUDIO_PLL1 0x150
	264	#define AT91_PMC_AUDIO_PLL_FRACR_MASK 0x3fffff
	265	#define AT91_PMC_AUDIO_PLL_QDPAD_OFFSET 24
	266	#define AT91_PMC_AUDIO_PLL_QDPAD_MASK (0x7f << AT91_PMC_AUDIO_PLL_QDPAD_OFFSET)
	267	#define AT91_PMC_AUDIO_PLL_QDPAD(n) ((n) << AT91_PMC_AUDIO_PLL_QDPAD_OFFSET)
	268	#define AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET AT91_PMC_AUDIO_PLL_QDPAD_OFFSET
	269	#define AT91_PMC_AUDIO_PLL_QDPAD_DIV_MASK (0x3 << AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET)
	270	#define AT91_PMC_AUDIO_PLL_QDPAD_DIV(n) ((n) << AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET)
	271	#define AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET 26
	272	#define AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MAX 0x1f
	273	#define AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MASK (AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MAX << AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET)
	274	#define AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV(n) ((n) << AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET)
	275
6171de8f	276	#endif