[linux-block.git] / include / linux / cacheinfo.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _LINUX_CACHEINFO_H
#define _LINUX_CACHEINFO_H

#include <linux/bitops.h>
#include <linux/cpumask.h>
#include <linux/smp.h>

struct device_node;
struct attribute;

enum cache_type {
	CACHE_TYPE_NOCACHE = 0,
	CACHE_TYPE_INST = BIT(0),
	CACHE_TYPE_DATA = BIT(1),
	CACHE_TYPE_SEPARATE = CACHE_TYPE_INST | CACHE_TYPE_DATA,
	CACHE_TYPE_UNIFIED = BIT(2),
};

extern unsigned int coherency_max_size;

/**
 * struct cacheinfo - represent a cache leaf node
 * @id: This cache's id. It is unique among caches with the same (type, level).
 * @type: type of the cache - data, inst or unified
 * @level: represents the hierarchy in the multi-level cache
 * @coherency_line_size: size of each cache line usually representing
 *	the minimum amount of data that gets transferred from memory
 * @number_of_sets: total number of sets, a set is a collection of cache
 *	lines sharing the same index
 * @ways_of_associativity: number of ways in which a particular memory
 *	block can be placed in the cache
 * @physical_line_partition: number of physical cache lines sharing the
 *	same cachetag
 * @size: Total size of the cache
 * @shared_cpu_map: logical cpumask representing all the cpus sharing
 *	this cache node
 * @attributes: bitfield representing various cache attributes
 * @fw_token: Unique value used to determine if different cacheinfo
 *	structures represent a single hardware cache instance.
 * @disable_sysfs: indicates whether this node is visible to the user via
 *	sysfs or not
 * @priv: pointer to any private data structure specific to particular
 *	cache design
 *
 * While @of_node, @disable_sysfs and @priv are used for internal book
 * keeping, the remaining members form the core properties of the cache
 */
struct cacheinfo {
	unsigned int id;
	enum cache_type type;
	unsigned int level;
	unsigned int coherency_line_size;
	unsigned int number_of_sets;
	unsigned int ways_of_associativity;
	unsigned int physical_line_partition;
	unsigned int size;
	cpumask_t shared_cpu_map;
	unsigned int attributes;
#define CACHE_WRITE_THROUGH	BIT(0)
#define CACHE_WRITE_BACK	BIT(1)
#define CACHE_WRITE_POLICY_MASK		\
	(CACHE_WRITE_THROUGH | CACHE_WRITE_BACK)
#define CACHE_READ_ALLOCATE	BIT(2)
#define CACHE_WRITE_ALLOCATE	BIT(3)
#define CACHE_ALLOCATE_POLICY_MASK	\
	(CACHE_READ_ALLOCATE | CACHE_WRITE_ALLOCATE)
#define CACHE_ID		BIT(4)
	void *fw_token;
	bool disable_sysfs;
	void *priv;
};

struct cpu_cacheinfo {
	struct cacheinfo *info_list;
	unsigned int num_levels;
	unsigned int num_leaves;
	bool cpu_map_populated;
	bool early_ci_levels;
};

struct cpu_cacheinfo *get_cpu_cacheinfo(unsigned int cpu);
int early_cache_level(unsigned int cpu);
int init_cache_level(unsigned int cpu);
int init_of_cache_level(unsigned int cpu);
int populate_cache_leaves(unsigned int cpu);
int cache_setup_acpi(unsigned int cpu);
bool last_level_cache_is_valid(unsigned int cpu);
bool last_level_cache_is_shared(unsigned int cpu_x, unsigned int cpu_y);
int fetch_cache_info(unsigned int cpu);
int detect_cache_attributes(unsigned int cpu);
#ifndef CONFIG_ACPI_PPTT
/*
 * acpi_get_cache_info() is only called on ACPI enabled
 * platforms using the PPTT for topology. This means that if
 * the platform supports other firmware configuration methods
 * we need to stub out the call when ACPI is disabled.
 * ACPI enabled platforms not using PPTT won't be making calls
 * to this function so we need not worry about them.
 */
static inline
int acpi_get_cache_info(unsigned int cpu,
			unsigned int *levels, unsigned int *split_levels)
{
	return -ENOENT;
}
#else
int acpi_get_cache_info(unsigned int cpu,
			unsigned int *levels, unsigned int *split_levels);
#endif

const struct attribute_group *cache_get_priv_group(struct cacheinfo *this_leaf);

/*
 * Get the id of the cache associated with @cpu at level @level.
 * cpuhp lock must be held.
 */
static inline int get_cpu_cacheinfo_id(int cpu, int level)
{
	struct cpu_cacheinfo *ci = get_cpu_cacheinfo(cpu);
	int i;

	for (i = 0; i < ci->num_leaves; i++) {
		if (ci->info_list[i].level == level) {
			if (ci->info_list[i].attributes & CACHE_ID)
				return ci->info_list[i].id;
			return -1;
		}
	}

	return -1;
}

#ifdef CONFIG_ARM64
#define use_arch_cache_info()	(true)
#else
#define use_arch_cache_info()	(false)
#endif

#endif /* _LINUX_CACHEINFO_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
246246cb SH	2	#ifndef _LINUX_CACHEINFO_H
	3	#define _LINUX_CACHEINFO_H
	4
	5	#include <linux/bitops.h>
	6	#include <linux/cpumask.h>
	7	#include <linux/smp.h>
	8
	9	struct device_node;
	10	struct attribute;
	11
	12	enum cache_type {
	13	CACHE_TYPE_NOCACHE = 0,
	14	CACHE_TYPE_INST = BIT(0),
	15	CACHE_TYPE_DATA = BIT(1),
	16	CACHE_TYPE_SEPARATE = CACHE_TYPE_INST \| CACHE_TYPE_DATA,
	17	CACHE_TYPE_UNIFIED = BIT(2),
	18	};
	19
9a83c84c SZ	20	extern unsigned int coherency_max_size;
9a83c84c SZ	21
246246cb SH	22	/**
246246cb SH	23	* struct cacheinfo - represent a cache leaf node
e9a2ea5a	24	* @id: This cache's id. It is unique among caches with the same (type, level).
246246cb	25	* @type: type of the cache - data, inst or unified
2539b258	26	* @level: represents the hierarchy in the multi-level cache
246246cb SH	27	* @coherency_line_size: size of each cache line usually representing
	28	* the minimum amount of data that gets transferred from memory
	29	* @number_of_sets: total number of sets, a set is a collection of cache
	30	* lines sharing the same index
	31	* @ways_of_associativity: number of ways in which a particular memory
	32	* block can be placed in the cache
	33	* @physical_line_partition: number of physical cache lines sharing the
	34	* same cachetag
	35	* @size: Total size of the cache
	36	* @shared_cpu_map: logical cpumask representing all the cpus sharing
	37	* this cache node
	38	* @attributes: bitfield representing various cache attributes
9b97387c JL	39	* @fw_token: Unique value used to determine if different cacheinfo
9b97387c JL	40	* structures represent a single hardware cache instance.
246246cb SH	41	* @disable_sysfs: indicates whether this node is visible to the user via
	42	* sysfs or not
	43	* @priv: pointer to any private data structure specific to particular
	44	* cache design
	45	*
	46	* While @of_node, @disable_sysfs and @priv are used for internal book
	47	* keeping, the remaining members form the core properties of the cache
	48	*/
	49	struct cacheinfo {
e9a2ea5a	50	unsigned int id;
246246cb SH	51	enum cache_type type;
	52	unsigned int level;
	53	unsigned int coherency_line_size;
	54	unsigned int number_of_sets;
	55	unsigned int ways_of_associativity;
	56	unsigned int physical_line_partition;
	57	unsigned int size;
	58	cpumask_t shared_cpu_map;
	59	unsigned int attributes;
	60	#define CACHE_WRITE_THROUGH BIT(0)
	61	#define CACHE_WRITE_BACK BIT(1)
	62	#define CACHE_WRITE_POLICY_MASK \
	63	(CACHE_WRITE_THROUGH \| CACHE_WRITE_BACK)
	64	#define CACHE_READ_ALLOCATE BIT(2)
	65	#define CACHE_WRITE_ALLOCATE BIT(3)
	66	#define CACHE_ALLOCATE_POLICY_MASK \
	67	(CACHE_READ_ALLOCATE \| CACHE_WRITE_ALLOCATE)
e9a2ea5a	68	#define CACHE_ID BIT(4)
9b97387c	69	void *fw_token;
246246cb SH	70	bool disable_sysfs;
	71	void *priv;
	72	};
	73
	74	struct cpu_cacheinfo {
	75	struct cacheinfo *info_list;
	76	unsigned int num_levels;
	77	unsigned int num_leaves;
fac51482	78	bool cpu_map_populated;
6539cffa	79	bool early_ci_levels;
246246cb SH	80	};
246246cb SH	81
246246cb	82	struct cpu_cacheinfo *get_cpu_cacheinfo(unsigned int cpu);
6539cffa	83	int early_cache_level(unsigned int cpu);
246246cb	84	int init_cache_level(unsigned int cpu);
c3719bd9	85	int init_of_cache_level(unsigned int cpu);
246246cb	86	int populate_cache_leaves(unsigned int cpu);
582b468b	87	int cache_setup_acpi(unsigned int cpu);
cc1cfc47 SH	88	bool last_level_cache_is_valid(unsigned int cpu);
cc1cfc47 SH	89	bool last_level_cache_is_shared(unsigned int cpu_x, unsigned int cpu_y);
5944ce09	90	int fetch_cache_info(unsigned int cpu);
36bbc5b4	91	int detect_cache_attributes(unsigned int cpu);
2520e627	92	#ifndef CONFIG_ACPI_PPTT
582b468b	93	/*
bd500361	94	* acpi_get_cache_info() is only called on ACPI enabled
582b468b JL	95	* platforms using the PPTT for topology. This means that if
	96	* the platform supports other firmware configuration methods
	97	* we need to stub out the call when ACPI is disabled.
	98	* ACPI enabled platforms not using PPTT won't be making calls
	99	* to this function so we need not worry about them.
	100	*/
bd500361 PG	101	static inline
	102	int acpi_get_cache_info(unsigned int cpu,
	103	unsigned int levels, unsigned int split_levels)
582b468b	104	{
d931b83e	105	return -ENOENT;
582b468b JL	106	}
582b468b JL	107	#else
bd500361 PG	108	int acpi_get_cache_info(unsigned int cpu,
bd500361 PG	109	unsigned int levels, unsigned int split_levels);
582b468b	110	#endif
246246cb SH	111
	112	const struct attribute_group cache_get_priv_group(struct cacheinfo this_leaf);
	113
709c4362 JM	114	/*
	115	* Get the id of the cache associated with @cpu at level @level.
	116	* cpuhp lock must be held.
	117	*/
	118	static inline int get_cpu_cacheinfo_id(int cpu, int level)
	119	{
	120	struct cpu_cacheinfo *ci = get_cpu_cacheinfo(cpu);
	121	int i;
	122
	123	for (i = 0; i < ci->num_leaves; i++) {
	124	if (ci->info_list[i].level == level) {
	125	if (ci->info_list[i].attributes & CACHE_ID)
	126	return ci->info_list[i].id;
	127	return -1;
	128	}
	129	}
	130
	131	return -1;
	132	}
	133
ef9f643a PG	134	#ifdef CONFIG_ARM64
	135	#define use_arch_cache_info() (true)
	136	#else
	137	#define use_arch_cache_info() (false)
	138	#endif
	139
246246cb	140	#endif /* _LINUX_CACHEINFO_H */