[linux-block.git] / include / linux / brcmphy.h

#ifndef _LINUX_BRCMPHY_H
#define _LINUX_BRCMPHY_H

#define PHY_ID_BCM50610			0x0143bd60
#define PHY_ID_BCM50610M		0x0143bd70
#define PHY_ID_BCM5241			0x0143bc30
#define PHY_ID_BCMAC131			0x0143bc70
#define PHY_ID_BCM5481			0x0143bca0
#define PHY_ID_BCM5482			0x0143bcb0
#define PHY_ID_BCM5411			0x00206070
#define PHY_ID_BCM5421			0x002060e0
#define PHY_ID_BCM5464			0x002060b0
#define PHY_ID_BCM5461			0x002060c0
#define PHY_ID_BCM57780			0x03625d90

#define PHY_ID_BCM7366			0x600d8490
#define PHY_ID_BCM7439			0x600d8480
#define PHY_ID_BCM7445			0x600d8510

#define PHY_BCM_OUI_MASK		0xfffffc00
#define PHY_BCM_OUI_1			0x00206000
#define PHY_BCM_OUI_2			0x0143bc00
#define PHY_BCM_OUI_3			0x03625c00
#define PHY_BCM_OUI_4			0x600d0000
#define PHY_BCM_OUI_5			0x03625e00


#define PHY_BCM_FLAGS_MODE_COPPER	0x00000001
#define PHY_BCM_FLAGS_MODE_1000BX	0x00000002
#define PHY_BCM_FLAGS_INTF_SGMII	0x00000010
#define PHY_BCM_FLAGS_INTF_XAUI		0x00000020
#define PHY_BRCM_WIRESPEED_ENABLE	0x00000100
#define PHY_BRCM_AUTO_PWRDWN_ENABLE	0x00000200
#define PHY_BRCM_RX_REFCLK_UNUSED	0x00000400
#define PHY_BRCM_STD_IBND_DISABLE	0x00000800
#define PHY_BRCM_EXT_IBND_RX_ENABLE	0x00001000
#define PHY_BRCM_EXT_IBND_TX_ENABLE	0x00002000
#define PHY_BRCM_CLEAR_RGMII_MODE	0x00004000
#define PHY_BRCM_DIS_TXCRXC_NOENRGY	0x00008000
/* Broadcom BCM7xxx specific workarounds */
#define PHY_BRCM_100MBPS_WAR		0x00010000
#define PHY_BCM_FLAGS_VALID		0x80000000

/* Broadcom BCM54XX register definitions, common to most Broadcom PHYs */
#define MII_BCM54XX_ECR		0x10	/* BCM54xx extended control register */
#define MII_BCM54XX_ECR_IM	0x1000	/* Interrupt mask */
#define MII_BCM54XX_ECR_IF	0x0800	/* Interrupt force */

#define MII_BCM54XX_ESR		0x11	/* BCM54xx extended status register */
#define MII_BCM54XX_ESR_IS	0x1000	/* Interrupt status */

#define MII_BCM54XX_EXP_DATA	0x15	/* Expansion register data */
#define MII_BCM54XX_EXP_SEL	0x17	/* Expansion register select */
#define MII_BCM54XX_EXP_SEL_SSD	0x0e00	/* Secondary SerDes select */
#define MII_BCM54XX_EXP_SEL_ER	0x0f00	/* Expansion register select */

#define MII_BCM54XX_AUX_CTL	0x18	/* Auxiliary control register */
#define MII_BCM54XX_ISR		0x1a	/* BCM54xx interrupt status register */
#define MII_BCM54XX_IMR		0x1b	/* BCM54xx interrupt mask register */
#define MII_BCM54XX_INT_CRCERR	0x0001	/* CRC error */
#define MII_BCM54XX_INT_LINK	0x0002	/* Link status changed */
#define MII_BCM54XX_INT_SPEED	0x0004	/* Link speed change */
#define MII_BCM54XX_INT_DUPLEX	0x0008	/* Duplex mode changed */
#define MII_BCM54XX_INT_LRS	0x0010	/* Local receiver status changed */
#define MII_BCM54XX_INT_RRS	0x0020	/* Remote receiver status changed */
#define MII_BCM54XX_INT_SSERR	0x0040	/* Scrambler synchronization error */
#define MII_BCM54XX_INT_UHCD	0x0080	/* Unsupported HCD negotiated */
#define MII_BCM54XX_INT_NHCD	0x0100	/* No HCD */
#define MII_BCM54XX_INT_NHCDL	0x0200	/* No HCD link */
#define MII_BCM54XX_INT_ANPR	0x0400	/* Auto-negotiation page received */
#define MII_BCM54XX_INT_LC	0x0800	/* All counters below 128 */
#define MII_BCM54XX_INT_HC	0x1000	/* Counter above 32768 */
#define MII_BCM54XX_INT_MDIX	0x2000	/* MDIX status change */
#define MII_BCM54XX_INT_PSERR	0x4000	/* Pair swap error */

#define MII_BCM54XX_SHD		0x1c	/* 0x1c shadow registers */
#define MII_BCM54XX_SHD_WRITE	0x8000
#define MII_BCM54XX_SHD_VAL(x)	((x & 0x1f) << 10)
#define MII_BCM54XX_SHD_DATA(x)	((x & 0x3ff) << 0)

/*
 * AUXILIARY CONTROL SHADOW ACCESS REGISTERS.  (PHY REG 0x18)
 */
#define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL	0x0000
#define MII_BCM54XX_AUXCTL_ACTL_TX_6DB		0x0400
#define MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA	0x0800

#define MII_BCM54XX_AUXCTL_MISC_WREN	0x8000
#define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX	0x0200
#define MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC	0x7000
#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC	0x0007

#define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL	0x0000

/*
 * Broadcom LED source encodings.  These are used in BCM5461, BCM5481,
 * BCM5482, and possibly some others.
 */
#define BCM_LED_SRC_LINKSPD1	0x0
#define BCM_LED_SRC_LINKSPD2	0x1
#define BCM_LED_SRC_XMITLED	0x2
#define BCM_LED_SRC_ACTIVITYLED	0x3
#define BCM_LED_SRC_FDXLED	0x4
#define BCM_LED_SRC_SLAVE	0x5
#define BCM_LED_SRC_INTR	0x6
#define BCM_LED_SRC_QUALITY	0x7
#define BCM_LED_SRC_RCVLED	0x8
#define BCM_LED_SRC_MULTICOLOR1	0xa
#define BCM_LED_SRC_OPENSHORT	0xb
#define BCM_LED_SRC_OFF		0xe	/* Tied high */
#define BCM_LED_SRC_ON		0xf	/* Tied low */


/*
 * BCM5482: Shadow registers
 * Shadow values go into bits [14:10] of register 0x1c to select a shadow
 * register to access.
 */
/* 00101: Spare Control Register 3 */
#define BCM54XX_SHD_SCR3		0x05
#define  BCM54XX_SHD_SCR3_DEF_CLK125	0x0001
#define  BCM54XX_SHD_SCR3_DLLAPD_DIS	0x0002
#define  BCM54XX_SHD_SCR3_TRDDAPD	0x0004

/* 01010: Auto Power-Down */
#define BCM54XX_SHD_APD			0x0a
#define  BCM54XX_SHD_APD_EN		0x0020

#define BCM5482_SHD_LEDS1	0x0d	/* 01101: LED Selector 1 */
					/* LED3 / ~LINKSPD[2] selector */
#define BCM5482_SHD_LEDS1_LED3(src)	((src & 0xf) << 4)
					/* LED1 / ~LINKSPD[1] selector */
#define BCM5482_SHD_LEDS1_LED1(src)	((src & 0xf) << 0)
#define BCM54XX_SHD_RGMII_MODE	0x0b	/* 01011: RGMII Mode Selector */
#define BCM5482_SHD_SSD		0x14	/* 10100: Secondary SerDes control */
#define BCM5482_SHD_SSD_LEDM	0x0008	/* SSD LED Mode enable */
#define BCM5482_SHD_SSD_EN	0x0001	/* SSD enable */
#define BCM5482_SHD_MODE	0x1f	/* 11111: Mode Control Register */
#define BCM5482_SHD_MODE_1000BX	0x0001	/* Enable 1000BASE-X registers */


/*
 * EXPANSION SHADOW ACCESS REGISTERS.  (PHY REG 0x15, 0x16, and 0x17)
 */
#define MII_BCM54XX_EXP_AADJ1CH0		0x001f
#define  MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN	0x0200
#define  MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF	0x0100
#define MII_BCM54XX_EXP_AADJ1CH3		0x601f
#define  MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ	0x0002
#define MII_BCM54XX_EXP_EXP08			0x0F08
#define  MII_BCM54XX_EXP_EXP08_RJCT_2MHZ	0x0001
#define  MII_BCM54XX_EXP_EXP08_EARLY_DAC_WAKE	0x0200
#define MII_BCM54XX_EXP_EXP75			0x0f75
#define  MII_BCM54XX_EXP_EXP75_VDACCTRL		0x003c
#define  MII_BCM54XX_EXP_EXP75_CM_OSC		0x0001
#define MII_BCM54XX_EXP_EXP96			0x0f96
#define  MII_BCM54XX_EXP_EXP96_MYST		0x0010
#define MII_BCM54XX_EXP_EXP97			0x0f97
#define  MII_BCM54XX_EXP_EXP97_MYST		0x0c0c

/*
 * BCM5482: Secondary SerDes registers
 */
#define BCM5482_SSD_1000BX_CTL		0x00	/* 1000BASE-X Control */
#define BCM5482_SSD_1000BX_CTL_PWRDOWN	0x0800	/* Power-down SSD */
#define BCM5482_SSD_SGMII_SLAVE		0x15	/* SGMII Slave Register */
#define BCM5482_SSD_SGMII_SLAVE_EN	0x0002	/* Slave mode enable */
#define BCM5482_SSD_SGMII_SLAVE_AD	0x0001	/* Slave auto-detection */


/*****************************************************************************/
/* Fast Ethernet Transceiver definitions. */
/*****************************************************************************/

#define MII_BRCM_FET_INTREG		0x1a	/* Interrupt register */
#define MII_BRCM_FET_IR_MASK		0x0100	/* Mask all interrupts */
#define MII_BRCM_FET_IR_LINK_EN		0x0200	/* Link status change enable */
#define MII_BRCM_FET_IR_SPEED_EN	0x0400	/* Link speed change enable */
#define MII_BRCM_FET_IR_DUPLEX_EN	0x0800	/* Duplex mode change enable */
#define MII_BRCM_FET_IR_ENABLE		0x4000	/* Interrupt enable */

#define MII_BRCM_FET_BRCMTEST		0x1f	/* Brcm test register */
#define MII_BRCM_FET_BT_SRE		0x0080	/* Shadow register enable */


/*** Shadow register definitions ***/

#define MII_BRCM_FET_SHDW_MISCCTRL	0x10	/* Shadow misc ctrl */
#define MII_BRCM_FET_SHDW_MC_FAME	0x4000	/* Force Auto MDIX enable */

#define MII_BRCM_FET_SHDW_AUXMODE4	0x1a	/* Auxiliary mode 4 */
#define MII_BRCM_FET_SHDW_AM4_LED_MASK	0x0003
#define MII_BRCM_FET_SHDW_AM4_LED_MODE1 0x0001

#define MII_BRCM_FET_SHDW_AUXSTAT2	0x1b	/* Auxiliary status 2 */
#define MII_BRCM_FET_SHDW_AS2_APDE	0x0020	/* Auto power down enable */

#endif /* _LINUX_BRCMPHY_H */
Commit	Line	Data
755ccb9d FF	1	#ifndef _LINUX_BRCMPHY_H
	2	#define _LINUX_BRCMPHY_H
	3
6a443a0f MC	4	#define PHY_ID_BCM50610 0x0143bd60
6a443a0f MC	5	#define PHY_ID_BCM50610M 0x0143bd70
7a938f80	6	#define PHY_ID_BCM5241 0x0143bc30
6a443a0f	7	#define PHY_ID_BCMAC131 0x0143bc70
fcb26ec5 DB	8	#define PHY_ID_BCM5481 0x0143bca0
	9	#define PHY_ID_BCM5482 0x0143bcb0
	10	#define PHY_ID_BCM5411 0x00206070
	11	#define PHY_ID_BCM5421 0x002060e0
	12	#define PHY_ID_BCM5464 0x002060b0
	13	#define PHY_ID_BCM5461 0x002060c0
6a443a0f MC	14	#define PHY_ID_BCM57780 0x03625d90
6a443a0f MC	15
b560a58c FF	16	#define PHY_ID_BCM7366 0x600d8490
	17	#define PHY_ID_BCM7439 0x600d8480
	18	#define PHY_ID_BCM7445 0x600d8510
b560a58c	19
6a443a0f MC	20	#define PHY_BCM_OUI_MASK 0xfffffc00
	21	#define PHY_BCM_OUI_1 0x00206000
	22	#define PHY_BCM_OUI_2 0x0143bc00
	23	#define PHY_BCM_OUI_3 0x03625c00
b560a58c FF	24	#define PHY_BCM_OUI_4 0x600d0000
b560a58c FF	25	#define PHY_BCM_OUI_5 0x03625e00
6a443a0f MC	26
6a443a0f MC	27
8649f13d MC	28	#define PHY_BCM_FLAGS_MODE_COPPER 0x00000001
	29	#define PHY_BCM_FLAGS_MODE_1000BX 0x00000002
	30	#define PHY_BCM_FLAGS_INTF_SGMII 0x00000010
	31	#define PHY_BCM_FLAGS_INTF_XAUI 0x00000020
	32	#define PHY_BRCM_WIRESPEED_ENABLE 0x00000100
	33	#define PHY_BRCM_AUTO_PWRDWN_ENABLE 0x00000200
32e5a8d6	34	#define PHY_BRCM_RX_REFCLK_UNUSED 0x00000400
8649f13d MC	35	#define PHY_BRCM_STD_IBND_DISABLE 0x00000800
	36	#define PHY_BRCM_EXT_IBND_RX_ENABLE 0x00001000
	37	#define PHY_BRCM_EXT_IBND_TX_ENABLE 0x00002000
63a14ce4	38	#define PHY_BRCM_CLEAR_RGMII_MODE 0x00004000
52fae083	39	#define PHY_BRCM_DIS_TXCRXC_NOENRGY 0x00008000
b560a58c FF	40	/* Broadcom BCM7xxx specific workarounds */
b560a58c FF	41	#define PHY_BRCM_100MBPS_WAR 0x00010000
8649f13d	42	#define PHY_BCM_FLAGS_VALID 0x80000000
755ccb9d	43
439d39a9 FF	44	/* Broadcom BCM54XX register definitions, common to most Broadcom PHYs */
	45	#define MII_BCM54XX_ECR 0x10 /* BCM54xx extended control register */
	46	#define MII_BCM54XX_ECR_IM 0x1000 /* Interrupt mask */
	47	#define MII_BCM54XX_ECR_IF 0x0800 /* Interrupt force */
	48
	49	#define MII_BCM54XX_ESR 0x11 /* BCM54xx extended status register */
	50	#define MII_BCM54XX_ESR_IS 0x1000 /* Interrupt status */
	51
	52	#define MII_BCM54XX_EXP_DATA 0x15 /* Expansion register data */
	53	#define MII_BCM54XX_EXP_SEL 0x17 /* Expansion register select */
	54	#define MII_BCM54XX_EXP_SEL_SSD 0x0e00 /* Secondary SerDes select */
	55	#define MII_BCM54XX_EXP_SEL_ER 0x0f00 /* Expansion register select */
	56
	57	#define MII_BCM54XX_AUX_CTL 0x18 /* Auxiliary control register */
	58	#define MII_BCM54XX_ISR 0x1a /* BCM54xx interrupt status register */
	59	#define MII_BCM54XX_IMR 0x1b /* BCM54xx interrupt mask register */
	60	#define MII_BCM54XX_INT_CRCERR 0x0001 /* CRC error */
	61	#define MII_BCM54XX_INT_LINK 0x0002 /* Link status changed */
	62	#define MII_BCM54XX_INT_SPEED 0x0004 /* Link speed change */
	63	#define MII_BCM54XX_INT_DUPLEX 0x0008 /* Duplex mode changed */
	64	#define MII_BCM54XX_INT_LRS 0x0010 /* Local receiver status changed */
	65	#define MII_BCM54XX_INT_RRS 0x0020 /* Remote receiver status changed */
	66	#define MII_BCM54XX_INT_SSERR 0x0040 /* Scrambler synchronization error */
	67	#define MII_BCM54XX_INT_UHCD 0x0080 /* Unsupported HCD negotiated */
	68	#define MII_BCM54XX_INT_NHCD 0x0100 /* No HCD */
	69	#define MII_BCM54XX_INT_NHCDL 0x0200 /* No HCD link */
	70	#define MII_BCM54XX_INT_ANPR 0x0400 /* Auto-negotiation page received */
	71	#define MII_BCM54XX_INT_LC 0x0800 /* All counters below 128 */
	72	#define MII_BCM54XX_INT_HC 0x1000 /* Counter above 32768 */
	73	#define MII_BCM54XX_INT_MDIX 0x2000 /* MDIX status change */
	74	#define MII_BCM54XX_INT_PSERR 0x4000 /* Pair swap error */
	75
	76	#define MII_BCM54XX_SHD 0x1c /* 0x1c shadow registers */
	77	#define MII_BCM54XX_SHD_WRITE 0x8000
	78	#define MII_BCM54XX_SHD_VAL(x) ((x & 0x1f) << 10)
	79	#define MII_BCM54XX_SHD_DATA(x) ((x & 0x3ff) << 0)
	80
	81	/*
	82	* AUXILIARY CONTROL SHADOW ACCESS REGISTERS. (PHY REG 0x18)
	83	*/
	84	#define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL 0x0000
	85	#define MII_BCM54XX_AUXCTL_ACTL_TX_6DB 0x0400
	86	#define MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA 0x0800
	87
	88	#define MII_BCM54XX_AUXCTL_MISC_WREN 0x8000
	89	#define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX 0x0200
	90	#define MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC 0x7000
	91	#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC 0x0007
	92
	93	#define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL 0x0000
	94
3af20efc FF	95	/*
	96	* Broadcom LED source encodings. These are used in BCM5461, BCM5481,
	97	* BCM5482, and possibly some others.
	98	*/
	99	#define BCM_LED_SRC_LINKSPD1 0x0
	100	#define BCM_LED_SRC_LINKSPD2 0x1
	101	#define BCM_LED_SRC_XMITLED 0x2
	102	#define BCM_LED_SRC_ACTIVITYLED 0x3
	103	#define BCM_LED_SRC_FDXLED 0x4
	104	#define BCM_LED_SRC_SLAVE 0x5
	105	#define BCM_LED_SRC_INTR 0x6
	106	#define BCM_LED_SRC_QUALITY 0x7
	107	#define BCM_LED_SRC_RCVLED 0x8
	108	#define BCM_LED_SRC_MULTICOLOR1 0xa
	109	#define BCM_LED_SRC_OPENSHORT 0xb
	110	#define BCM_LED_SRC_OFF 0xe /* Tied high */
	111	#define BCM_LED_SRC_ON 0xf /* Tied low */
	112
	113
	114	/*
	115	* BCM5482: Shadow registers
	116	* Shadow values go into bits [14:10] of register 0x1c to select a shadow
	117	* register to access.
	118	*/
	119	/* 00101: Spare Control Register 3 */
	120	#define BCM54XX_SHD_SCR3 0x05
	121	#define BCM54XX_SHD_SCR3_DEF_CLK125 0x0001
	122	#define BCM54XX_SHD_SCR3_DLLAPD_DIS 0x0002
	123	#define BCM54XX_SHD_SCR3_TRDDAPD 0x0004
	124
	125	/* 01010: Auto Power-Down */
	126	#define BCM54XX_SHD_APD 0x0a
	127	#define BCM54XX_SHD_APD_EN 0x0020
	128
	129	#define BCM5482_SHD_LEDS1 0x0d /* 01101: LED Selector 1 */
	130	/* LED3 / ~LINKSPD[2] selector */
	131	#define BCM5482_SHD_LEDS1_LED3(src) ((src & 0xf) << 4)
	132	/* LED1 / ~LINKSPD[1] selector */
	133	#define BCM5482_SHD_LEDS1_LED1(src) ((src & 0xf) << 0)
	134	#define BCM54XX_SHD_RGMII_MODE 0x0b /* 01011: RGMII Mode Selector */
	135	#define BCM5482_SHD_SSD 0x14 /* 10100: Secondary SerDes control */
	136	#define BCM5482_SHD_SSD_LEDM 0x0008 /* SSD LED Mode enable */
	137	#define BCM5482_SHD_SSD_EN 0x0001 /* SSD enable */
	138	#define BCM5482_SHD_MODE 0x1f /* 11111: Mode Control Register */
	139	#define BCM5482_SHD_MODE_1000BX 0x0001 /* Enable 1000BASE-X registers */
	140
	141
	142	/*
	143	* EXPANSION SHADOW ACCESS REGISTERS. (PHY REG 0x15, 0x16, and 0x17)
	144	*/
	145	#define MII_BCM54XX_EXP_AADJ1CH0 0x001f
	146	#define MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN 0x0200
	147	#define MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF 0x0100
	148	#define MII_BCM54XX_EXP_AADJ1CH3 0x601f
	149	#define MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ 0x0002
	150	#define MII_BCM54XX_EXP_EXP08 0x0F08
	151	#define MII_BCM54XX_EXP_EXP08_RJCT_2MHZ 0x0001
	152	#define MII_BCM54XX_EXP_EXP08_EARLY_DAC_WAKE 0x0200
	153	#define MII_BCM54XX_EXP_EXP75 0x0f75
	154	#define MII_BCM54XX_EXP_EXP75_VDACCTRL 0x003c
	155	#define MII_BCM54XX_EXP_EXP75_CM_OSC 0x0001
	156	#define MII_BCM54XX_EXP_EXP96 0x0f96
	157	#define MII_BCM54XX_EXP_EXP96_MYST 0x0010
	158	#define MII_BCM54XX_EXP_EXP97 0x0f97
159	#define MII_BCM54XX_EXP_EXP97_MYST 0x0c0c
160
161	/*
162	* BCM5482: Secondary SerDes registers
163	*/
164	#define BCM5482_SSD_1000BX_CTL 0x00 /* 1000BASE-X Control */
165	#define BCM5482_SSD_1000BX_CTL_PWRDOWN 0x0800 /* Power-down SSD */
166	#define BCM5482_SSD_SGMII_SLAVE 0x15 /* SGMII Slave Register */
167	#define BCM5482_SSD_SGMII_SLAVE_EN 0x0002 /* Slave mode enable */
168	#define BCM5482_SSD_SGMII_SLAVE_AD 0x0001 /* Slave auto-detection */
169
170
171	/*****************************************************************************/
172	/* Fast Ethernet Transceiver definitions. */
173	/*****************************************************************************/
174
175	#define MII_BRCM_FET_INTREG 0x1a /* Interrupt register */
176	#define MII_BRCM_FET_IR_MASK 0x0100 /* Mask all interrupts */
177	#define MII_BRCM_FET_IR_LINK_EN 0x0200 /* Link status change enable */
178	#define MII_BRCM_FET_IR_SPEED_EN 0x0400 /* Link speed change enable */
179	#define MII_BRCM_FET_IR_DUPLEX_EN 0x0800 /* Duplex mode change enable */
180	#define MII_BRCM_FET_IR_ENABLE 0x4000 /* Interrupt enable */
181
182	#define MII_BRCM_FET_BRCMTEST 0x1f /* Brcm test register */
183	#define MII_BRCM_FET_BT_SRE 0x0080 /* Shadow register enable */
184
185
186	/* Shadow register definitions */
187
188	#define MII_BRCM_FET_SHDW_MISCCTRL 0x10 /* Shadow misc ctrl */
189	#define MII_BRCM_FET_SHDW_MC_FAME 0x4000 /* Force Auto MDIX enable */
190
191	#define MII_BRCM_FET_SHDW_AUXMODE4 0x1a /* Auxiliary mode 4 */
192	#define MII_BRCM_FET_SHDW_AM4_LED_MASK 0x0003
193	#define MII_BRCM_FET_SHDW_AM4_LED_MODE1 0x0001
194
195	#define MII_BRCM_FET_SHDW_AUXSTAT2 0x1b /* Auxiliary status 2 */
196	#define MII_BRCM_FET_SHDW_AS2_APDE 0x0020 /* Auto power down enable */
197
755ccb9d	198	#endif /* _LINUX_BRCMPHY_H */