[linux-2.6-block.git] / include / linux / atmel-ssc.h

#ifndef __INCLUDE_ATMEL_SSC_H
#define __INCLUDE_ATMEL_SSC_H

#include <linux/platform_device.h>
#include <linux/list.h>
#include <linux/io.h>

struct atmel_ssc_platform_data {
	int			use_dma;
};

struct ssc_device {
	struct list_head	list;
	dma_addr_t		phybase;
	void __iomem		*regs;
	struct platform_device	*pdev;
	struct atmel_ssc_platform_data *pdata;
	struct clk		*clk;
	int			user;
	int			irq;
	bool			clk_from_rk_pin;
};

struct ssc_device * __must_check ssc_request(unsigned int ssc_num);
void ssc_free(struct ssc_device *ssc);

/* SSC register offsets */

/* SSC Control Register */
#define SSC_CR				0x00000000
#define SSC_CR_RXDIS_SIZE			 1
#define SSC_CR_RXDIS_OFFSET			 1
#define SSC_CR_RXEN_SIZE			 1
#define SSC_CR_RXEN_OFFSET			 0
#define SSC_CR_SWRST_SIZE			 1
#define SSC_CR_SWRST_OFFSET			15
#define SSC_CR_TXDIS_SIZE			 1
#define SSC_CR_TXDIS_OFFSET			 9
#define SSC_CR_TXEN_SIZE			 1
#define SSC_CR_TXEN_OFFSET			 8

/* SSC Clock Mode Register */
#define SSC_CMR				0x00000004
#define SSC_CMR_DIV_SIZE			12
#define SSC_CMR_DIV_OFFSET			 0

/* SSC Receive Clock Mode Register */
#define SSC_RCMR			0x00000010
#define SSC_RCMR_CKG_SIZE			 2
#define SSC_RCMR_CKG_OFFSET			 6
#define SSC_RCMR_CKI_SIZE			 1
#define SSC_RCMR_CKI_OFFSET			 5
#define SSC_RCMR_CKO_SIZE			 3
#define SSC_RCMR_CKO_OFFSET			 2
#define SSC_RCMR_CKS_SIZE			 2
#define SSC_RCMR_CKS_OFFSET			 0
#define SSC_RCMR_PERIOD_SIZE			 8
#define SSC_RCMR_PERIOD_OFFSET			24
#define SSC_RCMR_START_SIZE			 4
#define SSC_RCMR_START_OFFSET			 8
#define SSC_RCMR_STOP_SIZE			 1
#define SSC_RCMR_STOP_OFFSET			12
#define SSC_RCMR_STTDLY_SIZE			 8
#define SSC_RCMR_STTDLY_OFFSET			16

/* SSC Receive Frame Mode Register */
#define SSC_RFMR			0x00000014
#define SSC_RFMR_DATLEN_SIZE			 5
#define SSC_RFMR_DATLEN_OFFSET			 0
#define SSC_RFMR_DATNB_SIZE			 4
#define SSC_RFMR_DATNB_OFFSET			 8
#define SSC_RFMR_FSEDGE_SIZE			 1
#define SSC_RFMR_FSEDGE_OFFSET			24
#define SSC_RFMR_FSLEN_SIZE			 4
#define SSC_RFMR_FSLEN_OFFSET			16
#define SSC_RFMR_FSOS_SIZE			 4
#define SSC_RFMR_FSOS_OFFSET			20
#define SSC_RFMR_LOOP_SIZE			 1
#define SSC_RFMR_LOOP_OFFSET			 5
#define SSC_RFMR_MSBF_SIZE			 1
#define SSC_RFMR_MSBF_OFFSET			 7

/* SSC Transmit Clock Mode Register */
#define SSC_TCMR			0x00000018
#define SSC_TCMR_CKG_SIZE			 2
#define SSC_TCMR_CKG_OFFSET			 6
#define SSC_TCMR_CKI_SIZE			 1
#define SSC_TCMR_CKI_OFFSET			 5
#define SSC_TCMR_CKO_SIZE			 3
#define SSC_TCMR_CKO_OFFSET			 2
#define SSC_TCMR_CKS_SIZE			 2
#define SSC_TCMR_CKS_OFFSET			 0
#define SSC_TCMR_PERIOD_SIZE			 8
#define SSC_TCMR_PERIOD_OFFSET			24
#define SSC_TCMR_START_SIZE			 4
#define SSC_TCMR_START_OFFSET			 8
#define SSC_TCMR_STTDLY_SIZE			 8
#define SSC_TCMR_STTDLY_OFFSET			16

/* SSC Transmit Frame Mode Register */
#define SSC_TFMR			0x0000001c
#define SSC_TFMR_DATDEF_SIZE			 1
#define SSC_TFMR_DATDEF_OFFSET			 5
#define SSC_TFMR_DATLEN_SIZE			 5
#define SSC_TFMR_DATLEN_OFFSET			 0
#define SSC_TFMR_DATNB_SIZE			 4
#define SSC_TFMR_DATNB_OFFSET			 8
#define SSC_TFMR_FSDEN_SIZE			 1
#define SSC_TFMR_FSDEN_OFFSET			23
#define SSC_TFMR_FSEDGE_SIZE			 1
#define SSC_TFMR_FSEDGE_OFFSET			24
#define SSC_TFMR_FSLEN_SIZE			 4
#define SSC_TFMR_FSLEN_OFFSET			16
#define SSC_TFMR_FSOS_SIZE			 3
#define SSC_TFMR_FSOS_OFFSET			20
#define SSC_TFMR_MSBF_SIZE			 1
#define SSC_TFMR_MSBF_OFFSET			 7

/* SSC Receive Hold Register */
#define SSC_RHR				0x00000020
#define SSC_RHR_RDAT_SIZE			32
#define SSC_RHR_RDAT_OFFSET			 0

/* SSC Transmit Hold Register */
#define SSC_THR				0x00000024
#define SSC_THR_TDAT_SIZE			32
#define SSC_THR_TDAT_OFFSET			 0

/* SSC Receive Sync. Holding Register */
#define SSC_RSHR			0x00000030
#define SSC_RSHR_RSDAT_SIZE			16
#define SSC_RSHR_RSDAT_OFFSET			 0

/* SSC Transmit Sync. Holding Register */
#define SSC_TSHR			0x00000034
#define SSC_TSHR_TSDAT_SIZE			16
#define SSC_TSHR_RSDAT_OFFSET			 0

/* SSC Receive Compare 0 Register */
#define SSC_RC0R			0x00000038
#define SSC_RC0R_CP0_SIZE			16
#define SSC_RC0R_CP0_OFFSET			 0

/* SSC Receive Compare 1 Register */
#define SSC_RC1R			0x0000003c
#define SSC_RC1R_CP1_SIZE			16
#define SSC_RC1R_CP1_OFFSET			 0

/* SSC Status Register */
#define SSC_SR				0x00000040
#define SSC_SR_CP0_SIZE				 1
#define SSC_SR_CP0_OFFSET			 8
#define SSC_SR_CP1_SIZE				 1
#define SSC_SR_CP1_OFFSET			 9
#define SSC_SR_ENDRX_SIZE			 1
#define SSC_SR_ENDRX_OFFSET			 6
#define SSC_SR_ENDTX_SIZE			 1
#define SSC_SR_ENDTX_OFFSET			 2
#define SSC_SR_OVRUN_SIZE			 1
#define SSC_SR_OVRUN_OFFSET			 5
#define SSC_SR_RXBUFF_SIZE			 1
#define SSC_SR_RXBUFF_OFFSET			 7
#define SSC_SR_RXEN_SIZE			 1
#define SSC_SR_RXEN_OFFSET			17
#define SSC_SR_RXRDY_SIZE			 1
#define SSC_SR_RXRDY_OFFSET			 4
#define SSC_SR_RXSYN_SIZE			 1
#define SSC_SR_RXSYN_OFFSET			11
#define SSC_SR_TXBUFE_SIZE			 1
#define SSC_SR_TXBUFE_OFFSET			 3
#define SSC_SR_TXEMPTY_SIZE			 1
#define SSC_SR_TXEMPTY_OFFSET			 1
#define SSC_SR_TXEN_SIZE			 1
#define SSC_SR_TXEN_OFFSET			16
#define SSC_SR_TXRDY_SIZE			 1
#define SSC_SR_TXRDY_OFFSET			 0
#define SSC_SR_TXSYN_SIZE			 1
#define SSC_SR_TXSYN_OFFSET			10

/* SSC Interrupt Enable Register */
#define SSC_IER				0x00000044
#define SSC_IER_CP0_SIZE			 1
#define SSC_IER_CP0_OFFSET			 8
#define SSC_IER_CP1_SIZE			 1
#define SSC_IER_CP1_OFFSET			 9
#define SSC_IER_ENDRX_SIZE			 1
#define SSC_IER_ENDRX_OFFSET			 6
#define SSC_IER_ENDTX_SIZE			 1
#define SSC_IER_ENDTX_OFFSET			 2
#define SSC_IER_OVRUN_SIZE			 1
#define SSC_IER_OVRUN_OFFSET			 5
#define SSC_IER_RXBUFF_SIZE			 1
#define SSC_IER_RXBUFF_OFFSET			 7
#define SSC_IER_RXRDY_SIZE			 1
#define SSC_IER_RXRDY_OFFSET			 4
#define SSC_IER_RXSYN_SIZE			 1
#define SSC_IER_RXSYN_OFFSET			11
#define SSC_IER_TXBUFE_SIZE			 1
#define SSC_IER_TXBUFE_OFFSET			 3
#define SSC_IER_TXEMPTY_SIZE			 1
#define SSC_IER_TXEMPTY_OFFSET			 1
#define SSC_IER_TXRDY_SIZE			 1
#define SSC_IER_TXRDY_OFFSET			 0
#define SSC_IER_TXSYN_SIZE			 1
#define SSC_IER_TXSYN_OFFSET			10

/* SSC Interrupt Disable Register */
#define SSC_IDR				0x00000048
#define SSC_IDR_CP0_SIZE			 1
#define SSC_IDR_CP0_OFFSET			 8
#define SSC_IDR_CP1_SIZE			 1
#define SSC_IDR_CP1_OFFSET			 9
#define SSC_IDR_ENDRX_SIZE			 1
#define SSC_IDR_ENDRX_OFFSET			 6
#define SSC_IDR_ENDTX_SIZE			 1
#define SSC_IDR_ENDTX_OFFSET			 2
#define SSC_IDR_OVRUN_SIZE			 1
#define SSC_IDR_OVRUN_OFFSET			 5
#define SSC_IDR_RXBUFF_SIZE			 1
#define SSC_IDR_RXBUFF_OFFSET			 7
#define SSC_IDR_RXRDY_SIZE			 1
#define SSC_IDR_RXRDY_OFFSET			 4
#define SSC_IDR_RXSYN_SIZE			 1
#define SSC_IDR_RXSYN_OFFSET			11
#define SSC_IDR_TXBUFE_SIZE			 1
#define SSC_IDR_TXBUFE_OFFSET			 3
#define SSC_IDR_TXEMPTY_SIZE			 1
#define SSC_IDR_TXEMPTY_OFFSET			 1
#define SSC_IDR_TXRDY_SIZE			 1
#define SSC_IDR_TXRDY_OFFSET			 0
#define SSC_IDR_TXSYN_SIZE			 1
#define SSC_IDR_TXSYN_OFFSET			10

/* SSC Interrupt Mask Register */
#define SSC_IMR				0x0000004c
#define SSC_IMR_CP0_SIZE			 1
#define SSC_IMR_CP0_OFFSET			 8
#define SSC_IMR_CP1_SIZE			 1
#define SSC_IMR_CP1_OFFSET			 9
#define SSC_IMR_ENDRX_SIZE			 1
#define SSC_IMR_ENDRX_OFFSET			 6
#define SSC_IMR_ENDTX_SIZE			 1
#define SSC_IMR_ENDTX_OFFSET			 2
#define SSC_IMR_OVRUN_SIZE			 1
#define SSC_IMR_OVRUN_OFFSET			 5
#define SSC_IMR_RXBUFF_SIZE			 1
#define SSC_IMR_RXBUFF_OFFSET			 7
#define SSC_IMR_RXRDY_SIZE			 1
#define SSC_IMR_RXRDY_OFFSET			 4
#define SSC_IMR_RXSYN_SIZE			 1
#define SSC_IMR_RXSYN_OFFSET			11
#define SSC_IMR_TXBUFE_SIZE			 1
#define SSC_IMR_TXBUFE_OFFSET			 3
#define SSC_IMR_TXEMPTY_SIZE			 1
#define SSC_IMR_TXEMPTY_OFFSET			 1
#define SSC_IMR_TXRDY_SIZE			 1
#define SSC_IMR_TXRDY_OFFSET			 0
#define SSC_IMR_TXSYN_SIZE			 1
#define SSC_IMR_TXSYN_OFFSET			10

/* SSC PDC Receive Pointer Register */
#define SSC_PDC_RPR			0x00000100

/* SSC PDC Receive Counter Register */
#define SSC_PDC_RCR			0x00000104

/* SSC PDC Transmit Pointer Register */
#define SSC_PDC_TPR			0x00000108

/* SSC PDC Receive Next Pointer Register */
#define SSC_PDC_RNPR			0x00000110

/* SSC PDC Receive Next Counter Register */
#define SSC_PDC_RNCR			0x00000114

/* SSC PDC Transmit Counter Register */
#define SSC_PDC_TCR			0x0000010c

/* SSC PDC Transmit Next Pointer Register */
#define SSC_PDC_TNPR			0x00000118

/* SSC PDC Transmit Next Counter Register */
#define SSC_PDC_TNCR			0x0000011c

/* SSC PDC Transfer Control Register */
#define SSC_PDC_PTCR			0x00000120
#define SSC_PDC_PTCR_RXTDIS_SIZE		 1
#define SSC_PDC_PTCR_RXTDIS_OFFSET		 1
#define SSC_PDC_PTCR_RXTEN_SIZE			 1
#define SSC_PDC_PTCR_RXTEN_OFFSET		 0
#define SSC_PDC_PTCR_TXTDIS_SIZE		 1
#define SSC_PDC_PTCR_TXTDIS_OFFSET		 9
#define SSC_PDC_PTCR_TXTEN_SIZE			 1
#define SSC_PDC_PTCR_TXTEN_OFFSET		 8

/* SSC PDC Transfer Status Register */
#define SSC_PDC_PTSR			0x00000124
#define SSC_PDC_PTSR_RXTEN_SIZE			 1
#define SSC_PDC_PTSR_RXTEN_OFFSET		 0
#define SSC_PDC_PTSR_TXTEN_SIZE			 1
#define SSC_PDC_PTSR_TXTEN_OFFSET		 8

/* Bit manipulation macros */
#define SSC_BIT(name)					\
	(1 << SSC_##name##_OFFSET)
#define SSC_BF(name, value)				\
	(((value) & ((1 << SSC_##name##_SIZE) - 1))	\
	 << SSC_##name##_OFFSET)
#define SSC_BFEXT(name, value)				\
	(((value) >> SSC_##name##_OFFSET)		\
	 & ((1 << SSC_##name##_SIZE) - 1))
#define SSC_BFINS(name, value, old)			\
	(((old) & ~(((1 << SSC_##name##_SIZE) - 1)	\
	<< SSC_##name##_OFFSET)) | SSC_BF(name, value))

/* Register access macros */
#define ssc_readl(base, reg)		__raw_readl(base + SSC_##reg)
#define ssc_writel(base, reg, value)	__raw_writel((value), base + SSC_##reg)

#endif /* __INCLUDE_ATMEL_SSC_H */
Commit	Line	Data
eb1f2930 HCE	1	#ifndef __INCLUDE_ATMEL_SSC_H
	2	#define __INCLUDE_ATMEL_SSC_H
	3
	4	#include <linux/platform_device.h>
	5	#include <linux/list.h>
b969afc8	6	#include <linux/io.h>
eb1f2930	7
636036d2 BS	8	struct atmel_ssc_platform_data {
	9	int use_dma;
	10	};
	11
eb1f2930 HCE	12	struct ssc_device {
eb1f2930 HCE	13	struct list_head list;
10175b3b	14	dma_addr_t phybase;
eb1f2930 HCE	15	void __iomem *regs;
eb1f2930 HCE	16	struct platform_device *pdev;
636036d2	17	struct atmel_ssc_platform_data *pdata;
eb1f2930 HCE	18	struct clk *clk;
	19	int user;
	20	int irq;
048d4ff8	21	bool clk_from_rk_pin;
eb1f2930 HCE	22	};
	23
	24	struct ssc_device * __must_check ssc_request(unsigned int ssc_num);
	25	void ssc_free(struct ssc_device *ssc);
	26
	27	/* SSC register offsets */
	28
	29	/* SSC Control Register */
	30	#define SSC_CR 0x00000000
	31	#define SSC_CR_RXDIS_SIZE 1
	32	#define SSC_CR_RXDIS_OFFSET 1
	33	#define SSC_CR_RXEN_SIZE 1
	34	#define SSC_CR_RXEN_OFFSET 0
	35	#define SSC_CR_SWRST_SIZE 1
	36	#define SSC_CR_SWRST_OFFSET 15
	37	#define SSC_CR_TXDIS_SIZE 1
	38	#define SSC_CR_TXDIS_OFFSET 9
	39	#define SSC_CR_TXEN_SIZE 1
	40	#define SSC_CR_TXEN_OFFSET 8
	41
	42	/* SSC Clock Mode Register */
	43	#define SSC_CMR 0x00000004
	44	#define SSC_CMR_DIV_SIZE 12
	45	#define SSC_CMR_DIV_OFFSET 0
	46
	47	/* SSC Receive Clock Mode Register */
	48	#define SSC_RCMR 0x00000010
	49	#define SSC_RCMR_CKG_SIZE 2
	50	#define SSC_RCMR_CKG_OFFSET 6
	51	#define SSC_RCMR_CKI_SIZE 1
	52	#define SSC_RCMR_CKI_OFFSET 5
	53	#define SSC_RCMR_CKO_SIZE 3
	54	#define SSC_RCMR_CKO_OFFSET 2
	55	#define SSC_RCMR_CKS_SIZE 2
	56	#define SSC_RCMR_CKS_OFFSET 0
	57	#define SSC_RCMR_PERIOD_SIZE 8
	58	#define SSC_RCMR_PERIOD_OFFSET 24
	59	#define SSC_RCMR_START_SIZE 4
	60	#define SSC_RCMR_START_OFFSET 8
	61	#define SSC_RCMR_STOP_SIZE 1
	62	#define SSC_RCMR_STOP_OFFSET 12
	63	#define SSC_RCMR_STTDLY_SIZE 8
	64	#define SSC_RCMR_STTDLY_OFFSET 16
	65
	66	/* SSC Receive Frame Mode Register */
	67	#define SSC_RFMR 0x00000014
	68	#define SSC_RFMR_DATLEN_SIZE 5
	69	#define SSC_RFMR_DATLEN_OFFSET 0
	70	#define SSC_RFMR_DATNB_SIZE 4
	71	#define SSC_RFMR_DATNB_OFFSET 8
	72	#define SSC_RFMR_FSEDGE_SIZE 1
	73	#define SSC_RFMR_FSEDGE_OFFSET 24
	74	#define SSC_RFMR_FSLEN_SIZE 4
	75	#define SSC_RFMR_FSLEN_OFFSET 16
	76	#define SSC_RFMR_FSOS_SIZE 4
	77	#define SSC_RFMR_FSOS_OFFSET 20
	78	#define SSC_RFMR_LOOP_SIZE 1
	79	#define SSC_RFMR_LOOP_OFFSET 5
	80	#define SSC_RFMR_MSBF_SIZE 1
	81	#define SSC_RFMR_MSBF_OFFSET 7
	82
	83	/* SSC Transmit Clock Mode Register */
	84	#define SSC_TCMR 0x00000018
	85	#define SSC_TCMR_CKG_SIZE 2
86	#define SSC_TCMR_CKG_OFFSET 6
87	#define SSC_TCMR_CKI_SIZE 1
88	#define SSC_TCMR_CKI_OFFSET 5
89	#define SSC_TCMR_CKO_SIZE 3
90	#define SSC_TCMR_CKO_OFFSET 2
91	#define SSC_TCMR_CKS_SIZE 2
92	#define SSC_TCMR_CKS_OFFSET 0
93	#define SSC_TCMR_PERIOD_SIZE 8
94	#define SSC_TCMR_PERIOD_OFFSET 24
95	#define SSC_TCMR_START_SIZE 4
96	#define SSC_TCMR_START_OFFSET 8
97	#define SSC_TCMR_STTDLY_SIZE 8
98	#define SSC_TCMR_STTDLY_OFFSET 16
99
100	/* SSC Transmit Frame Mode Register */
101	#define SSC_TFMR 0x0000001c
102	#define SSC_TFMR_DATDEF_SIZE 1
103	#define SSC_TFMR_DATDEF_OFFSET 5
104	#define SSC_TFMR_DATLEN_SIZE 5
105	#define SSC_TFMR_DATLEN_OFFSET 0
106	#define SSC_TFMR_DATNB_SIZE 4
107	#define SSC_TFMR_DATNB_OFFSET 8
108	#define SSC_TFMR_FSDEN_SIZE 1
109	#define SSC_TFMR_FSDEN_OFFSET 23
110	#define SSC_TFMR_FSEDGE_SIZE 1
111	#define SSC_TFMR_FSEDGE_OFFSET 24
112	#define SSC_TFMR_FSLEN_SIZE 4
113	#define SSC_TFMR_FSLEN_OFFSET 16
114	#define SSC_TFMR_FSOS_SIZE 3
115	#define SSC_TFMR_FSOS_OFFSET 20
116	#define SSC_TFMR_MSBF_SIZE 1
117	#define SSC_TFMR_MSBF_OFFSET 7
118
119	/* SSC Receive Hold Register */
120	#define SSC_RHR 0x00000020
121	#define SSC_RHR_RDAT_SIZE 32
122	#define SSC_RHR_RDAT_OFFSET 0
123
124	/* SSC Transmit Hold Register */
125	#define SSC_THR 0x00000024
126	#define SSC_THR_TDAT_SIZE 32
127	#define SSC_THR_TDAT_OFFSET 0
128
129	/* SSC Receive Sync. Holding Register */
130	#define SSC_RSHR 0x00000030
131	#define SSC_RSHR_RSDAT_SIZE 16
132	#define SSC_RSHR_RSDAT_OFFSET 0
133
134	/* SSC Transmit Sync. Holding Register */
135	#define SSC_TSHR 0x00000034
136	#define SSC_TSHR_TSDAT_SIZE 16
137	#define SSC_TSHR_RSDAT_OFFSET 0
138
139	/* SSC Receive Compare 0 Register */
140	#define SSC_RC0R 0x00000038
141	#define SSC_RC0R_CP0_SIZE 16
142	#define SSC_RC0R_CP0_OFFSET 0
143
144	/* SSC Receive Compare 1 Register */
145	#define SSC_RC1R 0x0000003c
146	#define SSC_RC1R_CP1_SIZE 16
147	#define SSC_RC1R_CP1_OFFSET 0
148
149	/* SSC Status Register */
150	#define SSC_SR 0x00000040
151	#define SSC_SR_CP0_SIZE 1
152	#define SSC_SR_CP0_OFFSET 8
153	#define SSC_SR_CP1_SIZE 1
154	#define SSC_SR_CP1_OFFSET 9
155	#define SSC_SR_ENDRX_SIZE 1
156	#define SSC_SR_ENDRX_OFFSET 6
157	#define SSC_SR_ENDTX_SIZE 1
158	#define SSC_SR_ENDTX_OFFSET 2
159	#define SSC_SR_OVRUN_SIZE 1
160	#define SSC_SR_OVRUN_OFFSET 5
161	#define SSC_SR_RXBUFF_SIZE 1
162	#define SSC_SR_RXBUFF_OFFSET 7
163	#define SSC_SR_RXEN_SIZE 1
164	#define SSC_SR_RXEN_OFFSET 17
165	#define SSC_SR_RXRDY_SIZE 1
166	#define SSC_SR_RXRDY_OFFSET 4
167	#define SSC_SR_RXSYN_SIZE 1
168	#define SSC_SR_RXSYN_OFFSET 11
169	#define SSC_SR_TXBUFE_SIZE 1
170	#define SSC_SR_TXBUFE_OFFSET 3
171	#define SSC_SR_TXEMPTY_SIZE 1
172	#define SSC_SR_TXEMPTY_OFFSET 1
173	#define SSC_SR_TXEN_SIZE 1
174	#define SSC_SR_TXEN_OFFSET 16
175	#define SSC_SR_TXRDY_SIZE 1
176	#define SSC_SR_TXRDY_OFFSET 0
177	#define SSC_SR_TXSYN_SIZE 1
178	#define SSC_SR_TXSYN_OFFSET 10
179
180	/* SSC Interrupt Enable Register */
181	#define SSC_IER 0x00000044
182	#define SSC_IER_CP0_SIZE 1
183	#define SSC_IER_CP0_OFFSET 8
184	#define SSC_IER_CP1_SIZE 1
185	#define SSC_IER_CP1_OFFSET 9
186	#define SSC_IER_ENDRX_SIZE 1
187	#define SSC_IER_ENDRX_OFFSET 6
188	#define SSC_IER_ENDTX_SIZE 1
189	#define SSC_IER_ENDTX_OFFSET 2
190	#define SSC_IER_OVRUN_SIZE 1
191	#define SSC_IER_OVRUN_OFFSET 5
192	#define SSC_IER_RXBUFF_SIZE 1
193	#define SSC_IER_RXBUFF_OFFSET 7
194	#define SSC_IER_RXRDY_SIZE 1
195	#define SSC_IER_RXRDY_OFFSET 4
196	#define SSC_IER_RXSYN_SIZE 1
197	#define SSC_IER_RXSYN_OFFSET 11
198	#define SSC_IER_TXBUFE_SIZE 1
199	#define SSC_IER_TXBUFE_OFFSET 3
200	#define SSC_IER_TXEMPTY_SIZE 1
201	#define SSC_IER_TXEMPTY_OFFSET 1
202	#define SSC_IER_TXRDY_SIZE 1
203	#define SSC_IER_TXRDY_OFFSET 0
204	#define SSC_IER_TXSYN_SIZE 1
205	#define SSC_IER_TXSYN_OFFSET 10
206
207	/* SSC Interrupt Disable Register */
208	#define SSC_IDR 0x00000048
209	#define SSC_IDR_CP0_SIZE 1
210	#define SSC_IDR_CP0_OFFSET 8
211	#define SSC_IDR_CP1_SIZE 1
212	#define SSC_IDR_CP1_OFFSET 9
213	#define SSC_IDR_ENDRX_SIZE 1
214	#define SSC_IDR_ENDRX_OFFSET 6
215	#define SSC_IDR_ENDTX_SIZE 1
216	#define SSC_IDR_ENDTX_OFFSET 2
217	#define SSC_IDR_OVRUN_SIZE 1
218	#define SSC_IDR_OVRUN_OFFSET 5
219	#define SSC_IDR_RXBUFF_SIZE 1
220	#define SSC_IDR_RXBUFF_OFFSET 7
221	#define SSC_IDR_RXRDY_SIZE 1
222	#define SSC_IDR_RXRDY_OFFSET 4
223	#define SSC_IDR_RXSYN_SIZE 1
224	#define SSC_IDR_RXSYN_OFFSET 11
225	#define SSC_IDR_TXBUFE_SIZE 1
226	#define SSC_IDR_TXBUFE_OFFSET 3
227	#define SSC_IDR_TXEMPTY_SIZE 1
228	#define SSC_IDR_TXEMPTY_OFFSET 1
229	#define SSC_IDR_TXRDY_SIZE 1
230	#define SSC_IDR_TXRDY_OFFSET 0
231	#define SSC_IDR_TXSYN_SIZE 1
232	#define SSC_IDR_TXSYN_OFFSET 10
233
234	/* SSC Interrupt Mask Register */
235	#define SSC_IMR 0x0000004c
236	#define SSC_IMR_CP0_SIZE 1
237	#define SSC_IMR_CP0_OFFSET 8
238	#define SSC_IMR_CP1_SIZE 1
239	#define SSC_IMR_CP1_OFFSET 9
240	#define SSC_IMR_ENDRX_SIZE 1
241	#define SSC_IMR_ENDRX_OFFSET 6
242	#define SSC_IMR_ENDTX_SIZE 1
243	#define SSC_IMR_ENDTX_OFFSET 2
244	#define SSC_IMR_OVRUN_SIZE 1
245	#define SSC_IMR_OVRUN_OFFSET 5
246	#define SSC_IMR_RXBUFF_SIZE 1
247	#define SSC_IMR_RXBUFF_OFFSET 7
248	#define SSC_IMR_RXRDY_SIZE 1
249	#define SSC_IMR_RXRDY_OFFSET 4
250	#define SSC_IMR_RXSYN_SIZE 1
251	#define SSC_IMR_RXSYN_OFFSET 11
252	#define SSC_IMR_TXBUFE_SIZE 1
253	#define SSC_IMR_TXBUFE_OFFSET 3
254	#define SSC_IMR_TXEMPTY_SIZE 1
255	#define SSC_IMR_TXEMPTY_OFFSET 1
256	#define SSC_IMR_TXRDY_SIZE 1
257	#define SSC_IMR_TXRDY_OFFSET 0
258	#define SSC_IMR_TXSYN_SIZE 1
259	#define SSC_IMR_TXSYN_OFFSET 10
260
261	/* SSC PDC Receive Pointer Register */
262	#define SSC_PDC_RPR 0x00000100
263
264	/* SSC PDC Receive Counter Register */
265	#define SSC_PDC_RCR 0x00000104
266
267	/* SSC PDC Transmit Pointer Register */
268	#define SSC_PDC_TPR 0x00000108
269
270	/* SSC PDC Receive Next Pointer Register */
271	#define SSC_PDC_RNPR 0x00000110
272
273	/* SSC PDC Receive Next Counter Register */
274	#define SSC_PDC_RNCR 0x00000114
275
276	/* SSC PDC Transmit Counter Register */
277	#define SSC_PDC_TCR 0x0000010c
278
279	/* SSC PDC Transmit Next Pointer Register */
280	#define SSC_PDC_TNPR 0x00000118
281
282	/* SSC PDC Transmit Next Counter Register */
283	#define SSC_PDC_TNCR 0x0000011c
284
285	/* SSC PDC Transfer Control Register */
286	#define SSC_PDC_PTCR 0x00000120
287	#define SSC_PDC_PTCR_RXTDIS_SIZE 1
288	#define SSC_PDC_PTCR_RXTDIS_OFFSET 1
289	#define SSC_PDC_PTCR_RXTEN_SIZE 1
290	#define SSC_PDC_PTCR_RXTEN_OFFSET 0
291	#define SSC_PDC_PTCR_TXTDIS_SIZE 1
292	#define SSC_PDC_PTCR_TXTDIS_OFFSET 9
293	#define SSC_PDC_PTCR_TXTEN_SIZE 1
294	#define SSC_PDC_PTCR_TXTEN_OFFSET 8
295
296	/* SSC PDC Transfer Status Register */
297	#define SSC_PDC_PTSR 0x00000124
298	#define SSC_PDC_PTSR_RXTEN_SIZE 1
299	#define SSC_PDC_PTSR_RXTEN_OFFSET 0
300	#define SSC_PDC_PTSR_TXTEN_SIZE 1
301	#define SSC_PDC_PTSR_TXTEN_OFFSET 8
302
303	/* Bit manipulation macros */
304	#define SSC_BIT(name) \
305	(1 << SSC_##name##_OFFSET)
306	#define SSC_BF(name, value) \
307	(((value) & ((1 << SSC_##name##_SIZE) - 1)) \
308	<< SSC_##name##_OFFSET)
309	#define SSC_BFEXT(name, value) \
310	(((value) >> SSC_##name##_OFFSET) \
311	& ((1 << SSC_##name##_SIZE) - 1))
312	#define SSC_BFINS(name, value, old) \
313	(((old) & ~(((1 << SSC_##name##_SIZE) - 1) \
314	<< SSC_##name##_OFFSET)) \| SSC_BF(name, value))
315
316	/* Register access macros */
317	#define ssc_readl(base, reg) __raw_readl(base + SSC_##reg)
318	#define ssc_writel(base, reg, value) __raw_writel((value), base + SSC_##reg)
319
320	#endif /* __INCLUDE_ATMEL_SSC_H */