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1a59d1b8 | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
ed69bdd8 LP |
2 | /* |
3 | * CCI cache coherent interconnect support | |
4 | * | |
5 | * Copyright (C) 2013 ARM Ltd. | |
ed69bdd8 LP |
6 | */ |
7 | ||
8 | #ifndef __LINUX_ARM_CCI_H | |
9 | #define __LINUX_ARM_CCI_H | |
10 | ||
11 | #include <linux/errno.h> | |
12 | #include <linux/types.h> | |
13 | ||
772742a6 SP |
14 | #include <asm/arm-cci.h> |
15 | ||
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16 | struct device_node; |
17 | ||
18 | #ifdef CONFIG_ARM_CCI | |
19 | extern bool cci_probed(void); | |
ee8e5d5f SP |
20 | #else |
21 | static inline bool cci_probed(void) { return false; } | |
22 | #endif | |
23 | ||
24 | #ifdef CONFIG_ARM_CCI400_PORT_CTRL | |
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25 | extern int cci_ace_get_port(struct device_node *dn); |
26 | extern int cci_disable_port_by_cpu(u64 mpidr); | |
27 | extern int __cci_control_port_by_device(struct device_node *dn, bool enable); | |
28 | extern int __cci_control_port_by_index(u32 port, bool enable); | |
29 | #else | |
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30 | static inline int cci_ace_get_port(struct device_node *dn) |
31 | { | |
32 | return -ENODEV; | |
33 | } | |
34 | static inline int cci_disable_port_by_cpu(u64 mpidr) { return -ENODEV; } | |
35 | static inline int __cci_control_port_by_device(struct device_node *dn, | |
36 | bool enable) | |
37 | { | |
38 | return -ENODEV; | |
39 | } | |
40 | static inline int __cci_control_port_by_index(u32 port, bool enable) | |
41 | { | |
42 | return -ENODEV; | |
43 | } | |
44 | #endif | |
ee8e5d5f | 45 | |
db967cf8 AB |
46 | void cci_enable_port_for_self(void); |
47 | ||
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48 | #define cci_disable_port_by_device(dev) \ |
49 | __cci_control_port_by_device(dev, false) | |
50 | #define cci_enable_port_by_device(dev) \ | |
51 | __cci_control_port_by_device(dev, true) | |
52 | #define cci_disable_port_by_index(dev) \ | |
53 | __cci_control_port_by_index(dev, false) | |
54 | #define cci_enable_port_by_index(dev) \ | |
55 | __cci_control_port_by_index(dev, true) | |
56 | ||
57 | #endif |