[linux-2.6-block.git] / include / linux / aer.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (C) 2006 Intel Corp.
 *     Tom Long Nguyen (tom.l.nguyen@intel.com)
 *     Zhang Yanmin (yanmin.zhang@intel.com)
 */

#ifndef _AER_H_
#define _AER_H_

#include <linux/errno.h>
#include <linux/types.h>

#define AER_NONFATAL			0
#define AER_FATAL			1
#define AER_CORRECTABLE			2
#define DPC_FATAL			3

struct pci_dev;

struct pcie_tlp_log {
	u32 dw[4];
};

struct aer_capability_regs {
	u32 header;
	u32 uncor_status;
	u32 uncor_mask;
	u32 uncor_severity;
	u32 cor_status;
	u32 cor_mask;
	u32 cap_control;
	struct pcie_tlp_log header_log;
	u32 root_command;
	u32 root_status;
	u16 cor_err_source;
	u16 uncor_err_source;
};

int pcie_read_tlp_log(struct pci_dev *dev, int where, struct pcie_tlp_log *log);

#if defined(CONFIG_PCIEAER)
int pci_aer_clear_nonfatal_status(struct pci_dev *dev);
int pcie_aer_is_native(struct pci_dev *dev);
#else
static inline int pci_aer_clear_nonfatal_status(struct pci_dev *dev)
{
	return -EINVAL;
}
static inline int pcie_aer_is_native(struct pci_dev *dev) { return 0; }
#endif

void pci_print_aer(struct pci_dev *dev, int aer_severity,
		    struct aer_capability_regs *aer);
int cper_severity_to_aer(int cper_severity);
void aer_recover_queue(int domain, unsigned int bus, unsigned int devfn,
		       int severity, struct aer_capability_regs *aer_regs);
#endif //_AER_H_
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
6c2b374d ZY	2	/*
	3	* Copyright (C) 2006 Intel Corp.
	4	* Tom Long Nguyen (tom.l.nguyen@intel.com)
	5	* Zhang Yanmin (yanmin.zhang@intel.com)
	6	*/
	7
	8	#ifndef _AER_H_
	9	#define _AER_H_
	10
c89e5b80	11	#include <linux/errno.h>
efd01a72 TR	12	#include <linux/types.h>
efd01a72 TR	13
9e50a912 BD	14	#define AER_NONFATAL 0
	15	#define AER_FATAL 1
	16	#define AER_CORRECTABLE 2
b09803b5	17	#define DPC_FATAL 3
9e50a912	18
5ccb8225 MQ	19	struct pci_dev;
5ccb8225 MQ	20
0a5a46a6 IJ	21	struct pcie_tlp_log {
0a5a46a6 IJ	22	u32 dw[4];
c413d768 HY	23	};
	24
	25	struct aer_capability_regs {
	26	u32 header;
	27	u32 uncor_status;
	28	u32 uncor_mask;
	29	u32 uncor_severity;
	30	u32 cor_status;
	31	u32 cor_mask;
	32	u32 cap_control;
0a5a46a6	33	struct pcie_tlp_log header_log;
c413d768 HY	34	u32 root_command;
	35	u32 root_status;
	36	u16 cor_err_source;
	37	u16 uncor_err_source;
	38	};
	39
0a5a46a6 IJ	40	int pcie_read_tlp_log(struct pci_dev dev, int where, struct pcie_tlp_log log);
0a5a46a6 IJ	41
6c2b374d	42	#if defined(CONFIG_PCIEAER)
894020fd	43	int pci_aer_clear_nonfatal_status(struct pci_dev *dev);
49f77672	44	int pcie_aer_is_native(struct pci_dev *dev);
6c2b374d	45	#else
894020fd	46	static inline int pci_aer_clear_nonfatal_status(struct pci_dev *dev)
b07461a8 TI	47	{
	48	return -EINVAL;
	49	}
49f77672	50	static inline int pcie_aer_is_native(struct pci_dev *dev) { return 0; }
6c2b374d ZY	51	#endif
6c2b374d ZY	52
6777877e	53	void pci_print_aer(struct pci_dev *dev, int aer_severity,
fde41b9f BD	54	struct aer_capability_regs *aer);
	55	int cper_severity_to_aer(int cper_severity);
	56	void aer_recover_queue(int domain, unsigned int bus, unsigned int devfn,
96291d56	57	int severity, struct aer_capability_regs *aer_regs);
6c2b374d ZY	58	#endif //_AER_H_
6c2b374d ZY	59