[linux-2.6-block.git] / include / kvm / vgic / vgic.h

/*
 * Copyright (C) 2015, 2016 ARM Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
#ifndef __ASM_ARM_KVM_VGIC_VGIC_H
#define __ASM_ARM_KVM_VGIC_VGIC_H

#include <linux/kernel.h>
#include <linux/kvm.h>
#include <linux/irqreturn.h>
#include <linux/spinlock.h>
#include <linux/types.h>
#include <kvm/iodev.h>

#define VGIC_V3_MAX_CPUS	255
#define VGIC_V2_MAX_CPUS	8
#define VGIC_NR_IRQS_LEGACY     256
#define VGIC_NR_SGIS		16
#define VGIC_NR_PPIS		16
#define VGIC_NR_PRIVATE_IRQS	(VGIC_NR_SGIS + VGIC_NR_PPIS)
#define VGIC_MAX_PRIVATE	(VGIC_NR_PRIVATE_IRQS - 1)
#define VGIC_MAX_SPI		1019
#define VGIC_MAX_RESERVED	1023
#define VGIC_MIN_LPI		8192

enum vgic_type {
	VGIC_V2,		/* Good ol' GICv2 */
	VGIC_V3,		/* New fancy GICv3 */
};

/* same for all guests, as depending only on the _host's_ GIC model */
struct vgic_global {
	/* type of the host GIC */
	enum vgic_type		type;

	/* Physical address of vgic virtual cpu interface */
	phys_addr_t		vcpu_base;

	/* virtual control interface mapping */
	void __iomem		*vctrl_base;

	/* Number of implemented list registers */
	int			nr_lr;

	/* Maintenance IRQ number */
	unsigned int		maint_irq;

	/* maximum number of VCPUs allowed (GICv2 limits us to 8) */
	int			max_gic_vcpus;

	/* Only needed for the legacy KVM_CREATE_IRQCHIP */
	bool			can_emulate_gicv2;
};

extern struct vgic_global kvm_vgic_global_state;

#define VGIC_V2_MAX_LRS		(1 << 6)
#define VGIC_V3_MAX_LRS		16
#define VGIC_V3_LR_INDEX(lr)	(VGIC_V3_MAX_LRS - 1 - lr)

enum vgic_irq_config {
	VGIC_CONFIG_EDGE = 0,
	VGIC_CONFIG_LEVEL
};

struct vgic_irq {
	spinlock_t irq_lock;		/* Protects the content of the struct */
	struct list_head ap_list;

	struct kvm_vcpu *vcpu;		/* SGIs and PPIs: The VCPU
					 * SPIs and LPIs: The VCPU whose ap_list
					 * this is queued on.
					 */

	struct kvm_vcpu *target_vcpu;	/* The VCPU that this interrupt should
					 * be sent to, as a result of the
					 * targets reg (v2) or the
					 * affinity reg (v3).
					 */

	u32 intid;			/* Guest visible INTID */
	bool pending;
	bool line_level;		/* Level only */
	bool soft_pending;		/* Level only */
	bool active;			/* not used for LPIs */
	bool enabled;
	bool hw;			/* Tied to HW IRQ */
	u32 hwintid;			/* HW INTID number */
	union {
		u8 targets;			/* GICv2 target VCPUs mask */
		u32 mpidr;			/* GICv3 target VCPU */
	};
	u8 source;			/* GICv2 SGIs only */
	u8 priority;
	enum vgic_irq_config config;	/* Level or edge */
};

struct vgic_register_region;

struct vgic_io_device {
	gpa_t base_addr;
	struct kvm_vcpu *redist_vcpu;
	const struct vgic_register_region *regions;
	int nr_regions;
	struct kvm_io_device dev;
};

struct vgic_dist {
	bool			in_kernel;
	bool			ready;
	bool			initialized;

	/* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
	u32			vgic_model;

	int			nr_spis;

	/* TODO: Consider moving to global state */
	/* Virtual control interface mapping */
	void __iomem		*vctrl_base;

	/* base addresses in guest physical address space: */
	gpa_t			vgic_dist_base;		/* distributor */
	union {
		/* either a GICv2 CPU interface */
		gpa_t			vgic_cpu_base;
		/* or a number of GICv3 redistributor regions */
		gpa_t			vgic_redist_base;
	};

	/* distributor enabled */
	bool			enabled;

	struct vgic_irq		*spis;

	struct vgic_io_device	dist_iodev;
	struct vgic_io_device	*redist_iodevs;
};

struct vgic_v2_cpu_if {
	u32		vgic_hcr;
	u32		vgic_vmcr;
	u32		vgic_misr;	/* Saved only */
	u64		vgic_eisr;	/* Saved only */
	u64		vgic_elrsr;	/* Saved only */
	u32		vgic_apr;
	u32		vgic_lr[VGIC_V2_MAX_LRS];
};

struct vgic_v3_cpu_if {
#ifdef CONFIG_KVM_ARM_VGIC_V3
	u32		vgic_hcr;
	u32		vgic_vmcr;
	u32		vgic_sre;	/* Restored only, change ignored */
	u32		vgic_misr;	/* Saved only */
	u32		vgic_eisr;	/* Saved only */
	u32		vgic_elrsr;	/* Saved only */
	u32		vgic_ap0r[4];
	u32		vgic_ap1r[4];
	u64		vgic_lr[VGIC_V3_MAX_LRS];
#endif
};

struct vgic_cpu {
	/* CPU vif control registers for world switch */
	union {
		struct vgic_v2_cpu_if	vgic_v2;
		struct vgic_v3_cpu_if	vgic_v3;
	};

	unsigned int used_lrs;
	struct vgic_irq private_irqs[VGIC_NR_PRIVATE_IRQS];

	spinlock_t ap_list_lock;	/* Protects the ap_list */

	/*
	 * List of IRQs that this VCPU should consider because they are either
	 * Active or Pending (hence the name; AP list), or because they recently
	 * were one of the two and need to be migrated off this list to another
	 * VCPU.
	 */
	struct list_head ap_list_head;

	u64 live_lrs;
};

int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write);
void kvm_vgic_early_init(struct kvm *kvm);
int kvm_vgic_create(struct kvm *kvm, u32 type);
void kvm_vgic_destroy(struct kvm *kvm);
void kvm_vgic_vcpu_early_init(struct kvm_vcpu *vcpu);
void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
int kvm_vgic_map_resources(struct kvm *kvm);
int kvm_vgic_hyp_init(void);

int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid,
			bool level);

int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);

#define irqchip_in_kernel(k)	(!!((k)->arch.vgic.in_kernel))
#define vgic_initialized(k)	((k)->arch.vgic.initialized)
#define vgic_ready(k)		((k)->arch.vgic.ready)
#define vgic_valid_spi(k, i)	(((i) >= VGIC_NR_PRIVATE_IRQS) && \
			((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS))

bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu *vcpu);
void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);

#ifdef CONFIG_KVM_ARM_VGIC_V3
void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg);
#else
static inline void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg)
{
}
#endif

/**
 * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW
 *
 * The host's GIC naturally limits the maximum amount of VCPUs a guest
 * can use.
 */
static inline int kvm_vgic_get_max_vcpus(void)
{
	return kvm_vgic_global_state.max_gic_vcpus;
}

#endif /* __ASM_ARM_KVM_VGIC_VGIC_H */
Commit	Line	Data
b18b5778 CD	1	/*
	2	* Copyright (C) 2015, 2016 ARM Ltd.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*
	13	* You should have received a copy of the GNU General Public License
	14	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	15	*/
	16	#ifndef __ASM_ARM_KVM_VGIC_VGIC_H
	17	#define __ASM_ARM_KVM_VGIC_VGIC_H
	18
	19	#include <linux/kernel.h>
	20	#include <linux/kvm.h>
	21	#include <linux/irqreturn.h>
	22	#include <linux/spinlock.h>
	23	#include <linux/types.h>
	24	#include <kvm/iodev.h>
	25
	26	#define VGIC_V3_MAX_CPUS 255
	27	#define VGIC_V2_MAX_CPUS 8
	28	#define VGIC_NR_IRQS_LEGACY 256
	29	#define VGIC_NR_SGIS 16
	30	#define VGIC_NR_PPIS 16
	31	#define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS)
	32	#define VGIC_MAX_PRIVATE (VGIC_NR_PRIVATE_IRQS - 1)
	33	#define VGIC_MAX_SPI 1019
	34	#define VGIC_MAX_RESERVED 1023
	35	#define VGIC_MIN_LPI 8192
	36
	37	enum vgic_type {
	38	VGIC_V2, /* Good ol' GICv2 */
	39	VGIC_V3, /* New fancy GICv3 */
	40	};
	41
	42	/* same for all guests, as depending only on the _host's_ GIC model */
	43	struct vgic_global {
	44	/* type of the host GIC */
	45	enum vgic_type type;
	46
	47	/* Physical address of vgic virtual cpu interface */
	48	phys_addr_t vcpu_base;
	49
	50	/* virtual control interface mapping */
	51	void __iomem *vctrl_base;
	52
	53	/* Number of implemented list registers */
	54	int nr_lr;
	55
	56	/* Maintenance IRQ number */
	57	unsigned int maint_irq;
	58
	59	/* maximum number of VCPUs allowed (GICv2 limits us to 8) */
	60	int max_gic_vcpus;
	61
	62	/* Only needed for the legacy KVM_CREATE_IRQCHIP */
	63	bool can_emulate_gicv2;
	64	};
65
66	extern struct vgic_global kvm_vgic_global_state;
67
68	#define VGIC_V2_MAX_LRS (1 << 6)
69	#define VGIC_V3_MAX_LRS 16
70	#define VGIC_V3_LR_INDEX(lr) (VGIC_V3_MAX_LRS - 1 - lr)
71
72	enum vgic_irq_config {
73	VGIC_CONFIG_EDGE = 0,
74	VGIC_CONFIG_LEVEL
75	};
76
77	struct vgic_irq {
78	spinlock_t irq_lock; /* Protects the content of the struct */
79	struct list_head ap_list;
80
81	struct kvm_vcpu vcpu; / SGIs and PPIs: The VCPU
82	* SPIs and LPIs: The VCPU whose ap_list
83	* this is queued on.
84	*/
85
86	struct kvm_vcpu target_vcpu; / The VCPU that this interrupt should
87	* be sent to, as a result of the
88	* targets reg (v2) or the
89	* affinity reg (v3).
90	*/
91
92	u32 intid; /* Guest visible INTID */
93	bool pending;
94	bool line_level; /* Level only */
95	bool soft_pending; /* Level only */
96	bool active; /* not used for LPIs */
97	bool enabled;
98	bool hw; /* Tied to HW IRQ */
99	u32 hwintid; /* HW INTID number */
100	union {
101	u8 targets; /* GICv2 target VCPUs mask */
102	u32 mpidr; /* GICv3 target VCPU */
103	};
104	u8 source; /* GICv2 SGIs only */
105	u8 priority;
106	enum vgic_irq_config config; /* Level or edge */
107	};
108
4493b1c4 MZ	109	struct vgic_register_region;
	110
	111	struct vgic_io_device {
	112	gpa_t base_addr;
	113	struct kvm_vcpu *redist_vcpu;
	114	const struct vgic_register_region *regions;
	115	int nr_regions;
	116	struct kvm_io_device dev;
	117	};
	118
b18b5778 CD	119	struct vgic_dist {
	120	bool in_kernel;
	121	bool ready;
ad275b8b	122	bool initialized;
b18b5778 CD	123
	124	/* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
	125	u32 vgic_model;
	126
	127	int nr_spis;
	128
	129	/* TODO: Consider moving to global state */
	130	/* Virtual control interface mapping */
	131	void __iomem *vctrl_base;
	132
	133	/* base addresses in guest physical address space: */
	134	gpa_t vgic_dist_base; /* distributor */
	135	union {
	136	/* either a GICv2 CPU interface */
	137	gpa_t vgic_cpu_base;
	138	/* or a number of GICv3 redistributor regions */
	139	gpa_t vgic_redist_base;
	140	};
	141
	142	/* distributor enabled */
	143	bool enabled;
	144
	145	struct vgic_irq *spis;
4493b1c4 MZ	146
	147	struct vgic_io_device dist_iodev;
	148	struct vgic_io_device *redist_iodevs;
b18b5778 CD	149	};
	150
	151	struct vgic_v2_cpu_if {
	152	u32 vgic_hcr;
	153	u32 vgic_vmcr;
	154	u32 vgic_misr; /* Saved only */
	155	u64 vgic_eisr; /* Saved only */
	156	u64 vgic_elrsr; /* Saved only */
	157	u32 vgic_apr;
	158	u32 vgic_lr[VGIC_V2_MAX_LRS];
	159	};
	160
	161	struct vgic_v3_cpu_if {
	162	#ifdef CONFIG_KVM_ARM_VGIC_V3
	163	u32 vgic_hcr;
	164	u32 vgic_vmcr;
	165	u32 vgic_sre; /* Restored only, change ignored */
	166	u32 vgic_misr; /* Saved only */
	167	u32 vgic_eisr; /* Saved only */
	168	u32 vgic_elrsr; /* Saved only */
	169	u32 vgic_ap0r[4];
	170	u32 vgic_ap1r[4];
	171	u64 vgic_lr[VGIC_V3_MAX_LRS];
	172	#endif
	173	};
	174
	175	struct vgic_cpu {
	176	/* CPU vif control registers for world switch */
	177	union {
	178	struct vgic_v2_cpu_if vgic_v2;
	179	struct vgic_v3_cpu_if vgic_v3;
	180	};
	181
	182	unsigned int used_lrs;
	183	struct vgic_irq private_irqs[VGIC_NR_PRIVATE_IRQS];
	184
	185	spinlock_t ap_list_lock; /* Protects the ap_list */
	186
	187	/*
	188	* List of IRQs that this VCPU should consider because they are either
	189	* Active or Pending (hence the name; AP list), or because they recently
	190	* were one of the two and need to be migrated off this list to another
	191	* VCPU.
	192	*/
	193	struct list_head ap_list_head;
	194
	195	u64 live_lrs;
	196	};
	197
e2c1f9ab	198	int kvm_vgic_addr(struct kvm kvm, unsigned long type, u64 addr, bool write);
ad275b8b	199	void kvm_vgic_early_init(struct kvm *kvm);
5e6431da	200	int kvm_vgic_create(struct kvm *kvm, u32 type);
ad275b8b EA	201	void kvm_vgic_destroy(struct kvm *kvm);
	202	void kvm_vgic_vcpu_early_init(struct kvm_vcpu *vcpu);
	203	void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
b0442ee2	204	int kvm_vgic_map_resources(struct kvm *kvm);
90977732	205	int kvm_vgic_hyp_init(void);
e2c1f9ab	206
81eeb95d CD	207	int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid,
	208	bool level);
	209
90eee56c EA	210	int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
90eee56c EA	211
b18b5778	212	#define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel))
ad275b8b	213	#define vgic_initialized(k) ((k)->arch.vgic.initialized)
b18b5778 CD	214	#define vgic_ready(k) ((k)->arch.vgic.ready)
	215	#define vgic_valid_spi(k, i) (((i) >= VGIC_NR_PRIVATE_IRQS) && \
	216	((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS))
	217
0919e84c MZ	218	bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu *vcpu);
	219	void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
	220	void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
	221
621ecd8d AP	222	#ifdef CONFIG_KVM_ARM_VGIC_V3
	223	void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg);
	224	#else
	225	static inline void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg)
	226	{
	227	}
	228	#endif
	229
b18b5778 CD	230	/**
	231	* kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW
	232	*
	233	* The host's GIC naturally limits the maximum amount of VCPUs a guest
	234	* can use.
	235	*/
	236	static inline int kvm_vgic_get_max_vcpus(void)
	237	{
	238	return kvm_vgic_global_state.max_gic_vcpus;
	239	}
	240
	241	#endif /* __ASM_ARM_KVM_VGIC_VGIC_H */