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1a89dd91 MZ |
1 | /* |
2 | * Copyright (C) 2012 ARM Ltd. | |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
17 | */ | |
18 | ||
19 | #ifndef __ASM_ARM_KVM_VGIC_H | |
20 | #define __ASM_ARM_KVM_VGIC_H | |
21 | ||
b47ef92a MZ |
22 | #include <linux/kernel.h> |
23 | #include <linux/kvm.h> | |
b47ef92a MZ |
24 | #include <linux/irqreturn.h> |
25 | #include <linux/spinlock.h> | |
26 | #include <linux/types.h> | |
1a89dd91 | 27 | |
9b2d2e0d | 28 | #define VGIC_NR_IRQS 256 |
b47ef92a MZ |
29 | #define VGIC_NR_SGIS 16 |
30 | #define VGIC_NR_PPIS 16 | |
31 | #define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS) | |
32 | #define VGIC_NR_SHARED_IRQS (VGIC_NR_IRQS - VGIC_NR_PRIVATE_IRQS) | |
33 | #define VGIC_MAX_CPUS KVM_MAX_VCPUS | |
8f186d52 MZ |
34 | |
35 | #define VGIC_V2_MAX_LRS (1 << 6) | |
b2fb1c0d | 36 | #define VGIC_V3_MAX_LRS 16 |
b47ef92a MZ |
37 | |
38 | /* Sanity checks... */ | |
39 | #if (VGIC_MAX_CPUS > 8) | |
40 | #error Invalid number of CPU interfaces | |
41 | #endif | |
42 | ||
43 | #if (VGIC_NR_IRQS & 31) | |
44 | #error "VGIC_NR_IRQS must be a multiple of 32" | |
45 | #endif | |
46 | ||
47 | #if (VGIC_NR_IRQS > 1024) | |
48 | #error "VGIC_NR_IRQS must be <= 1024" | |
49 | #endif | |
50 | ||
51 | /* | |
52 | * The GIC distributor registers describing interrupts have two parts: | |
53 | * - 32 per-CPU interrupts (SGI + PPI) | |
54 | * - a bunch of shared interrupts (SPI) | |
55 | */ | |
56 | struct vgic_bitmap { | |
57 | union { | |
58 | u32 reg[VGIC_NR_PRIVATE_IRQS / 32]; | |
59 | DECLARE_BITMAP(reg_ul, VGIC_NR_PRIVATE_IRQS); | |
60 | } percpu[VGIC_MAX_CPUS]; | |
61 | union { | |
62 | u32 reg[VGIC_NR_SHARED_IRQS / 32]; | |
63 | DECLARE_BITMAP(reg_ul, VGIC_NR_SHARED_IRQS); | |
64 | } shared; | |
65 | }; | |
66 | ||
67 | struct vgic_bytemap { | |
68 | u32 percpu[VGIC_MAX_CPUS][VGIC_NR_PRIVATE_IRQS / 4]; | |
69 | u32 shared[VGIC_NR_SHARED_IRQS / 4]; | |
70 | }; | |
71 | ||
8d5c6b06 MZ |
72 | struct kvm_vcpu; |
73 | ||
1a9b1305 MZ |
74 | enum vgic_type { |
75 | VGIC_V2, /* Good ol' GICv2 */ | |
b2fb1c0d | 76 | VGIC_V3, /* New fancy GICv3 */ |
1a9b1305 MZ |
77 | }; |
78 | ||
8d5c6b06 MZ |
79 | #define LR_STATE_PENDING (1 << 0) |
80 | #define LR_STATE_ACTIVE (1 << 1) | |
81 | #define LR_STATE_MASK (3 << 0) | |
82 | #define LR_EOI_INT (1 << 2) | |
83 | ||
84 | struct vgic_lr { | |
85 | u16 irq; | |
86 | u8 source; | |
87 | u8 state; | |
88 | }; | |
89 | ||
beee38b9 MZ |
90 | struct vgic_vmcr { |
91 | u32 ctlr; | |
92 | u32 abpr; | |
93 | u32 bpr; | |
94 | u32 pmr; | |
95 | }; | |
96 | ||
8d5c6b06 MZ |
97 | struct vgic_ops { |
98 | struct vgic_lr (*get_lr)(const struct kvm_vcpu *, int); | |
99 | void (*set_lr)(struct kvm_vcpu *, int, struct vgic_lr); | |
69bb2c9f MZ |
100 | void (*sync_lr_elrsr)(struct kvm_vcpu *, int, struct vgic_lr); |
101 | u64 (*get_elrsr)(const struct kvm_vcpu *vcpu); | |
8d6a0313 | 102 | u64 (*get_eisr)(const struct kvm_vcpu *vcpu); |
495dd859 | 103 | u32 (*get_interrupt_status)(const struct kvm_vcpu *vcpu); |
909d9b50 MZ |
104 | void (*enable_underflow)(struct kvm_vcpu *vcpu); |
105 | void (*disable_underflow)(struct kvm_vcpu *vcpu); | |
beee38b9 MZ |
106 | void (*get_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); |
107 | void (*set_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); | |
da8dafd1 | 108 | void (*enable)(struct kvm_vcpu *vcpu); |
8d5c6b06 MZ |
109 | }; |
110 | ||
ca85f623 | 111 | struct vgic_params { |
1a9b1305 MZ |
112 | /* vgic type */ |
113 | enum vgic_type type; | |
ca85f623 MZ |
114 | /* Physical address of vgic virtual cpu interface */ |
115 | phys_addr_t vcpu_base; | |
116 | /* Number of list registers */ | |
117 | u32 nr_lr; | |
118 | /* Interrupt number */ | |
119 | unsigned int maint_irq; | |
120 | /* Virtual control interface base address */ | |
121 | void __iomem *vctrl_base; | |
122 | }; | |
123 | ||
1a89dd91 | 124 | struct vgic_dist { |
b47ef92a MZ |
125 | #ifdef CONFIG_KVM_ARM_VGIC |
126 | spinlock_t lock; | |
f982cf4e | 127 | bool in_kernel; |
01ac5e34 | 128 | bool ready; |
b47ef92a MZ |
129 | |
130 | /* Virtual control interface mapping */ | |
131 | void __iomem *vctrl_base; | |
132 | ||
330690cd CD |
133 | /* Distributor and vcpu interface mapping in the guest */ |
134 | phys_addr_t vgic_dist_base; | |
135 | phys_addr_t vgic_cpu_base; | |
b47ef92a MZ |
136 | |
137 | /* Distributor enabled */ | |
138 | u32 enabled; | |
139 | ||
140 | /* Interrupt enabled (one bit per IRQ) */ | |
141 | struct vgic_bitmap irq_enabled; | |
142 | ||
faa1b46c CD |
143 | /* Level-triggered interrupt external input is asserted */ |
144 | struct vgic_bitmap irq_level; | |
145 | ||
146 | /* | |
147 | * Interrupt state is pending on the distributor | |
148 | */ | |
227844f5 | 149 | struct vgic_bitmap irq_pending; |
b47ef92a | 150 | |
faa1b46c CD |
151 | /* |
152 | * Tracks writes to GICD_ISPENDRn and GICD_ICPENDRn for level-triggered | |
153 | * interrupts. Essentially holds the state of the flip-flop in | |
154 | * Figure 4-10 on page 4-101 in ARM IHI 0048B.b. | |
155 | * Once set, it is only cleared for level-triggered interrupts on | |
156 | * guest ACKs (when we queue it) or writes to GICD_ICPENDRn. | |
157 | */ | |
158 | struct vgic_bitmap irq_soft_pend; | |
159 | ||
dbf20f9d CD |
160 | /* Level-triggered interrupt queued on VCPU interface */ |
161 | struct vgic_bitmap irq_queued; | |
b47ef92a MZ |
162 | |
163 | /* Interrupt priority. Not used yet. */ | |
164 | struct vgic_bytemap irq_priority; | |
165 | ||
166 | /* Level/edge triggered */ | |
167 | struct vgic_bitmap irq_cfg; | |
168 | ||
169 | /* Source CPU per SGI and target CPU */ | |
170 | u8 irq_sgi_sources[VGIC_MAX_CPUS][VGIC_NR_SGIS]; | |
171 | ||
172 | /* Target CPU for each IRQ */ | |
173 | u8 irq_spi_cpu[VGIC_NR_SHARED_IRQS]; | |
174 | struct vgic_bitmap irq_spi_target[VGIC_MAX_CPUS]; | |
175 | ||
176 | /* Bitmap indicating which CPU has something pending */ | |
177 | unsigned long irq_pending_on_cpu; | |
178 | #endif | |
1a89dd91 MZ |
179 | }; |
180 | ||
eede821d MZ |
181 | struct vgic_v2_cpu_if { |
182 | u32 vgic_hcr; | |
183 | u32 vgic_vmcr; | |
184 | u32 vgic_misr; /* Saved only */ | |
185 | u32 vgic_eisr[2]; /* Saved only */ | |
186 | u32 vgic_elrsr[2]; /* Saved only */ | |
187 | u32 vgic_apr; | |
8f186d52 | 188 | u32 vgic_lr[VGIC_V2_MAX_LRS]; |
eede821d MZ |
189 | }; |
190 | ||
b2fb1c0d MZ |
191 | struct vgic_v3_cpu_if { |
192 | #ifdef CONFIG_ARM_GIC_V3 | |
193 | u32 vgic_hcr; | |
194 | u32 vgic_vmcr; | |
195 | u32 vgic_misr; /* Saved only */ | |
196 | u32 vgic_eisr; /* Saved only */ | |
197 | u32 vgic_elrsr; /* Saved only */ | |
198 | u32 vgic_ap0r[4]; | |
199 | u32 vgic_ap1r[4]; | |
200 | u64 vgic_lr[VGIC_V3_MAX_LRS]; | |
201 | #endif | |
202 | }; | |
203 | ||
1a89dd91 | 204 | struct vgic_cpu { |
9d949dce MZ |
205 | #ifdef CONFIG_KVM_ARM_VGIC |
206 | /* per IRQ to LR mapping */ | |
207 | u8 vgic_irq_lr_map[VGIC_NR_IRQS]; | |
208 | ||
209 | /* Pending interrupts on this VCPU */ | |
210 | DECLARE_BITMAP( pending_percpu, VGIC_NR_PRIVATE_IRQS); | |
211 | DECLARE_BITMAP( pending_shared, VGIC_NR_SHARED_IRQS); | |
212 | ||
213 | /* Bitmap of used/free list registers */ | |
8f186d52 | 214 | DECLARE_BITMAP( lr_used, VGIC_V2_MAX_LRS); |
9d949dce MZ |
215 | |
216 | /* Number of list registers on this CPU */ | |
217 | int nr_lr; | |
218 | ||
219 | /* CPU vif control registers for world switch */ | |
eede821d MZ |
220 | union { |
221 | struct vgic_v2_cpu_if vgic_v2; | |
b2fb1c0d | 222 | struct vgic_v3_cpu_if vgic_v3; |
eede821d | 223 | }; |
9d949dce | 224 | #endif |
1a89dd91 MZ |
225 | }; |
226 | ||
9d949dce MZ |
227 | #define LR_EMPTY 0xff |
228 | ||
495dd859 MZ |
229 | #define INT_STATUS_EOI (1 << 0) |
230 | #define INT_STATUS_UNDERFLOW (1 << 1) | |
231 | ||
1a89dd91 MZ |
232 | struct kvm; |
233 | struct kvm_vcpu; | |
234 | struct kvm_run; | |
235 | struct kvm_exit_mmio; | |
236 | ||
237 | #ifdef CONFIG_KVM_ARM_VGIC | |
ce01e4e8 | 238 | int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write); |
01ac5e34 MZ |
239 | int kvm_vgic_hyp_init(void); |
240 | int kvm_vgic_init(struct kvm *kvm); | |
241 | int kvm_vgic_create(struct kvm *kvm); | |
242 | int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu); | |
9d949dce MZ |
243 | void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu); |
244 | void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu); | |
5863c2ce MZ |
245 | int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num, |
246 | bool level); | |
9d949dce | 247 | int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu); |
1a89dd91 MZ |
248 | bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run, |
249 | struct kvm_exit_mmio *mmio); | |
250 | ||
f982cf4e | 251 | #define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel)) |
01ac5e34 | 252 | #define vgic_initialized(k) ((k)->arch.vgic.ready) |
9d949dce | 253 | |
8f186d52 MZ |
254 | int vgic_v2_probe(struct device_node *vgic_node, |
255 | const struct vgic_ops **ops, | |
256 | const struct vgic_params **params); | |
b2fb1c0d MZ |
257 | #ifdef CONFIG_ARM_GIC_V3 |
258 | int vgic_v3_probe(struct device_node *vgic_node, | |
259 | const struct vgic_ops **ops, | |
260 | const struct vgic_params **params); | |
261 | #else | |
262 | static inline int vgic_v3_probe(struct device_node *vgic_node, | |
263 | const struct vgic_ops **ops, | |
264 | const struct vgic_params **params) | |
265 | { | |
266 | return -ENODEV; | |
267 | } | |
268 | #endif | |
8f186d52 | 269 | |
1a89dd91 MZ |
270 | #else |
271 | static inline int kvm_vgic_hyp_init(void) | |
272 | { | |
273 | return 0; | |
274 | } | |
275 | ||
330690cd CD |
276 | static inline int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr) |
277 | { | |
278 | return 0; | |
279 | } | |
280 | ||
6cbde825 MZ |
281 | static inline int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write) |
282 | { | |
283 | return -ENXIO; | |
284 | } | |
285 | ||
1a89dd91 MZ |
286 | static inline int kvm_vgic_init(struct kvm *kvm) |
287 | { | |
288 | return 0; | |
289 | } | |
290 | ||
291 | static inline int kvm_vgic_create(struct kvm *kvm) | |
292 | { | |
293 | return 0; | |
294 | } | |
295 | ||
296 | static inline int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu) | |
297 | { | |
298 | return 0; | |
299 | } | |
300 | ||
301 | static inline void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) {} | |
302 | static inline void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) {} | |
303 | ||
5863c2ce MZ |
304 | static inline int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, |
305 | unsigned int irq_num, bool level) | |
306 | { | |
307 | return 0; | |
308 | } | |
309 | ||
1a89dd91 MZ |
310 | static inline int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu) |
311 | { | |
312 | return 0; | |
313 | } | |
314 | ||
315 | static inline bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run, | |
316 | struct kvm_exit_mmio *mmio) | |
317 | { | |
318 | return false; | |
319 | } | |
320 | ||
321 | static inline int irqchip_in_kernel(struct kvm *kvm) | |
322 | { | |
323 | return 0; | |
324 | } | |
01ac5e34 MZ |
325 | |
326 | static inline bool vgic_initialized(struct kvm *kvm) | |
327 | { | |
328 | return true; | |
329 | } | |
1a89dd91 MZ |
330 | #endif |
331 | ||
332 | #endif |