[linux-block.git] / include / kvm / arm_vgic.h

/*
 * Copyright (C) 2012 ARM Ltd.
 * Author: Marc Zyngier <marc.zyngier@arm.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 */

#ifndef __ASM_ARM_KVM_VGIC_H
#define __ASM_ARM_KVM_VGIC_H

#include <linux/kernel.h>
#include <linux/kvm.h>
#include <linux/irqreturn.h>
#include <linux/spinlock.h>
#include <linux/types.h>

#define VGIC_NR_IRQS_LEGACY	256
#define VGIC_NR_SGIS		16
#define VGIC_NR_PPIS		16
#define VGIC_NR_PRIVATE_IRQS	(VGIC_NR_SGIS + VGIC_NR_PPIS)

#define VGIC_V2_MAX_LRS		(1 << 6)
#define VGIC_V3_MAX_LRS		16
#define VGIC_MAX_IRQS		1024

/* Sanity checks... */
#if (KVM_MAX_VCPUS > 8)
#error	Invalid number of CPU interfaces
#endif

#if (VGIC_NR_IRQS_LEGACY & 31)
#error "VGIC_NR_IRQS must be a multiple of 32"
#endif

#if (VGIC_NR_IRQS_LEGACY > VGIC_MAX_IRQS)
#error "VGIC_NR_IRQS must be <= 1024"
#endif

/*
 * The GIC distributor registers describing interrupts have two parts:
 * - 32 per-CPU interrupts (SGI + PPI)
 * - a bunch of shared interrupts (SPI)
 */
struct vgic_bitmap {
	/*
	 * - One UL per VCPU for private interrupts (assumes UL is at
	 *   least 32 bits)
	 * - As many UL as necessary for shared interrupts.
	 *
	 * The private interrupts are accessed via the "private"
	 * field, one UL per vcpu (the state for vcpu n is in
	 * private[n]). The shared interrupts are accessed via the
	 * "shared" pointer (IRQn state is at bit n-32 in the bitmap).
	 */
	unsigned long *private;
	unsigned long *shared;
};

struct vgic_bytemap {
	/*
	 * - 8 u32 per VCPU for private interrupts
	 * - As many u32 as necessary for shared interrupts.
	 *
	 * The private interrupts are accessed via the "private"
	 * field, (the state for vcpu n is in private[n*8] to
	 * private[n*8 + 7]). The shared interrupts are accessed via
	 * the "shared" pointer (IRQn state is at byte (n-32)%4 of the
	 * shared[(n-32)/4] word).
	 */
	u32 *private;
	u32 *shared;
};

struct kvm_vcpu;

enum vgic_type {
	VGIC_V2,		/* Good ol' GICv2 */
	VGIC_V3,		/* New fancy GICv3 */
};

#define LR_STATE_PENDING	(1 << 0)
#define LR_STATE_ACTIVE		(1 << 1)
#define LR_STATE_MASK		(3 << 0)
#define LR_EOI_INT		(1 << 2)

struct vgic_lr {
	u16	irq;
	u8	source;
	u8	state;
};

struct vgic_vmcr {
	u32	ctlr;
	u32	abpr;
	u32	bpr;
	u32	pmr;
};

struct vgic_ops {
	struct vgic_lr	(*get_lr)(const struct kvm_vcpu *, int);
	void	(*set_lr)(struct kvm_vcpu *, int, struct vgic_lr);
	void	(*sync_lr_elrsr)(struct kvm_vcpu *, int, struct vgic_lr);
	u64	(*get_elrsr)(const struct kvm_vcpu *vcpu);
	u64	(*get_eisr)(const struct kvm_vcpu *vcpu);
	u32	(*get_interrupt_status)(const struct kvm_vcpu *vcpu);
	void	(*enable_underflow)(struct kvm_vcpu *vcpu);
	void	(*disable_underflow)(struct kvm_vcpu *vcpu);
	void	(*get_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
	void	(*set_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
	void	(*enable)(struct kvm_vcpu *vcpu);
};

struct vgic_params {
	/* vgic type */
	enum vgic_type	type;
	/* Physical address of vgic virtual cpu interface */
	phys_addr_t	vcpu_base;
	/* Number of list registers */
	u32		nr_lr;
	/* Interrupt number */
	unsigned int	maint_irq;
	/* Virtual control interface base address */
	void __iomem	*vctrl_base;
};

struct vgic_dist {
#ifdef CONFIG_KVM_ARM_VGIC
	spinlock_t		lock;
	bool			in_kernel;
	bool			ready;

	/* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
	u32			vgic_model;

	int			nr_cpus;
	int			nr_irqs;

	/* Virtual control interface mapping */
	void __iomem		*vctrl_base;

	/* Distributor and vcpu interface mapping in the guest */
	phys_addr_t		vgic_dist_base;
	phys_addr_t		vgic_cpu_base;

	/* Distributor enabled */
	u32			enabled;

	/* Interrupt enabled (one bit per IRQ) */
	struct vgic_bitmap	irq_enabled;

	/* Level-triggered interrupt external input is asserted */
	struct vgic_bitmap	irq_level;

	/*
	 * Interrupt state is pending on the distributor
	 */
	struct vgic_bitmap	irq_pending;

	/*
	 * Tracks writes to GICD_ISPENDRn and GICD_ICPENDRn for level-triggered
	 * interrupts.  Essentially holds the state of the flip-flop in
	 * Figure 4-10 on page 4-101 in ARM IHI 0048B.b.
	 * Once set, it is only cleared for level-triggered interrupts on
	 * guest ACKs (when we queue it) or writes to GICD_ICPENDRn.
	 */
	struct vgic_bitmap	irq_soft_pend;

	/* Level-triggered interrupt queued on VCPU interface */
	struct vgic_bitmap	irq_queued;

	/* Interrupt priority. Not used yet. */
	struct vgic_bytemap	irq_priority;

	/* Level/edge triggered */
	struct vgic_bitmap	irq_cfg;

	/*
	 * Source CPU per SGI and target CPU:
	 *
	 * Each byte represent a SGI observable on a VCPU, each bit of
	 * this byte indicating if the corresponding VCPU has
	 * generated this interrupt. This is a GICv2 feature only.
	 *
	 * For VCPUn (n < 8), irq_sgi_sources[n*16] to [n*16 + 15] are
	 * the SGIs observable on VCPUn.
	 */
	u8			*irq_sgi_sources;

	/*
	 * Target CPU for each SPI:
	 *
	 * Array of available SPI, each byte indicating the target
	 * VCPU for SPI. IRQn (n >=32) is at irq_spi_cpu[n-32].
	 */
	u8			*irq_spi_cpu;

	/*
	 * Reverse lookup of irq_spi_cpu for faster compute pending:
	 *
	 * Array of bitmaps, one per VCPU, describing if IRQn is
	 * routed to a particular VCPU.
	 */
	struct vgic_bitmap	*irq_spi_target;

	/* Bitmap indicating which CPU has something pending */
	unsigned long		*irq_pending_on_cpu;
#endif
};

struct vgic_v2_cpu_if {
	u32		vgic_hcr;
	u32		vgic_vmcr;
	u32		vgic_misr;	/* Saved only */
	u64		vgic_eisr;	/* Saved only */
	u64		vgic_elrsr;	/* Saved only */
	u32		vgic_apr;
	u32		vgic_lr[VGIC_V2_MAX_LRS];
};

struct vgic_v3_cpu_if {
#ifdef CONFIG_ARM_GIC_V3
	u32		vgic_hcr;
	u32		vgic_vmcr;
	u32		vgic_misr;	/* Saved only */
	u32		vgic_eisr;	/* Saved only */
	u32		vgic_elrsr;	/* Saved only */
	u32		vgic_ap0r[4];
	u32		vgic_ap1r[4];
	u64		vgic_lr[VGIC_V3_MAX_LRS];
#endif
};

struct vgic_cpu {
#ifdef CONFIG_KVM_ARM_VGIC
	/* per IRQ to LR mapping */
	u8		*vgic_irq_lr_map;

	/* Pending interrupts on this VCPU */
	DECLARE_BITMAP(	pending_percpu, VGIC_NR_PRIVATE_IRQS);
	unsigned long	*pending_shared;

	/* Bitmap of used/free list registers */
	DECLARE_BITMAP(	lr_used, VGIC_V2_MAX_LRS);

	/* Number of list registers on this CPU */
	int		nr_lr;

	/* CPU vif control registers for world switch */
	union {
		struct vgic_v2_cpu_if	vgic_v2;
		struct vgic_v3_cpu_if	vgic_v3;
	};
#endif
};

#define LR_EMPTY	0xff

#define INT_STATUS_EOI		(1 << 0)
#define INT_STATUS_UNDERFLOW	(1 << 1)

struct kvm;
struct kvm_vcpu;
struct kvm_run;
struct kvm_exit_mmio;

#ifdef CONFIG_KVM_ARM_VGIC
int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write);
int kvm_vgic_hyp_init(void);
int kvm_vgic_map_resources(struct kvm *kvm);
int kvm_vgic_create(struct kvm *kvm, u32 type);
void kvm_vgic_destroy(struct kvm *kvm);
void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
			bool level);
int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
		      struct kvm_exit_mmio *mmio);

#define irqchip_in_kernel(k)	(!!((k)->arch.vgic.in_kernel))
#define vgic_initialized(k)	(!!((k)->arch.vgic.nr_cpus))
#define vgic_ready(k)		((k)->arch.vgic.ready)

int vgic_v2_probe(struct device_node *vgic_node,
		  const struct vgic_ops **ops,
		  const struct vgic_params **params);
#ifdef CONFIG_ARM_GIC_V3
int vgic_v3_probe(struct device_node *vgic_node,
		  const struct vgic_ops **ops,
		  const struct vgic_params **params);
#else
static inline int vgic_v3_probe(struct device_node *vgic_node,
				const struct vgic_ops **ops,
				const struct vgic_params **params)
{
	return -ENODEV;
}
#endif

#else
static inline int kvm_vgic_hyp_init(void)
{
	return 0;
}

static inline int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr)
{
	return 0;
}

static inline int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write)
{
	return -ENXIO;
}

static inline int kvm_vgic_map_resources(struct kvm *kvm)
{
	return 0;
}

static inline int kvm_vgic_create(struct kvm *kvm, u32 type)
{
	return 0;
}

static inline void kvm_vgic_destroy(struct kvm *kvm)
{
}

static inline void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu)
{
}

static inline int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu)
{
	return 0;
}

static inline void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) {}
static inline void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) {}

static inline int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid,
				      unsigned int irq_num, bool level)
{
	return 0;
}

static inline int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
{
	return 0;
}

static inline bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
				    struct kvm_exit_mmio *mmio)
{
	return false;
}

static inline int irqchip_in_kernel(struct kvm *kvm)
{
	return 0;
}

static inline bool vgic_initialized(struct kvm *kvm)
{
	return true;
}

static inline bool vgic_ready(struct kvm *kvm)
{
	return true;
}
#endif

#endif
Commit	Line	Data
1a89dd91 MZ	1	/*
	2	* Copyright (C) 2012 ARM Ltd.
	3	* Author: Marc Zyngier <marc.zyngier@arm.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	17	*/
	18
	19	#ifndef __ASM_ARM_KVM_VGIC_H
	20	#define __ASM_ARM_KVM_VGIC_H
	21
b47ef92a MZ	22	#include <linux/kernel.h>
b47ef92a MZ	23	#include <linux/kvm.h>
b47ef92a MZ	24	#include <linux/irqreturn.h>
	25	#include <linux/spinlock.h>
	26	#include <linux/types.h>
1a89dd91	27
5fb66da6	28	#define VGIC_NR_IRQS_LEGACY 256
b47ef92a MZ	29	#define VGIC_NR_SGIS 16
	30	#define VGIC_NR_PPIS 16
	31	#define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS)
8f186d52 MZ	32
8f186d52 MZ	33	#define VGIC_V2_MAX_LRS (1 << 6)
b2fb1c0d	34	#define VGIC_V3_MAX_LRS 16
c3c91836	35	#define VGIC_MAX_IRQS 1024
b47ef92a MZ	36
b47ef92a MZ	37	/* Sanity checks... */
fc675e35	38	#if (KVM_MAX_VCPUS > 8)
b47ef92a MZ	39	#error Invalid number of CPU interfaces
	40	#endif
	41
5fb66da6	42	#if (VGIC_NR_IRQS_LEGACY & 31)
b47ef92a MZ	43	#error "VGIC_NR_IRQS must be a multiple of 32"
	44	#endif
	45
5fb66da6	46	#if (VGIC_NR_IRQS_LEGACY > VGIC_MAX_IRQS)
b47ef92a MZ	47	#error "VGIC_NR_IRQS must be <= 1024"
	48	#endif
	49
	50	/*
	51	* The GIC distributor registers describing interrupts have two parts:
	52	* - 32 per-CPU interrupts (SGI + PPI)
	53	* - a bunch of shared interrupts (SPI)
	54	*/
	55	struct vgic_bitmap {
c1bfb577 MZ	56	/*
	57	* - One UL per VCPU for private interrupts (assumes UL is at
	58	* least 32 bits)
	59	* - As many UL as necessary for shared interrupts.
	60	*
	61	* The private interrupts are accessed via the "private"
	62	* field, one UL per vcpu (the state for vcpu n is in
	63	* private[n]). The shared interrupts are accessed via the
	64	* "shared" pointer (IRQn state is at bit n-32 in the bitmap).
	65	*/
	66	unsigned long *private;
	67	unsigned long *shared;
b47ef92a MZ	68	};
	69
	70	struct vgic_bytemap {
c1bfb577 MZ	71	/*
	72	* - 8 u32 per VCPU for private interrupts
	73	* - As many u32 as necessary for shared interrupts.
	74	*
	75	* The private interrupts are accessed via the "private"
	76	* field, (the state for vcpu n is in private[n*8] to
	77	* private[n*8 + 7]). The shared interrupts are accessed via
	78	* the "shared" pointer (IRQn state is at byte (n-32)%4 of the
	79	* shared[(n-32)/4] word).
	80	*/
	81	u32 *private;
	82	u32 *shared;
b47ef92a MZ	83	};
b47ef92a MZ	84
8d5c6b06 MZ	85	struct kvm_vcpu;
8d5c6b06 MZ	86
1a9b1305 MZ	87	enum vgic_type {
1a9b1305 MZ	88	VGIC_V2, /* Good ol' GICv2 */
b2fb1c0d	89	VGIC_V3, /* New fancy GICv3 */
1a9b1305 MZ	90	};
1a9b1305 MZ	91
8d5c6b06 MZ	92	#define LR_STATE_PENDING (1 << 0)
	93	#define LR_STATE_ACTIVE (1 << 1)
	94	#define LR_STATE_MASK (3 << 0)
	95	#define LR_EOI_INT (1 << 2)
	96
	97	struct vgic_lr {
	98	u16 irq;
	99	u8 source;
	100	u8 state;
	101	};
	102
beee38b9 MZ	103	struct vgic_vmcr {
	104	u32 ctlr;
	105	u32 abpr;
	106	u32 bpr;
	107	u32 pmr;
	108	};
	109
8d5c6b06 MZ	110	struct vgic_ops {
	111	struct vgic_lr (get_lr)(const struct kvm_vcpu , int);
	112	void (set_lr)(struct kvm_vcpu , int, struct vgic_lr);
69bb2c9f MZ	113	void (sync_lr_elrsr)(struct kvm_vcpu , int, struct vgic_lr);
69bb2c9f MZ	114	u64 (get_elrsr)(const struct kvm_vcpu vcpu);
8d6a0313	115	u64 (get_eisr)(const struct kvm_vcpu vcpu);
495dd859	116	u32 (get_interrupt_status)(const struct kvm_vcpu vcpu);
909d9b50 MZ	117	void (enable_underflow)(struct kvm_vcpu vcpu);
909d9b50 MZ	118	void (disable_underflow)(struct kvm_vcpu vcpu);
beee38b9 MZ	119	void (get_vmcr)(struct kvm_vcpu vcpu, struct vgic_vmcr *vmcr);
beee38b9 MZ	120	void (set_vmcr)(struct kvm_vcpu vcpu, struct vgic_vmcr *vmcr);
da8dafd1	121	void (enable)(struct kvm_vcpu vcpu);
8d5c6b06 MZ	122	};
8d5c6b06 MZ	123
ca85f623	124	struct vgic_params {
1a9b1305 MZ	125	/* vgic type */
1a9b1305 MZ	126	enum vgic_type type;
ca85f623 MZ	127	/* Physical address of vgic virtual cpu interface */
	128	phys_addr_t vcpu_base;
	129	/* Number of list registers */
	130	u32 nr_lr;
	131	/* Interrupt number */
	132	unsigned int maint_irq;
	133	/* Virtual control interface base address */
	134	void __iomem *vctrl_base;
	135	};
	136
1a89dd91	137	struct vgic_dist {
b47ef92a MZ	138	#ifdef CONFIG_KVM_ARM_VGIC
b47ef92a MZ	139	spinlock_t lock;
f982cf4e	140	bool in_kernel;
01ac5e34	141	bool ready;
b47ef92a	142
59892136 AP	143	/* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
	144	u32 vgic_model;
	145
c1bfb577 MZ	146	int nr_cpus;
	147	int nr_irqs;
	148
b47ef92a MZ	149	/* Virtual control interface mapping */
	150	void __iomem *vctrl_base;
	151
330690cd CD	152	/* Distributor and vcpu interface mapping in the guest */
	153	phys_addr_t vgic_dist_base;
	154	phys_addr_t vgic_cpu_base;
b47ef92a MZ	155
	156	/* Distributor enabled */
	157	u32 enabled;
	158
	159	/* Interrupt enabled (one bit per IRQ) */
	160	struct vgic_bitmap irq_enabled;
	161
faa1b46c CD	162	/* Level-triggered interrupt external input is asserted */
	163	struct vgic_bitmap irq_level;
	164
	165	/*
	166	* Interrupt state is pending on the distributor
	167	*/
227844f5	168	struct vgic_bitmap irq_pending;
b47ef92a	169
faa1b46c CD	170	/*
	171	* Tracks writes to GICD_ISPENDRn and GICD_ICPENDRn for level-triggered
	172	* interrupts. Essentially holds the state of the flip-flop in
	173	* Figure 4-10 on page 4-101 in ARM IHI 0048B.b.
	174	* Once set, it is only cleared for level-triggered interrupts on
	175	* guest ACKs (when we queue it) or writes to GICD_ICPENDRn.
	176	*/
	177	struct vgic_bitmap irq_soft_pend;
	178
dbf20f9d CD	179	/* Level-triggered interrupt queued on VCPU interface */
dbf20f9d CD	180	struct vgic_bitmap irq_queued;
b47ef92a MZ	181
	182	/* Interrupt priority. Not used yet. */
	183	struct vgic_bytemap irq_priority;
	184
	185	/* Level/edge triggered */
	186	struct vgic_bitmap irq_cfg;
	187
c1bfb577 MZ	188	/*
	189	* Source CPU per SGI and target CPU:
	190	*
	191	* Each byte represent a SGI observable on a VCPU, each bit of
	192	* this byte indicating if the corresponding VCPU has
	193	* generated this interrupt. This is a GICv2 feature only.
	194	*
	195	* For VCPUn (n < 8), irq_sgi_sources[n16] to [n16 + 15] are
	196	* the SGIs observable on VCPUn.
	197	*/
	198	u8 *irq_sgi_sources;
b47ef92a	199
c1bfb577 MZ	200	/*
	201	* Target CPU for each SPI:
	202	*
	203	* Array of available SPI, each byte indicating the target
	204	* VCPU for SPI. IRQn (n >=32) is at irq_spi_cpu[n-32].
	205	*/
	206	u8 *irq_spi_cpu;
	207
	208	/*
	209	* Reverse lookup of irq_spi_cpu for faster compute pending:
	210	*
	211	* Array of bitmaps, one per VCPU, describing if IRQn is
	212	* routed to a particular VCPU.
	213	*/
	214	struct vgic_bitmap *irq_spi_target;
b47ef92a MZ	215
b47ef92a MZ	216	/* Bitmap indicating which CPU has something pending */
c1bfb577	217	unsigned long *irq_pending_on_cpu;
b47ef92a	218	#endif
1a89dd91 MZ	219	};
1a89dd91 MZ	220
eede821d MZ	221	struct vgic_v2_cpu_if {
	222	u32 vgic_hcr;
	223	u32 vgic_vmcr;
	224	u32 vgic_misr; /* Saved only */
2df36a5d CD	225	u64 vgic_eisr; /* Saved only */
2df36a5d CD	226	u64 vgic_elrsr; /* Saved only */
eede821d	227	u32 vgic_apr;
8f186d52	228	u32 vgic_lr[VGIC_V2_MAX_LRS];
eede821d MZ	229	};
eede821d MZ	230
b2fb1c0d MZ	231	struct vgic_v3_cpu_if {
	232	#ifdef CONFIG_ARM_GIC_V3
	233	u32 vgic_hcr;
	234	u32 vgic_vmcr;
	235	u32 vgic_misr; /* Saved only */
	236	u32 vgic_eisr; /* Saved only */
	237	u32 vgic_elrsr; /* Saved only */
	238	u32 vgic_ap0r[4];
	239	u32 vgic_ap1r[4];
	240	u64 vgic_lr[VGIC_V3_MAX_LRS];
	241	#endif
	242	};
	243
1a89dd91	244	struct vgic_cpu {
9d949dce MZ	245	#ifdef CONFIG_KVM_ARM_VGIC
9d949dce MZ	246	/* per IRQ to LR mapping */
c1bfb577	247	u8 *vgic_irq_lr_map;
9d949dce MZ	248
	249	/* Pending interrupts on this VCPU */
	250	DECLARE_BITMAP( pending_percpu, VGIC_NR_PRIVATE_IRQS);
c1bfb577	251	unsigned long *pending_shared;
9d949dce MZ	252
9d949dce MZ	253	/* Bitmap of used/free list registers */
8f186d52	254	DECLARE_BITMAP( lr_used, VGIC_V2_MAX_LRS);
9d949dce MZ	255
	256	/* Number of list registers on this CPU */
	257	int nr_lr;
	258
	259	/* CPU vif control registers for world switch */
eede821d MZ	260	union {
eede821d MZ	261	struct vgic_v2_cpu_if vgic_v2;
b2fb1c0d	262	struct vgic_v3_cpu_if vgic_v3;
eede821d	263	};
9d949dce	264	#endif
1a89dd91 MZ	265	};
1a89dd91 MZ	266
9d949dce MZ	267	#define LR_EMPTY 0xff
9d949dce MZ	268
495dd859 MZ	269	#define INT_STATUS_EOI (1 << 0)
	270	#define INT_STATUS_UNDERFLOW (1 << 1)
	271
1a89dd91 MZ	272	struct kvm;
	273	struct kvm_vcpu;
	274	struct kvm_run;
	275	struct kvm_exit_mmio;
	276
	277	#ifdef CONFIG_KVM_ARM_VGIC
ce01e4e8	278	int kvm_vgic_addr(struct kvm kvm, unsigned long type, u64 addr, bool write);
01ac5e34	279	int kvm_vgic_hyp_init(void);
6d3cfbe2	280	int kvm_vgic_map_resources(struct kvm *kvm);
59892136	281	int kvm_vgic_create(struct kvm *kvm, u32 type);
c1bfb577	282	void kvm_vgic_destroy(struct kvm *kvm);
c1bfb577	283	void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
9d949dce MZ	284	void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
9d949dce MZ	285	void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
5863c2ce MZ	286	int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
5863c2ce MZ	287	bool level);
9d949dce	288	int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
1a89dd91 MZ	289	bool vgic_handle_mmio(struct kvm_vcpu vcpu, struct kvm_run run,
	290	struct kvm_exit_mmio *mmio);
	291
f982cf4e	292	#define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel))
1f57be28	293	#define vgic_initialized(k) (!!((k)->arch.vgic.nr_cpus))
c52edf5f	294	#define vgic_ready(k) ((k)->arch.vgic.ready)
9d949dce	295
8f186d52 MZ	296	int vgic_v2_probe(struct device_node *vgic_node,
	297	const struct vgic_ops **ops,
	298	const struct vgic_params **params);
b2fb1c0d MZ	299	#ifdef CONFIG_ARM_GIC_V3
	300	int vgic_v3_probe(struct device_node *vgic_node,
	301	const struct vgic_ops **ops,
	302	const struct vgic_params **params);
	303	#else
	304	static inline int vgic_v3_probe(struct device_node *vgic_node,
	305	const struct vgic_ops **ops,
	306	const struct vgic_params **params)
	307	{
	308	return -ENODEV;
	309	}
	310	#endif
8f186d52	311
1a89dd91 MZ	312	#else
	313	static inline int kvm_vgic_hyp_init(void)
	314	{
	315	return 0;
	316	}
	317
330690cd CD	318	static inline int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr)
	319	{
	320	return 0;
	321	}
	322
6cbde825 MZ	323	static inline int kvm_vgic_addr(struct kvm kvm, unsigned long type, u64 addr, bool write)
	324	{
	325	return -ENXIO;
	326	}
	327
6d3cfbe2	328	static inline int kvm_vgic_map_resources(struct kvm *kvm)
1a89dd91 MZ	329	{
	330	return 0;
	331	}
	332
59892136	333	static inline int kvm_vgic_create(struct kvm *kvm, u32 type)
1a89dd91 MZ	334	{
	335	return 0;
	336	}
	337
b5e7a955 AB	338	static inline void kvm_vgic_destroy(struct kvm *kvm)
	339	{
	340	}
	341
	342	static inline void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu)
	343	{
	344	}
	345
1a89dd91 MZ	346	static inline int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu)
	347	{
	348	return 0;
	349	}
	350
	351	static inline void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) {}
	352	static inline void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) {}
	353
5863c2ce MZ	354	static inline int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid,
	355	unsigned int irq_num, bool level)
	356	{
	357	return 0;
	358	}
	359
1a89dd91 MZ	360	static inline int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
	361	{
	362	return 0;
	363	}
	364
	365	static inline bool vgic_handle_mmio(struct kvm_vcpu vcpu, struct kvm_run run,
	366	struct kvm_exit_mmio *mmio)
	367	{
	368	return false;
	369	}
	370
	371	static inline int irqchip_in_kernel(struct kvm *kvm)
	372	{
	373	return 0;
	374	}
01ac5e34	375
1f57be28 CD	376	static inline bool vgic_initialized(struct kvm *kvm)
	377	{
	378	return true;
	379	}
	380
c52edf5f	381	static inline bool vgic_ready(struct kvm *kvm)
01ac5e34 MZ	382	{
	383	return true;
	384	}
1a89dd91 MZ	385	#endif
	386
	387	#endif