[linux-2.6-block.git] / include / kvm / arm_pmu.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (C) 2015 Linaro Ltd.
 * Author: Shannon Zhao <shannon.zhao@linaro.org>
 */

#ifndef __ASM_ARM_KVM_PMU_H
#define __ASM_ARM_KVM_PMU_H

#include <linux/perf_event.h>
#include <asm/perf_event.h>

#define ARMV8_PMU_CYCLE_IDX		(ARMV8_PMU_MAX_COUNTERS - 1)
#define ARMV8_PMU_MAX_COUNTER_PAIRS	((ARMV8_PMU_MAX_COUNTERS + 1) >> 1)

#ifdef CONFIG_KVM_ARM_PMU

struct kvm_pmc {
	u8 idx;	/* index into the pmu->pmc array */
	struct perf_event *perf_event;
};

struct kvm_pmu {
	int irq_num;
	struct kvm_pmc pmc[ARMV8_PMU_MAX_COUNTERS];
	DECLARE_BITMAP(chained, ARMV8_PMU_MAX_COUNTER_PAIRS);
	bool ready;
	bool created;
	bool irq_level;
};

#define kvm_arm_pmu_v3_ready(v)		((v)->arch.pmu.ready)
#define kvm_arm_pmu_irq_initialized(v)	((v)->arch.pmu.irq_num >= VGIC_NR_SGIS)
u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx);
void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, u64 select_idx, u64 val);
u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu);
void kvm_pmu_vcpu_init(struct kvm_vcpu *vcpu);
void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu);
void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu);
void kvm_pmu_disable_counter_mask(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_enable_counter_mask(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu);
void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu);
bool kvm_pmu_should_notify_user(struct kvm_vcpu *vcpu);
void kvm_pmu_update_run(struct kvm_vcpu *vcpu);
void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
				    u64 select_idx);
bool kvm_arm_support_pmu_v3(void);
int kvm_arm_pmu_v3_set_attr(struct kvm_vcpu *vcpu,
			    struct kvm_device_attr *attr);
int kvm_arm_pmu_v3_get_attr(struct kvm_vcpu *vcpu,
			    struct kvm_device_attr *attr);
int kvm_arm_pmu_v3_has_attr(struct kvm_vcpu *vcpu,
			    struct kvm_device_attr *attr);
int kvm_arm_pmu_v3_enable(struct kvm_vcpu *vcpu);
#else
struct kvm_pmu {
};

#define kvm_arm_pmu_v3_ready(v)		(false)
#define kvm_arm_pmu_irq_initialized(v)	(false)
static inline u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu,
					    u64 select_idx)
{
	return 0;
}
static inline void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu,
					     u64 select_idx, u64 val) {}
static inline u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu)
{
	return 0;
}
static inline void kvm_pmu_vcpu_init(struct kvm_vcpu *vcpu) {}
static inline void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu) {}
static inline void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu) {}
static inline void kvm_pmu_disable_counter_mask(struct kvm_vcpu *vcpu, u64 val) {}
static inline void kvm_pmu_enable_counter_mask(struct kvm_vcpu *vcpu, u64 val) {}
static inline void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu) {}
static inline void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu) {}
static inline bool kvm_pmu_should_notify_user(struct kvm_vcpu *vcpu)
{
	return false;
}
static inline void kvm_pmu_update_run(struct kvm_vcpu *vcpu) {}
static inline void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val) {}
static inline void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val) {}
static inline void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu,
						  u64 data, u64 select_idx) {}
static inline bool kvm_arm_support_pmu_v3(void) { return false; }
static inline int kvm_arm_pmu_v3_set_attr(struct kvm_vcpu *vcpu,
					  struct kvm_device_attr *attr)
{
	return -ENXIO;
}
static inline int kvm_arm_pmu_v3_get_attr(struct kvm_vcpu *vcpu,
					  struct kvm_device_attr *attr)
{
	return -ENXIO;
}
static inline int kvm_arm_pmu_v3_has_attr(struct kvm_vcpu *vcpu,
					  struct kvm_device_attr *attr)
{
	return -ENXIO;
}
static inline int kvm_arm_pmu_v3_enable(struct kvm_vcpu *vcpu)
{
	return 0;
}
#endif

#endif
Commit	Line	Data
caab277b	1	/* SPDX-License-Identifier: GPL-2.0-only */
04fe4726 SZ	2	/*
	3	* Copyright (C) 2015 Linaro Ltd.
	4	* Author: Shannon Zhao <shannon.zhao@linaro.org>
04fe4726 SZ	5	*/
	6
	7	#ifndef __ASM_ARM_KVM_PMU_H
	8	#define __ASM_ARM_KVM_PMU_H
	9
04fe4726 SZ	10	#include <linux/perf_event.h>
	11	#include <asm/perf_event.h>
	12
051ff581	13	#define ARMV8_PMU_CYCLE_IDX (ARMV8_PMU_MAX_COUNTERS - 1)
80f393a2	14	#define ARMV8_PMU_MAX_COUNTER_PAIRS ((ARMV8_PMU_MAX_COUNTERS + 1) >> 1)
051ff581	15
0efce9da SH	16	#ifdef CONFIG_KVM_ARM_PMU
0efce9da SH	17
04fe4726 SZ	18	struct kvm_pmc {
	19	u8 idx; /* index into the pmu->pmc array */
	20	struct perf_event *perf_event;
04fe4726 SZ	21	};
	22
	23	struct kvm_pmu {
	24	int irq_num;
	25	struct kvm_pmc pmc[ARMV8_PMU_MAX_COUNTERS];
80f393a2	26	DECLARE_BITMAP(chained, ARMV8_PMU_MAX_COUNTER_PAIRS);
04fe4726	27	bool ready;
a2befacf	28	bool created;
b02386eb	29	bool irq_level;
04fe4726	30	};
ab946834 SZ	31
ab946834 SZ	32	#define kvm_arm_pmu_v3_ready(v) ((v)->arch.pmu.ready)
bb0c70bc	33	#define kvm_arm_pmu_irq_initialized(v) ((v)->arch.pmu.irq_num >= VGIC_NR_SGIS)
051ff581 SZ	34	u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx);
051ff581 SZ	35	void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, u64 select_idx, u64 val);
96b0eebc	36	u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu);
bca031e2	37	void kvm_pmu_vcpu_init(struct kvm_vcpu *vcpu);
2aa36e98	38	void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu);
5f0a714a	39	void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu);
418e5ca8 AM	40	void kvm_pmu_disable_counter_mask(struct kvm_vcpu *vcpu, u64 val);
418e5ca8 AM	41	void kvm_pmu_enable_counter_mask(struct kvm_vcpu *vcpu, u64 val);
b02386eb SZ	42	void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu);
b02386eb SZ	43	void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu);
3dbbdf78 CD	44	bool kvm_pmu_should_notify_user(struct kvm_vcpu *vcpu);
3dbbdf78 CD	45	void kvm_pmu_update_run(struct kvm_vcpu *vcpu);
7a0adc70	46	void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val);
76993739	47	void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val);
7f766358 SZ	48	void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
7f766358 SZ	49	u64 select_idx);
808e7381	50	bool kvm_arm_support_pmu_v3(void);
bb0c70bc SZ	51	int kvm_arm_pmu_v3_set_attr(struct kvm_vcpu *vcpu,
	52	struct kvm_device_attr *attr);
	53	int kvm_arm_pmu_v3_get_attr(struct kvm_vcpu *vcpu,
	54	struct kvm_device_attr *attr);
	55	int kvm_arm_pmu_v3_has_attr(struct kvm_vcpu *vcpu,
	56	struct kvm_device_attr *attr);
a2befacf	57	int kvm_arm_pmu_v3_enable(struct kvm_vcpu *vcpu);
04fe4726 SZ	58	#else
	59	struct kvm_pmu {
	60	};
ab946834 SZ	61
ab946834 SZ	62	#define kvm_arm_pmu_v3_ready(v) (false)
bb0c70bc	63	#define kvm_arm_pmu_irq_initialized(v) (false)
051ff581 SZ	64	static inline u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu,
	65	u64 select_idx)
	66	{
	67	return 0;
	68	}
	69	static inline void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu,
	70	u64 select_idx, u64 val) {}
96b0eebc SZ	71	static inline u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu)
	72	{
	73	return 0;
	74	}
bca031e2	75	static inline void kvm_pmu_vcpu_init(struct kvm_vcpu *vcpu) {}
2aa36e98	76	static inline void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu) {}
5f0a714a	77	static inline void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu) {}
418e5ca8 AM	78	static inline void kvm_pmu_disable_counter_mask(struct kvm_vcpu *vcpu, u64 val) {}
418e5ca8 AM	79	static inline void kvm_pmu_enable_counter_mask(struct kvm_vcpu *vcpu, u64 val) {}
b02386eb SZ	80	static inline void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu) {}
b02386eb SZ	81	static inline void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu) {}
3dbbdf78 CD	82	static inline bool kvm_pmu_should_notify_user(struct kvm_vcpu *vcpu)
	83	{
	84	return false;
	85	}
	86	static inline void kvm_pmu_update_run(struct kvm_vcpu *vcpu) {}
7a0adc70	87	static inline void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val) {}
76993739	88	static inline void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val) {}
7f766358 SZ	89	static inline void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu,
7f766358 SZ	90	u64 data, u64 select_idx) {}
808e7381	91	static inline bool kvm_arm_support_pmu_v3(void) { return false; }
bb0c70bc SZ	92	static inline int kvm_arm_pmu_v3_set_attr(struct kvm_vcpu *vcpu,
	93	struct kvm_device_attr *attr)
	94	{
	95	return -ENXIO;
	96	}
	97	static inline int kvm_arm_pmu_v3_get_attr(struct kvm_vcpu *vcpu,
	98	struct kvm_device_attr *attr)
	99	{
	100	return -ENXIO;
	101	}
	102	static inline int kvm_arm_pmu_v3_has_attr(struct kvm_vcpu *vcpu,
	103	struct kvm_device_attr *attr)
	104	{
	105	return -ENXIO;
	106	}
a2befacf CD	107	static inline int kvm_arm_pmu_v3_enable(struct kvm_vcpu *vcpu)
	108	{
	109	return 0;
	110	}
04fe4726 SZ	111	#endif
	112
	113	#endif