Commit | Line | Data |
---|---|---|
caab277b | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
04fe4726 SZ |
2 | /* |
3 | * Copyright (C) 2015 Linaro Ltd. | |
4 | * Author: Shannon Zhao <shannon.zhao@linaro.org> | |
04fe4726 SZ |
5 | */ |
6 | ||
7 | #ifndef __ASM_ARM_KVM_PMU_H | |
8 | #define __ASM_ARM_KVM_PMU_H | |
9 | ||
04fe4726 | 10 | #include <linux/perf_event.h> |
7755cec6 | 11 | #include <linux/perf/arm_pmuv3.h> |
04fe4726 | 12 | |
051ff581 SZ |
13 | #define ARMV8_PMU_CYCLE_IDX (ARMV8_PMU_MAX_COUNTERS - 1) |
14 | ||
9b80b967 | 15 | #if IS_ENABLED(CONFIG_HW_PERF_EVENTS) && IS_ENABLED(CONFIG_KVM) |
04fe4726 SZ |
16 | struct kvm_pmc { |
17 | u8 idx; /* index into the pmu->pmc array */ | |
18 | struct perf_event *perf_event; | |
04fe4726 SZ |
19 | }; |
20 | ||
84d751a0 FT |
21 | struct kvm_pmu_events { |
22 | u32 events_host; | |
23 | u32 events_guest; | |
24 | }; | |
25 | ||
04fe4726 | 26 | struct kvm_pmu { |
e987a4c6 | 27 | struct irq_work overflow_work; |
84d751a0 | 28 | struct kvm_pmu_events events; |
04fe4726 | 29 | struct kvm_pmc pmc[ARMV8_PMU_MAX_COUNTERS]; |
e987a4c6 | 30 | int irq_num; |
a2befacf | 31 | bool created; |
b02386eb | 32 | bool irq_level; |
04fe4726 | 33 | }; |
ab946834 | 34 | |
db858060 AE |
35 | struct arm_pmu_entry { |
36 | struct list_head entry; | |
37 | struct arm_pmu *arm_pmu; | |
38 | }; | |
39 | ||
be399d82 SC |
40 | DECLARE_STATIC_KEY_FALSE(kvm_arm_pmu_available); |
41 | ||
42 | static __always_inline bool kvm_arm_support_pmu_v3(void) | |
43 | { | |
44 | return static_branch_likely(&kvm_arm_pmu_available); | |
45 | } | |
46 | ||
bb0c70bc | 47 | #define kvm_arm_pmu_irq_initialized(v) ((v)->arch.pmu.irq_num >= VGIC_NR_SGIS) |
051ff581 SZ |
48 | u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx); |
49 | void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, u64 select_idx, u64 val); | |
96b0eebc | 50 | u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu); |
88865bec | 51 | u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmceid1); |
bca031e2 | 52 | void kvm_pmu_vcpu_init(struct kvm_vcpu *vcpu); |
2aa36e98 | 53 | void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu); |
5f0a714a | 54 | void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu); |
418e5ca8 AM |
55 | void kvm_pmu_disable_counter_mask(struct kvm_vcpu *vcpu, u64 val); |
56 | void kvm_pmu_enable_counter_mask(struct kvm_vcpu *vcpu, u64 val); | |
b02386eb SZ |
57 | void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu); |
58 | void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu); | |
3dbbdf78 CD |
59 | bool kvm_pmu_should_notify_user(struct kvm_vcpu *vcpu); |
60 | void kvm_pmu_update_run(struct kvm_vcpu *vcpu); | |
7a0adc70 | 61 | void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val); |
76993739 | 62 | void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val); |
7f766358 SZ |
63 | void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data, |
64 | u64 select_idx); | |
27131b19 | 65 | void kvm_vcpu_reload_pmu(struct kvm_vcpu *vcpu); |
bb0c70bc SZ |
66 | int kvm_arm_pmu_v3_set_attr(struct kvm_vcpu *vcpu, |
67 | struct kvm_device_attr *attr); | |
68 | int kvm_arm_pmu_v3_get_attr(struct kvm_vcpu *vcpu, | |
69 | struct kvm_device_attr *attr); | |
70 | int kvm_arm_pmu_v3_has_attr(struct kvm_vcpu *vcpu, | |
71 | struct kvm_device_attr *attr); | |
a2befacf | 72 | int kvm_arm_pmu_v3_enable(struct kvm_vcpu *vcpu); |
20492a62 MZ |
73 | |
74 | struct kvm_pmu_events *kvm_get_pmu_events(void); | |
75 | void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu); | |
76 | void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu); | |
b1f778a2 | 77 | void kvm_vcpu_pmu_resync_el0(void); |
20492a62 MZ |
78 | |
79 | #define kvm_vcpu_has_pmu(vcpu) \ | |
1de10b7d | 80 | (vcpu_has_feature(vcpu, KVM_ARM_VCPU_PMU_V3)) |
20492a62 MZ |
81 | |
82 | /* | |
83 | * Updates the vcpu's view of the pmu events for this cpu. | |
84 | * Must be called before every vcpu run after disabling interrupts, to ensure | |
85 | * that an interrupt cannot fire and update the structure. | |
86 | */ | |
87 | #define kvm_pmu_update_vcpu_events(vcpu) \ | |
88 | do { \ | |
89 | if (!has_vhe() && kvm_vcpu_has_pmu(vcpu)) \ | |
90 | vcpu->arch.pmu.events = *kvm_get_pmu_events(); \ | |
91 | } while (0) | |
92 | ||
11af4c37 MZ |
93 | /* |
94 | * Evaluates as true when emulating PMUv3p5, and false otherwise. | |
95 | */ | |
68667240 OU |
96 | #define kvm_pmu_is_3p5(vcpu) ({ \ |
97 | u64 val = IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1); \ | |
98 | u8 pmuver = SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, val); \ | |
99 | \ | |
100 | pmuver >= ID_AA64DFR0_EL1_PMUVer_V3P5; \ | |
101 | }) | |
11af4c37 | 102 | |
3d0dba57 | 103 | u8 kvm_arm_pmu_get_pmuver_limit(void); |
bc512d6a | 104 | u64 kvm_pmu_evtyper_mask(struct kvm *kvm); |
42773357 | 105 | int kvm_arm_set_default_pmu(struct kvm *kvm); |
4d20debf | 106 | u8 kvm_arm_pmu_get_max_counters(struct kvm *kvm); |
3d0dba57 | 107 | |
57fc267f | 108 | u64 kvm_vcpu_read_pmcr(struct kvm_vcpu *vcpu); |
04fe4726 SZ |
109 | #else |
110 | struct kvm_pmu { | |
111 | }; | |
ab946834 | 112 | |
be399d82 SC |
113 | static inline bool kvm_arm_support_pmu_v3(void) |
114 | { | |
115 | return false; | |
116 | } | |
117 | ||
bb0c70bc | 118 | #define kvm_arm_pmu_irq_initialized(v) (false) |
051ff581 SZ |
119 | static inline u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, |
120 | u64 select_idx) | |
121 | { | |
122 | return 0; | |
123 | } | |
124 | static inline void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, | |
125 | u64 select_idx, u64 val) {} | |
96b0eebc SZ |
126 | static inline u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu) |
127 | { | |
128 | return 0; | |
129 | } | |
bca031e2 | 130 | static inline void kvm_pmu_vcpu_init(struct kvm_vcpu *vcpu) {} |
2aa36e98 | 131 | static inline void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu) {} |
5f0a714a | 132 | static inline void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu) {} |
418e5ca8 AM |
133 | static inline void kvm_pmu_disable_counter_mask(struct kvm_vcpu *vcpu, u64 val) {} |
134 | static inline void kvm_pmu_enable_counter_mask(struct kvm_vcpu *vcpu, u64 val) {} | |
b02386eb SZ |
135 | static inline void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu) {} |
136 | static inline void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu) {} | |
3dbbdf78 CD |
137 | static inline bool kvm_pmu_should_notify_user(struct kvm_vcpu *vcpu) |
138 | { | |
139 | return false; | |
140 | } | |
141 | static inline void kvm_pmu_update_run(struct kvm_vcpu *vcpu) {} | |
7a0adc70 | 142 | static inline void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val) {} |
76993739 | 143 | static inline void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val) {} |
7f766358 SZ |
144 | static inline void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, |
145 | u64 data, u64 select_idx) {} | |
bb0c70bc SZ |
146 | static inline int kvm_arm_pmu_v3_set_attr(struct kvm_vcpu *vcpu, |
147 | struct kvm_device_attr *attr) | |
148 | { | |
149 | return -ENXIO; | |
150 | } | |
151 | static inline int kvm_arm_pmu_v3_get_attr(struct kvm_vcpu *vcpu, | |
152 | struct kvm_device_attr *attr) | |
153 | { | |
154 | return -ENXIO; | |
155 | } | |
156 | static inline int kvm_arm_pmu_v3_has_attr(struct kvm_vcpu *vcpu, | |
157 | struct kvm_device_attr *attr) | |
158 | { | |
159 | return -ENXIO; | |
160 | } | |
a2befacf CD |
161 | static inline int kvm_arm_pmu_v3_enable(struct kvm_vcpu *vcpu) |
162 | { | |
163 | return 0; | |
164 | } | |
88865bec MZ |
165 | static inline u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmceid1) |
166 | { | |
167 | return 0; | |
168 | } | |
5421db1b | 169 | |
20492a62 | 170 | #define kvm_vcpu_has_pmu(vcpu) ({ false; }) |
11af4c37 | 171 | #define kvm_pmu_is_3p5(vcpu) ({ false; }) |
20492a62 MZ |
172 | static inline void kvm_pmu_update_vcpu_events(struct kvm_vcpu *vcpu) {} |
173 | static inline void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu) {} | |
174 | static inline void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu) {} | |
27131b19 | 175 | static inline void kvm_vcpu_reload_pmu(struct kvm_vcpu *vcpu) {} |
3d0dba57 MZ |
176 | static inline u8 kvm_arm_pmu_get_pmuver_limit(void) |
177 | { | |
178 | return 0; | |
179 | } | |
bc512d6a OU |
180 | static inline u64 kvm_pmu_evtyper_mask(struct kvm *kvm) |
181 | { | |
182 | return 0; | |
183 | } | |
b1f778a2 | 184 | static inline void kvm_vcpu_pmu_resync_el0(void) {} |
20492a62 | 185 | |
42773357 RW |
186 | static inline int kvm_arm_set_default_pmu(struct kvm *kvm) |
187 | { | |
188 | return -ENODEV; | |
189 | } | |
190 | ||
4d20debf RRA |
191 | static inline u8 kvm_arm_pmu_get_max_counters(struct kvm *kvm) |
192 | { | |
193 | return 0; | |
194 | } | |
195 | ||
57fc267f RW |
196 | static inline u64 kvm_vcpu_read_pmcr(struct kvm_vcpu *vcpu) |
197 | { | |
198 | return 0; | |
199 | } | |
200 | ||
04fe4726 SZ |
201 | #endif |
202 | ||
203 | #endif |