[linux-2.6-block.git] / include / dt-bindings / reset / mt8135-resets.h

/*
 * Copyright (c) 2014 MediaTek Inc.
 * Author: Flora Fu, MediaTek
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8135
#define _DT_BINDINGS_RESET_CONTROLLER_MT8135

/* INFRACFG resets */
#define MT8135_INFRA_EMI_REG_RST        0
#define MT8135_INFRA_DRAMC0_A0_RST      1
#define MT8135_INFRA_CCIF0_RST          2
#define MT8135_INFRA_APCIRQ_EINT_RST    3
#define MT8135_INFRA_APXGPT_RST         4
#define MT8135_INFRA_SCPSYS_RST         5
#define MT8135_INFRA_CCIF1_RST          6
#define MT8135_INFRA_PMIC_WRAP_RST      7
#define MT8135_INFRA_KP_RST             8
#define MT8135_INFRA_EMI_RST            32
#define MT8135_INFRA_DRAMC0_RST         34
#define MT8135_INFRA_SMI_RST            35
#define MT8135_INFRA_M4U_RST            36

/*  PERICFG resets */
#define MT8135_PERI_UART0_SW_RST        0
#define MT8135_PERI_UART1_SW_RST        1
#define MT8135_PERI_UART2_SW_RST        2
#define MT8135_PERI_UART3_SW_RST        3
#define MT8135_PERI_IRDA_SW_RST         4
#define MT8135_PERI_PTP_SW_RST          5
#define MT8135_PERI_AP_HIF_SW_RST       6
#define MT8135_PERI_GPCU_SW_RST         7
#define MT8135_PERI_MD_HIF_SW_RST       8
#define MT8135_PERI_NLI_SW_RST          9
#define MT8135_PERI_AUXADC_SW_RST       10
#define MT8135_PERI_DMA_SW_RST          11
#define MT8135_PERI_NFI_SW_RST          14
#define MT8135_PERI_PWM_SW_RST          15
#define MT8135_PERI_THERM_SW_RST        16
#define MT8135_PERI_MSDC0_SW_RST        17
#define MT8135_PERI_MSDC1_SW_RST        18
#define MT8135_PERI_MSDC2_SW_RST        19
#define MT8135_PERI_MSDC3_SW_RST        20
#define MT8135_PERI_I2C0_SW_RST         22
#define MT8135_PERI_I2C1_SW_RST         23
#define MT8135_PERI_I2C2_SW_RST         24
#define MT8135_PERI_I2C3_SW_RST         25
#define MT8135_PERI_I2C4_SW_RST         26
#define MT8135_PERI_I2C5_SW_RST         27
#define MT8135_PERI_I2C6_SW_RST         28
#define MT8135_PERI_USB_SW_RST          29
#define MT8135_PERI_SPI1_SW_RST         33
#define MT8135_PERI_PWRAP_BRIDGE_SW_RST 34

#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8135 */
Commit	Line	Data
a8aede79 JL	1	/*
	2	* Copyright (c) 2014 MediaTek Inc.
	3	* Author: Flora Fu, MediaTek
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*/
	14
	15	#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8135
	16	#define _DT_BINDINGS_RESET_CONTROLLER_MT8135
	17
	18	/* INFRACFG resets */
	19	#define MT8135_INFRA_EMI_REG_RST 0
	20	#define MT8135_INFRA_DRAMC0_A0_RST 1
	21	#define MT8135_INFRA_CCIF0_RST 2
	22	#define MT8135_INFRA_APCIRQ_EINT_RST 3
	23	#define MT8135_INFRA_APXGPT_RST 4
	24	#define MT8135_INFRA_SCPSYS_RST 5
	25	#define MT8135_INFRA_CCIF1_RST 6
	26	#define MT8135_INFRA_PMIC_WRAP_RST 7
	27	#define MT8135_INFRA_KP_RST 8
	28	#define MT8135_INFRA_EMI_RST 32
	29	#define MT8135_INFRA_DRAMC0_RST 34
	30	#define MT8135_INFRA_SMI_RST 35
	31	#define MT8135_INFRA_M4U_RST 36
	32
	33	/* PERICFG resets */
	34	#define MT8135_PERI_UART0_SW_RST 0
	35	#define MT8135_PERI_UART1_SW_RST 1
	36	#define MT8135_PERI_UART2_SW_RST 2
	37	#define MT8135_PERI_UART3_SW_RST 3
	38	#define MT8135_PERI_IRDA_SW_RST 4
	39	#define MT8135_PERI_PTP_SW_RST 5
	40	#define MT8135_PERI_AP_HIF_SW_RST 6
	41	#define MT8135_PERI_GPCU_SW_RST 7
	42	#define MT8135_PERI_MD_HIF_SW_RST 8
	43	#define MT8135_PERI_NLI_SW_RST 9
	44	#define MT8135_PERI_AUXADC_SW_RST 10
	45	#define MT8135_PERI_DMA_SW_RST 11
	46	#define MT8135_PERI_NFI_SW_RST 14
	47	#define MT8135_PERI_PWM_SW_RST 15
	48	#define MT8135_PERI_THERM_SW_RST 16
	49	#define MT8135_PERI_MSDC0_SW_RST 17
	50	#define MT8135_PERI_MSDC1_SW_RST 18
	51	#define MT8135_PERI_MSDC2_SW_RST 19
	52	#define MT8135_PERI_MSDC3_SW_RST 20
	53	#define MT8135_PERI_I2C0_SW_RST 22
	54	#define MT8135_PERI_I2C1_SW_RST 23
	55	#define MT8135_PERI_I2C2_SW_RST 24
	56	#define MT8135_PERI_I2C3_SW_RST 25
	57	#define MT8135_PERI_I2C4_SW_RST 26
	58	#define MT8135_PERI_I2C5_SW_RST 27
	59	#define MT8135_PERI_I2C6_SW_RST 28
	60	#define MT8135_PERI_USB_SW_RST 29
	61	#define MT8135_PERI_SPI1_SW_RST 33
	62	#define MT8135_PERI_PWRAP_BRIDGE_SW_RST 34
	63
	64	#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8135 */