Commit | Line | Data |
---|---|---|
b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
1d15cb9c TR |
2 | /* |
3 | * This header provides constants for binding nvidia,tegra210-car. | |
4 | * | |
5 | * The first 224 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB | |
6 | * registers. These IDs often match those in the CAR's RST_DEVICES registers, | |
7 | * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In | |
8 | * this case, those clocks are assigned IDs above 224 in order to highlight | |
9 | * this issue. Implementations that interpret these clock IDs as bit values | |
10 | * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to | |
11 | * explicitly handle these special cases. | |
12 | * | |
13 | * The balance of the clocks controlled by the CAR are assigned IDs of 224 and | |
14 | * above. | |
15 | */ | |
16 | ||
17 | #ifndef _DT_BINDINGS_CLOCK_TEGRA210_CAR_H | |
18 | #define _DT_BINDINGS_CLOCK_TEGRA210_CAR_H | |
19 | ||
20 | /* 0 */ | |
21 | /* 1 */ | |
22 | /* 2 */ | |
23 | #define TEGRA210_CLK_ISPB 3 | |
24 | #define TEGRA210_CLK_RTC 4 | |
25 | #define TEGRA210_CLK_TIMER 5 | |
26 | #define TEGRA210_CLK_UARTA 6 | |
27 | /* 7 (register bit affects uartb and vfir) */ | |
28 | #define TEGRA210_CLK_GPIO 8 | |
29 | #define TEGRA210_CLK_SDMMC2 9 | |
30 | /* 10 (register bit affects spdif_in and spdif_out) */ | |
31 | #define TEGRA210_CLK_I2S1 11 | |
32 | #define TEGRA210_CLK_I2C1 12 | |
33 | /* 13 */ | |
34 | #define TEGRA210_CLK_SDMMC1 14 | |
35 | #define TEGRA210_CLK_SDMMC4 15 | |
36 | /* 16 */ | |
37 | #define TEGRA210_CLK_PWM 17 | |
38 | #define TEGRA210_CLK_I2S2 18 | |
39 | /* 19 */ | |
40 | /* 20 (register bit affects vi and vi_sensor) */ | |
41 | /* 21 */ | |
42 | #define TEGRA210_CLK_USBD 22 | |
34ac2c27 | 43 | #define TEGRA210_CLK_ISPA 23 |
1d15cb9c TR |
44 | /* 24 */ |
45 | /* 25 */ | |
46 | #define TEGRA210_CLK_DISP2 26 | |
47 | #define TEGRA210_CLK_DISP1 27 | |
48 | #define TEGRA210_CLK_HOST1X 28 | |
49 | /* 29 */ | |
50 | #define TEGRA210_CLK_I2S0 30 | |
51 | /* 31 */ | |
52 | ||
53 | #define TEGRA210_CLK_MC 32 | |
54 | #define TEGRA210_CLK_AHBDMA 33 | |
55 | #define TEGRA210_CLK_APBDMA 34 | |
56 | /* 35 */ | |
57 | /* 36 */ | |
58 | /* 37 */ | |
59 | #define TEGRA210_CLK_PMC 38 | |
60 | /* 39 (register bit affects fuse and fuse_burn) */ | |
61 | #define TEGRA210_CLK_KFUSE 40 | |
62 | #define TEGRA210_CLK_SBC1 41 | |
63 | /* 42 */ | |
64 | /* 43 */ | |
65 | #define TEGRA210_CLK_SBC2 44 | |
66 | /* 45 */ | |
67 | #define TEGRA210_CLK_SBC3 46 | |
68 | #define TEGRA210_CLK_I2C5 47 | |
69 | #define TEGRA210_CLK_DSIA 48 | |
70 | /* 49 */ | |
71 | /* 50 */ | |
72 | /* 51 */ | |
73 | #define TEGRA210_CLK_CSI 52 | |
74 | /* 53 */ | |
75 | #define TEGRA210_CLK_I2C2 54 | |
76 | #define TEGRA210_CLK_UARTC 55 | |
77 | #define TEGRA210_CLK_MIPI_CAL 56 | |
78 | #define TEGRA210_CLK_EMC 57 | |
79 | #define TEGRA210_CLK_USB2 58 | |
80 | /* 59 */ | |
81 | /* 60 */ | |
82 | /* 61 */ | |
83 | /* 62 */ | |
84 | #define TEGRA210_CLK_BSEV 63 | |
85 | ||
86 | /* 64 */ | |
87 | #define TEGRA210_CLK_UARTD 65 | |
88 | /* 66 */ | |
89 | #define TEGRA210_CLK_I2C3 67 | |
90 | #define TEGRA210_CLK_SBC4 68 | |
91 | #define TEGRA210_CLK_SDMMC3 69 | |
92 | #define TEGRA210_CLK_PCIE 70 | |
93 | #define TEGRA210_CLK_OWR 71 | |
94 | #define TEGRA210_CLK_AFI 72 | |
95 | #define TEGRA210_CLK_CSITE 73 | |
96 | /* 74 */ | |
97 | /* 75 */ | |
89e423c3 | 98 | #define TEGRA210_CLK_LA 76 |
1d15cb9c TR |
99 | /* 77 */ |
100 | #define TEGRA210_CLK_SOC_THERM 78 | |
101 | #define TEGRA210_CLK_DTV 79 | |
102 | /* 80 */ | |
103 | #define TEGRA210_CLK_I2CSLOW 81 | |
104 | #define TEGRA210_CLK_DSIB 82 | |
105 | #define TEGRA210_CLK_TSEC 83 | |
106 | /* 84 */ | |
107 | /* 85 */ | |
108 | /* 86 */ | |
109 | /* 87 */ | |
110 | /* 88 */ | |
111 | #define TEGRA210_CLK_XUSB_HOST 89 | |
112 | /* 90 */ | |
113 | /* 91 */ | |
114 | #define TEGRA210_CLK_CSUS 92 | |
115 | /* 93 */ | |
116 | /* 94 */ | |
117 | /* 95 (bit affects xusb_dev and xusb_dev_src) */ | |
118 | ||
119 | /* 96 */ | |
120 | /* 97 */ | |
121 | /* 98 */ | |
122 | #define TEGRA210_CLK_MSELECT 99 | |
123 | #define TEGRA210_CLK_TSENSOR 100 | |
124 | #define TEGRA210_CLK_I2S3 101 | |
125 | #define TEGRA210_CLK_I2S4 102 | |
126 | #define TEGRA210_CLK_I2C4 103 | |
127 | /* 104 */ | |
128 | /* 105 */ | |
129 | #define TEGRA210_CLK_D_AUDIO 106 | |
29569941 | 130 | #define TEGRA210_CLK_APB2APE 107 |
1d15cb9c TR |
131 | /* 108 */ |
132 | /* 109 */ | |
133 | /* 110 */ | |
134 | #define TEGRA210_CLK_HDA2CODEC_2X 111 | |
135 | /* 112 */ | |
136 | /* 113 */ | |
137 | /* 114 */ | |
138 | /* 115 */ | |
139 | /* 116 */ | |
140 | /* 117 */ | |
141 | #define TEGRA210_CLK_SPDIF_2X 118 | |
142 | #define TEGRA210_CLK_ACTMON 119 | |
143 | #define TEGRA210_CLK_EXTERN1 120 | |
144 | #define TEGRA210_CLK_EXTERN2 121 | |
145 | #define TEGRA210_CLK_EXTERN3 122 | |
146 | #define TEGRA210_CLK_SATA_OOB 123 | |
147 | #define TEGRA210_CLK_SATA 124 | |
148 | #define TEGRA210_CLK_HDA 125 | |
149 | /* 126 */ | |
150 | /* 127 */ | |
151 | ||
152 | #define TEGRA210_CLK_HDA2HDMI 128 | |
153 | /* 129 */ | |
154 | /* 130 */ | |
155 | /* 131 */ | |
156 | /* 132 */ | |
157 | /* 133 */ | |
158 | /* 134 */ | |
159 | /* 135 */ | |
bfa34832 | 160 | #define TEGRA210_CLK_CEC 136 |
1d15cb9c TR |
161 | /* 137 */ |
162 | /* 138 */ | |
163 | /* 139 */ | |
164 | /* 140 */ | |
165 | /* 141 */ | |
166 | /* 142 */ | |
167 | /* (bit affects xusb_falcon_src, xusb_fs_src, xusb_host_src and xusb_ss_src) */ | |
168 | #define TEGRA210_CLK_XUSB_GATE 143 | |
169 | #define TEGRA210_CLK_CILAB 144 | |
170 | #define TEGRA210_CLK_CILCD 145 | |
171 | #define TEGRA210_CLK_CILE 146 | |
172 | #define TEGRA210_CLK_DSIALP 147 | |
173 | #define TEGRA210_CLK_DSIBLP 148 | |
174 | #define TEGRA210_CLK_ENTROPY 149 | |
175 | /* 150 */ | |
176 | /* 151 */ | |
88da44c5 | 177 | #define TEGRA210_CLK_DP2 152 |
1d15cb9c TR |
178 | /* 153 */ |
179 | /* 154 */ | |
180 | /* 155 (bit affects dfll_ref and dfll_soc) */ | |
181 | #define TEGRA210_CLK_XUSB_SS 156 | |
182 | /* 157 */ | |
183 | /* 158 */ | |
184 | /* 159 */ | |
185 | ||
186 | /* 160 */ | |
187 | #define TEGRA210_CLK_DMIC1 161 | |
188 | #define TEGRA210_CLK_DMIC2 162 | |
189 | /* 163 */ | |
190 | /* 164 */ | |
191 | /* 165 */ | |
192 | #define TEGRA210_CLK_I2C6 166 | |
193 | /* 167 */ | |
194 | /* 168 */ | |
195 | /* 169 */ | |
196 | /* 170 */ | |
197 | #define TEGRA210_CLK_VIM2_CLK 171 | |
198 | /* 172 */ | |
199 | #define TEGRA210_CLK_MIPIBIF 173 | |
200 | /* 174 */ | |
201 | /* 175 */ | |
202 | /* 176 */ | |
203 | #define TEGRA210_CLK_CLK72MHZ 177 | |
204 | #define TEGRA210_CLK_VIC03 178 | |
205 | /* 179 */ | |
206 | /* 180 */ | |
207 | #define TEGRA210_CLK_DPAUX 181 | |
208 | #define TEGRA210_CLK_SOR0 182 | |
209 | #define TEGRA210_CLK_SOR1 183 | |
210 | #define TEGRA210_CLK_GPU 184 | |
211 | #define TEGRA210_CLK_DBGAPB 185 | |
212 | /* 186 */ | |
213 | #define TEGRA210_CLK_PLL_P_OUT_ADSP 187 | |
88da44c5 | 214 | /* 188 ((bit affects pll_a_out_adsp and pll_a_out0_out_adsp)*/ |
1d15cb9c TR |
215 | #define TEGRA210_CLK_PLL_G_REF 189 |
216 | /* 190 */ | |
217 | /* 191 */ | |
218 | ||
219 | /* 192 */ | |
220 | #define TEGRA210_CLK_SDMMC_LEGACY 193 | |
221 | #define TEGRA210_CLK_NVDEC 194 | |
222 | #define TEGRA210_CLK_NVJPG 195 | |
223 | /* 196 */ | |
224 | #define TEGRA210_CLK_DMIC3 197 | |
225 | #define TEGRA210_CLK_APE 198 | |
88da44c5 | 226 | #define TEGRA210_CLK_ADSP 199 |
1d15cb9c TR |
227 | /* 200 */ |
228 | /* 201 */ | |
229 | #define TEGRA210_CLK_MAUD 202 | |
230 | /* 203 */ | |
231 | /* 204 */ | |
232 | /* 205 */ | |
233 | #define TEGRA210_CLK_TSECB 206 | |
234 | #define TEGRA210_CLK_DPAUX1 207 | |
235 | #define TEGRA210_CLK_VI_I2C 208 | |
236 | #define TEGRA210_CLK_HSIC_TRK 209 | |
237 | #define TEGRA210_CLK_USB2_TRK 210 | |
238 | #define TEGRA210_CLK_QSPI 211 | |
239 | #define TEGRA210_CLK_UARTAPE 212 | |
240 | /* 213 */ | |
241 | /* 214 */ | |
242 | /* 215 */ | |
243 | /* 216 */ | |
244 | /* 217 */ | |
88da44c5 | 245 | #define TEGRA210_CLK_ADSP_NEON 218 |
1d15cb9c | 246 | #define TEGRA210_CLK_NVENC 219 |
88da44c5 PDS |
247 | #define TEGRA210_CLK_IQC2 220 |
248 | #define TEGRA210_CLK_IQC1 221 | |
1d15cb9c TR |
249 | #define TEGRA210_CLK_SOR_SAFE 222 |
250 | #define TEGRA210_CLK_PLL_P_OUT_CPU 223 | |
251 | ||
252 | ||
253 | #define TEGRA210_CLK_UARTB 224 | |
254 | #define TEGRA210_CLK_VFIR 225 | |
255 | #define TEGRA210_CLK_SPDIF_IN 226 | |
256 | #define TEGRA210_CLK_SPDIF_OUT 227 | |
257 | #define TEGRA210_CLK_VI 228 | |
258 | #define TEGRA210_CLK_VI_SENSOR 229 | |
259 | #define TEGRA210_CLK_FUSE 230 | |
260 | #define TEGRA210_CLK_FUSE_BURN 231 | |
261 | #define TEGRA210_CLK_CLK_32K 232 | |
262 | #define TEGRA210_CLK_CLK_M 233 | |
263 | #define TEGRA210_CLK_CLK_M_DIV2 234 | |
264 | #define TEGRA210_CLK_CLK_M_DIV4 235 | |
e5377ab2 SK |
265 | #define TEGRA210_CLK_OSC_DIV2 234 |
266 | #define TEGRA210_CLK_OSC_DIV4 235 | |
1d15cb9c TR |
267 | #define TEGRA210_CLK_PLL_REF 236 |
268 | #define TEGRA210_CLK_PLL_C 237 | |
269 | #define TEGRA210_CLK_PLL_C_OUT1 238 | |
270 | #define TEGRA210_CLK_PLL_C2 239 | |
271 | #define TEGRA210_CLK_PLL_C3 240 | |
272 | #define TEGRA210_CLK_PLL_M 241 | |
273 | #define TEGRA210_CLK_PLL_M_OUT1 242 | |
274 | #define TEGRA210_CLK_PLL_P 243 | |
275 | #define TEGRA210_CLK_PLL_P_OUT1 244 | |
276 | #define TEGRA210_CLK_PLL_P_OUT2 245 | |
277 | #define TEGRA210_CLK_PLL_P_OUT3 246 | |
278 | #define TEGRA210_CLK_PLL_P_OUT4 247 | |
279 | #define TEGRA210_CLK_PLL_A 248 | |
280 | #define TEGRA210_CLK_PLL_A_OUT0 249 | |
281 | #define TEGRA210_CLK_PLL_D 250 | |
282 | #define TEGRA210_CLK_PLL_D_OUT0 251 | |
283 | #define TEGRA210_CLK_PLL_D2 252 | |
284 | #define TEGRA210_CLK_PLL_D2_OUT0 253 | |
285 | #define TEGRA210_CLK_PLL_U 254 | |
286 | #define TEGRA210_CLK_PLL_U_480M 255 | |
287 | ||
288 | #define TEGRA210_CLK_PLL_U_60M 256 | |
289 | #define TEGRA210_CLK_PLL_U_48M 257 | |
290 | /* 258 */ | |
291 | #define TEGRA210_CLK_PLL_X 259 | |
292 | #define TEGRA210_CLK_PLL_X_OUT0 260 | |
293 | #define TEGRA210_CLK_PLL_RE_VCO 261 | |
294 | #define TEGRA210_CLK_PLL_RE_OUT 262 | |
295 | #define TEGRA210_CLK_PLL_E 263 | |
296 | #define TEGRA210_CLK_SPDIF_IN_SYNC 264 | |
297 | #define TEGRA210_CLK_I2S0_SYNC 265 | |
298 | #define TEGRA210_CLK_I2S1_SYNC 266 | |
299 | #define TEGRA210_CLK_I2S2_SYNC 267 | |
300 | #define TEGRA210_CLK_I2S3_SYNC 268 | |
301 | #define TEGRA210_CLK_I2S4_SYNC 269 | |
302 | #define TEGRA210_CLK_VIMCLK_SYNC 270 | |
303 | #define TEGRA210_CLK_AUDIO0 271 | |
304 | #define TEGRA210_CLK_AUDIO1 272 | |
305 | #define TEGRA210_CLK_AUDIO2 273 | |
306 | #define TEGRA210_CLK_AUDIO3 274 | |
307 | #define TEGRA210_CLK_AUDIO4 275 | |
308 | #define TEGRA210_CLK_SPDIF 276 | |
c9585405 | 309 | /* 277 */ |
88893986 | 310 | #define TEGRA210_CLK_QSPI_PM 278 |
c9585405 SK |
311 | /* 279 */ |
312 | /* 280 */ | |
05308d7e TR |
313 | #define TEGRA210_CLK_SOR0_LVDS 281 /* deprecated */ |
314 | #define TEGRA210_CLK_SOR0_OUT 281 | |
4d1dc401 | 315 | #define TEGRA210_CLK_SOR1_OUT 282 |
1d15cb9c TR |
316 | /* 283 */ |
317 | #define TEGRA210_CLK_XUSB_HOST_SRC 284 | |
318 | #define TEGRA210_CLK_XUSB_FALCON_SRC 285 | |
319 | #define TEGRA210_CLK_XUSB_FS_SRC 286 | |
320 | #define TEGRA210_CLK_XUSB_SS_SRC 287 | |
321 | ||
322 | #define TEGRA210_CLK_XUSB_DEV_SRC 288 | |
323 | #define TEGRA210_CLK_XUSB_DEV 289 | |
324 | #define TEGRA210_CLK_XUSB_HS_SRC 290 | |
325 | #define TEGRA210_CLK_SCLK 291 | |
326 | #define TEGRA210_CLK_HCLK 292 | |
327 | #define TEGRA210_CLK_PCLK 293 | |
328 | #define TEGRA210_CLK_CCLK_G 294 | |
329 | #define TEGRA210_CLK_CCLK_LP 295 | |
330 | #define TEGRA210_CLK_DFLL_REF 296 | |
331 | #define TEGRA210_CLK_DFLL_SOC 297 | |
332 | #define TEGRA210_CLK_VI_SENSOR2 298 | |
333 | #define TEGRA210_CLK_PLL_P_OUT5 299 | |
334 | #define TEGRA210_CLK_CML0 300 | |
335 | #define TEGRA210_CLK_CML1 301 | |
336 | #define TEGRA210_CLK_PLL_C4 302 | |
337 | #define TEGRA210_CLK_PLL_DP 303 | |
338 | #define TEGRA210_CLK_PLL_E_MUX 304 | |
339 | #define TEGRA210_CLK_PLL_MB 305 | |
340 | #define TEGRA210_CLK_PLL_A1 306 | |
341 | #define TEGRA210_CLK_PLL_D_DSI_OUT 307 | |
342 | #define TEGRA210_CLK_PLL_C4_OUT0 308 | |
343 | #define TEGRA210_CLK_PLL_C4_OUT1 309 | |
344 | #define TEGRA210_CLK_PLL_C4_OUT2 310 | |
345 | #define TEGRA210_CLK_PLL_C4_OUT3 311 | |
346 | #define TEGRA210_CLK_PLL_U_OUT 312 | |
347 | #define TEGRA210_CLK_PLL_U_OUT1 313 | |
348 | #define TEGRA210_CLK_PLL_U_OUT2 314 | |
349 | #define TEGRA210_CLK_USB2_HSIC_TRK 315 | |
350 | #define TEGRA210_CLK_PLL_P_OUT_HSIO 316 | |
351 | #define TEGRA210_CLK_PLL_P_OUT_XUSB 317 | |
352 | #define TEGRA210_CLK_XUSB_SSP_SRC 318 | |
926655f9 | 353 | #define TEGRA210_CLK_PLL_RE_OUT1 319 |
cd4d6f35 JL |
354 | #define TEGRA210_CLK_PLL_MB_UD 320 |
355 | #define TEGRA210_CLK_PLL_P_UD 321 | |
34ac2c27 | 356 | #define TEGRA210_CLK_ISP 322 |
88da44c5 PDS |
357 | #define TEGRA210_CLK_PLL_A_OUT_ADSP 323 |
358 | #define TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP 324 | |
1d15cb9c | 359 | /* 325 */ |
e5377ab2 | 360 | #define TEGRA210_CLK_OSC 326 |
796705bc | 361 | #define TEGRA210_CLK_CSI_TPG 327 |
1d15cb9c TR |
362 | /* 328 */ |
363 | /* 329 */ | |
364 | /* 330 */ | |
365 | /* 331 */ | |
366 | /* 332 */ | |
367 | /* 333 */ | |
368 | /* 334 */ | |
369 | /* 335 */ | |
370 | /* 336 */ | |
371 | /* 337 */ | |
372 | /* 338 */ | |
373 | /* 339 */ | |
374 | /* 340 */ | |
375 | /* 341 */ | |
376 | /* 342 */ | |
377 | /* 343 */ | |
378 | /* 344 */ | |
379 | /* 345 */ | |
380 | /* 346 */ | |
381 | /* 347 */ | |
382 | /* 348 */ | |
383 | /* 349 */ | |
384 | ||
385 | #define TEGRA210_CLK_AUDIO0_MUX 350 | |
386 | #define TEGRA210_CLK_AUDIO1_MUX 351 | |
387 | #define TEGRA210_CLK_AUDIO2_MUX 352 | |
388 | #define TEGRA210_CLK_AUDIO3_MUX 353 | |
389 | #define TEGRA210_CLK_AUDIO4_MUX 354 | |
390 | #define TEGRA210_CLK_SPDIF_MUX 355 | |
c9585405 SK |
391 | /* 356 */ |
392 | /* 357 */ | |
393 | /* 358 */ | |
1d15cb9c TR |
394 | #define TEGRA210_CLK_DSIA_MUX 359 |
395 | #define TEGRA210_CLK_DSIB_MUX 360 | |
05308d7e | 396 | /* 361 */ |
1d15cb9c TR |
397 | #define TEGRA210_CLK_XUSB_SS_DIV2 362 |
398 | ||
399 | #define TEGRA210_CLK_PLL_M_UD 363 | |
400 | #define TEGRA210_CLK_PLL_C_UD 364 | |
401 | #define TEGRA210_CLK_SCLK_MUX 365 | |
402 | ||
24c3ebef PDS |
403 | #define TEGRA210_CLK_ACLK 370 |
404 | ||
319af797 PDS |
405 | #define TEGRA210_CLK_DMIC1_SYNC_CLK 388 |
406 | #define TEGRA210_CLK_DMIC1_SYNC_CLK_MUX 389 | |
407 | #define TEGRA210_CLK_DMIC2_SYNC_CLK 390 | |
408 | #define TEGRA210_CLK_DMIC2_SYNC_CLK_MUX 391 | |
409 | #define TEGRA210_CLK_DMIC3_SYNC_CLK 392 | |
410 | #define TEGRA210_CLK_DMIC3_SYNC_CLK_MUX 393 | |
411 | ||
412 | #define TEGRA210_CLK_CLK_MAX 394 | |
1d15cb9c TR |
413 | |
414 | #endif /* _DT_BINDINGS_CLOCK_TEGRA210_CAR_H */ |