[linux-block.git] / include / dt-bindings / clock / r8a7791-clock.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * Copyright 2013 Ideas On Board SPRL
 */

#ifndef __DT_BINDINGS_CLOCK_R8A7791_H__
#define __DT_BINDINGS_CLOCK_R8A7791_H__

/* CPG */
#define R8A7791_CLK_MAIN		0
#define R8A7791_CLK_PLL0		1
#define R8A7791_CLK_PLL1		2
#define R8A7791_CLK_PLL3		3
#define R8A7791_CLK_LB			4
#define R8A7791_CLK_QSPI		5
#define R8A7791_CLK_SDH			6
#define R8A7791_CLK_SD0			7
#define R8A7791_CLK_Z			8
#define R8A7791_CLK_RCAN		9
#define R8A7791_CLK_ADSP		10

/* MSTP0 */
#define R8A7791_CLK_MSIOF0		0

/* MSTP1 */
#define R8A7791_CLK_VCP0		1
#define R8A7791_CLK_VPC0		3
#define R8A7791_CLK_JPU			6
#define R8A7791_CLK_SSP1		9
#define R8A7791_CLK_TMU1		11
#define R8A7791_CLK_3DG			12
#define R8A7791_CLK_2DDMAC		15
#define R8A7791_CLK_FDP1_1		18
#define R8A7791_CLK_FDP1_0		19
#define R8A7791_CLK_TMU3		21
#define R8A7791_CLK_TMU2		22
#define R8A7791_CLK_CMT0		24
#define R8A7791_CLK_TMU0		25
#define R8A7791_CLK_VSP1_DU1		27
#define R8A7791_CLK_VSP1_DU0		28
#define R8A7791_CLK_VSP1_S		31

/* MSTP2 */
#define R8A7791_CLK_SCIFA2		2
#define R8A7791_CLK_SCIFA1		3
#define R8A7791_CLK_SCIFA0		4
#define R8A7791_CLK_MSIOF2		5
#define R8A7791_CLK_SCIFB0		6
#define R8A7791_CLK_SCIFB1		7
#define R8A7791_CLK_MSIOF1		8
#define R8A7791_CLK_SCIFB2		16
#define R8A7791_CLK_SYS_DMAC1		18
#define R8A7791_CLK_SYS_DMAC0		19

/* MSTP3 */
#define R8A7791_CLK_TPU0		4
#define R8A7791_CLK_SDHI2		11
#define R8A7791_CLK_SDHI1		12
#define R8A7791_CLK_SDHI0		14
#define R8A7791_CLK_MMCIF0		15
#define R8A7791_CLK_IIC0		18
#define R8A7791_CLK_PCIEC		19
#define R8A7791_CLK_IIC1		23
#define R8A7791_CLK_SSUSB		28
#define R8A7791_CLK_CMT1		29
#define R8A7791_CLK_USBDMAC0		30
#define R8A7791_CLK_USBDMAC1		31

/* MSTP4 */
#define R8A7791_CLK_IRQC		7
#define R8A7791_CLK_INTC_SYS		8

/* MSTP5 */
#define R8A7791_CLK_AUDIO_DMAC1		1
#define R8A7791_CLK_AUDIO_DMAC0		2
#define R8A7791_CLK_ADSP_MOD		6
#define R8A7791_CLK_THERMAL		22
#define R8A7791_CLK_PWM			23

/* MSTP7 */
#define R8A7791_CLK_EHCI		3
#define R8A7791_CLK_HSUSB		4
#define R8A7791_CLK_HSCIF2		13
#define R8A7791_CLK_SCIF5		14
#define R8A7791_CLK_SCIF4		15
#define R8A7791_CLK_HSCIF1		16
#define R8A7791_CLK_HSCIF0		17
#define R8A7791_CLK_SCIF3		18
#define R8A7791_CLK_SCIF2		19
#define R8A7791_CLK_SCIF1		20
#define R8A7791_CLK_SCIF0		21
#define R8A7791_CLK_DU1			23
#define R8A7791_CLK_DU0			24
#define R8A7791_CLK_LVDS0		26

/* MSTP8 */
#define R8A7791_CLK_IPMMU_SGX		0
#define R8A7791_CLK_MLB			2
#define R8A7791_CLK_VIN2		9
#define R8A7791_CLK_VIN1		10
#define R8A7791_CLK_VIN0		11
#define R8A7791_CLK_ETHERAVB		12
#define R8A7791_CLK_ETHER		13
#define R8A7791_CLK_SATA1		14
#define R8A7791_CLK_SATA0		15

/* MSTP9 */
#define R8A7791_CLK_GYROADC		1
#define R8A7791_CLK_GPIO7		4
#define R8A7791_CLK_GPIO6		5
#define R8A7791_CLK_GPIO5		7
#define R8A7791_CLK_GPIO4		8
#define R8A7791_CLK_GPIO3		9
#define R8A7791_CLK_GPIO2		10
#define R8A7791_CLK_GPIO1		11
#define R8A7791_CLK_GPIO0		12
#define R8A7791_CLK_RCAN1		15
#define R8A7791_CLK_RCAN0		16
#define R8A7791_CLK_QSPI_MOD		17
#define R8A7791_CLK_I2C5		25
#define R8A7791_CLK_IICDVFS		26
#define R8A7791_CLK_I2C4		27
#define R8A7791_CLK_I2C3		28
#define R8A7791_CLK_I2C2		29
#define R8A7791_CLK_I2C1		30
#define R8A7791_CLK_I2C0		31

/* MSTP10 */
#define R8A7791_CLK_SSI_ALL		5
#define R8A7791_CLK_SSI9		6
#define R8A7791_CLK_SSI8		7
#define R8A7791_CLK_SSI7		8
#define R8A7791_CLK_SSI6		9
#define R8A7791_CLK_SSI5		10
#define R8A7791_CLK_SSI4		11
#define R8A7791_CLK_SSI3		12
#define R8A7791_CLK_SSI2		13
#define R8A7791_CLK_SSI1		14
#define R8A7791_CLK_SSI0		15
#define R8A7791_CLK_SCU_ALL		17
#define R8A7791_CLK_SCU_DVC1		18
#define R8A7791_CLK_SCU_DVC0		19
#define R8A7791_CLK_SCU_CTU1_MIX1	20
#define R8A7791_CLK_SCU_CTU0_MIX0	21
#define R8A7791_CLK_SCU_SRC9		22
#define R8A7791_CLK_SCU_SRC8		23
#define R8A7791_CLK_SCU_SRC7		24
#define R8A7791_CLK_SCU_SRC6		25
#define R8A7791_CLK_SCU_SRC5		26
#define R8A7791_CLK_SCU_SRC4		27
#define R8A7791_CLK_SCU_SRC3		28
#define R8A7791_CLK_SCU_SRC2		29
#define R8A7791_CLK_SCU_SRC1		30
#define R8A7791_CLK_SCU_SRC0		31

/* MSTP11 */
#define R8A7791_CLK_SCIFA3		6
#define R8A7791_CLK_SCIFA4		7
#define R8A7791_CLK_SCIFA5		8

#endif /* __DT_BINDINGS_CLOCK_R8A7791_H__ */
Commit	Line	Data
2874c5fd	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
4d8864c9 LP	2	/*
4d8864c9 LP	3	* Copyright 2013 Ideas On Board SPRL
4d8864c9 LP	4	*/
	5
	6	#ifndef __DT_BINDINGS_CLOCK_R8A7791_H__
	7	#define __DT_BINDINGS_CLOCK_R8A7791_H__
	8
	9	/* CPG */
	10	#define R8A7791_CLK_MAIN 0
	11	#define R8A7791_CLK_PLL0 1
	12	#define R8A7791_CLK_PLL1 2
	13	#define R8A7791_CLK_PLL3 3
	14	#define R8A7791_CLK_LB 4
	15	#define R8A7791_CLK_QSPI 5
	16	#define R8A7791_CLK_SDH 6
	17	#define R8A7791_CLK_SD0 7
	18	#define R8A7791_CLK_Z 8
b324252c	19	#define R8A7791_CLK_RCAN 9
ae65a8ae	20	#define R8A7791_CLK_ADSP 10
4d8864c9	21
cded80f8 LP	22	/* MSTP0 */
	23	#define R8A7791_CLK_MSIOF0 0
	24
4d8864c9	25	/* MSTP1 */
74d89d25 YH	26	#define R8A7791_CLK_VCP0 1
	27	#define R8A7791_CLK_VPC0 3
	28	#define R8A7791_CLK_JPU 6
	29	#define R8A7791_CLK_SSP1 9
4d8864c9	30	#define R8A7791_CLK_TMU1 11
e4d2fd9e	31	#define R8A7791_CLK_3DG 12
74d89d25 YH	32	#define R8A7791_CLK_2DDMAC 15
	33	#define R8A7791_CLK_FDP1_1 18
	34	#define R8A7791_CLK_FDP1_0 19
4d8864c9 LP	35	#define R8A7791_CLK_TMU3 21
	36	#define R8A7791_CLK_TMU2 22
	37	#define R8A7791_CLK_CMT0 24
	38	#define R8A7791_CLK_TMU0 25
	39	#define R8A7791_CLK_VSP1_DU1 27
	40	#define R8A7791_CLK_VSP1_DU0 28
58ea1d53	41	#define R8A7791_CLK_VSP1_S 31
4d8864c9 LP	42
	43	/* MSTP2 */
	44	#define R8A7791_CLK_SCIFA2 2
	45	#define R8A7791_CLK_SCIFA1 3
	46	#define R8A7791_CLK_SCIFA0 4
cded80f8	47	#define R8A7791_CLK_MSIOF2 5
4d8864c9 LP	48	#define R8A7791_CLK_SCIFB0 6
4d8864c9 LP	49	#define R8A7791_CLK_SCIFB1 7
cded80f8	50	#define R8A7791_CLK_MSIOF1 8
4d8864c9	51	#define R8A7791_CLK_SCIFB2 16
a505daa5 GU	52	#define R8A7791_CLK_SYS_DMAC1 18
a505daa5 GU	53	#define R8A7791_CLK_SYS_DMAC0 19
4d8864c9 LP	54
	55	/* MSTP3 */
	56	#define R8A7791_CLK_TPU0 4
	57	#define R8A7791_CLK_SDHI2 11
	58	#define R8A7791_CLK_SDHI1 12
	59	#define R8A7791_CLK_SDHI0 14
	60	#define R8A7791_CLK_MMCIF0 15
c6e8f325	61	#define R8A7791_CLK_IIC0 18
4bfb3767	62	#define R8A7791_CLK_PCIEC 19
c6e8f325	63	#define R8A7791_CLK_IIC1 23
4d8864c9 LP	64	#define R8A7791_CLK_SSUSB 28
	65	#define R8A7791_CLK_CMT1 29
	66	#define R8A7791_CLK_USBDMAC0 30
	67	#define R8A7791_CLK_USBDMAC1 31
	68
62d386c0 GU	69	/* MSTP4 */
62d386c0 GU	70	#define R8A7791_CLK_IRQC 7
c2f2e266	71	#define R8A7791_CLK_INTC_SYS 8
62d386c0	72
4d8864c9	73	/* MSTP5 */
8994fff6 KM	74	#define R8A7791_CLK_AUDIO_DMAC1 1
8994fff6 KM	75	#define R8A7791_CLK_AUDIO_DMAC0 2
ae65a8ae	76	#define R8A7791_CLK_ADSP_MOD 6
4d8864c9 LP	77	#define R8A7791_CLK_THERMAL 22
	78	#define R8A7791_CLK_PWM 23
	79
	80	/* MSTP7 */
6225b99a	81	#define R8A7791_CLK_EHCI 3
4d8864c9 LP	82	#define R8A7791_CLK_HSUSB 4
	83	#define R8A7791_CLK_HSCIF2 13
	84	#define R8A7791_CLK_SCIF5 14
	85	#define R8A7791_CLK_SCIF4 15
	86	#define R8A7791_CLK_HSCIF1 16
	87	#define R8A7791_CLK_HSCIF0 17
	88	#define R8A7791_CLK_SCIF3 18
	89	#define R8A7791_CLK_SCIF2 19
	90	#define R8A7791_CLK_SCIF1 20
	91	#define R8A7791_CLK_SCIF0 21
	92	#define R8A7791_CLK_DU1 23
	93	#define R8A7791_CLK_DU0 24
	94	#define R8A7791_CLK_LVDS0 26
	95
	96	/* MSTP8 */
ce85ad47	97	#define R8A7791_CLK_IPMMU_SGX 0
7408d306	98	#define R8A7791_CLK_MLB 2
4d8864c9 LP	99	#define R8A7791_CLK_VIN2 9
	100	#define R8A7791_CLK_VIN1 10
	101	#define R8A7791_CLK_VIN0 11
eaa870b3	102	#define R8A7791_CLK_ETHERAVB 12
4d8864c9 LP	103	#define R8A7791_CLK_ETHER 13
	104	#define R8A7791_CLK_SATA1 14
	105	#define R8A7791_CLK_SATA0 15
	106
	107	/* MSTP9 */
a56a2fe7	108	#define R8A7791_CLK_GYROADC 1
4d8864c9 LP	109	#define R8A7791_CLK_GPIO7 4
	110	#define R8A7791_CLK_GPIO6 5
	111	#define R8A7791_CLK_GPIO5 7
	112	#define R8A7791_CLK_GPIO4 8
	113	#define R8A7791_CLK_GPIO3 9
	114	#define R8A7791_CLK_GPIO2 10
	115	#define R8A7791_CLK_GPIO1 11
	116	#define R8A7791_CLK_GPIO0 12
	117	#define R8A7791_CLK_RCAN1 15
	118	#define R8A7791_CLK_RCAN0 16
ec71f552	119	#define R8A7791_CLK_QSPI_MOD 17
4d8864c9 LP	120	#define R8A7791_CLK_I2C5 25
	121	#define R8A7791_CLK_IICDVFS 26
	122	#define R8A7791_CLK_I2C4 27
	123	#define R8A7791_CLK_I2C3 28
	124	#define R8A7791_CLK_I2C2 29
	125	#define R8A7791_CLK_I2C1 30
	126	#define R8A7791_CLK_I2C0 31
	127
ee914152 KM	128	/* MSTP10 */
	129	#define R8A7791_CLK_SSI_ALL 5
	130	#define R8A7791_CLK_SSI9 6
	131	#define R8A7791_CLK_SSI8 7
	132	#define R8A7791_CLK_SSI7 8
	133	#define R8A7791_CLK_SSI6 9
	134	#define R8A7791_CLK_SSI5 10
	135	#define R8A7791_CLK_SSI4 11
	136	#define R8A7791_CLK_SSI3 12
	137	#define R8A7791_CLK_SSI2 13
	138	#define R8A7791_CLK_SSI1 14
	139	#define R8A7791_CLK_SSI0 15
	140	#define R8A7791_CLK_SCU_ALL 17
	141	#define R8A7791_CLK_SCU_DVC1 18
	142	#define R8A7791_CLK_SCU_DVC0 19
88401702 KM	143	#define R8A7791_CLK_SCU_CTU1_MIX1 20
88401702 KM	144	#define R8A7791_CLK_SCU_CTU0_MIX0 21
ee914152 KM	145	#define R8A7791_CLK_SCU_SRC9 22
	146	#define R8A7791_CLK_SCU_SRC8 23
	147	#define R8A7791_CLK_SCU_SRC7 24
	148	#define R8A7791_CLK_SCU_SRC6 25
	149	#define R8A7791_CLK_SCU_SRC5 26
	150	#define R8A7791_CLK_SCU_SRC4 27
	151	#define R8A7791_CLK_SCU_SRC3 28
	152	#define R8A7791_CLK_SCU_SRC2 29
	153	#define R8A7791_CLK_SCU_SRC1 30
	154	#define R8A7791_CLK_SCU_SRC0 31
	155
4d8864c9 LP	156	/* MSTP11 */
	157	#define R8A7791_CLK_SCIFA3 6
	158	#define R8A7791_CLK_SCIFA4 7
	159	#define R8A7791_CLK_SCIFA5 8
	160
	161	#endif /* __DT_BINDINGS_CLOCK_R8A7791_H__ */