[linux-block.git] / include / dt-bindings / clock / r8a7790-clock.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * Copyright 2013 Ideas On Board SPRL
 */

#ifndef __DT_BINDINGS_CLOCK_R8A7790_H__
#define __DT_BINDINGS_CLOCK_R8A7790_H__

/* CPG */
#define R8A7790_CLK_MAIN		0
#define R8A7790_CLK_PLL0		1
#define R8A7790_CLK_PLL1		2
#define R8A7790_CLK_PLL3		3
#define R8A7790_CLK_LB			4
#define R8A7790_CLK_QSPI		5
#define R8A7790_CLK_SDH			6
#define R8A7790_CLK_SD0			7
#define R8A7790_CLK_SD1			8
#define R8A7790_CLK_Z			9
#define R8A7790_CLK_RCAN		10
#define R8A7790_CLK_ADSP		11

/* MSTP0 */
#define R8A7790_CLK_MSIOF0		0

/* MSTP1 */
#define R8A7790_CLK_VCP1		0
#define R8A7790_CLK_VCP0		1
#define R8A7790_CLK_VPC1		2
#define R8A7790_CLK_VPC0		3
#define R8A7790_CLK_JPU			6
#define R8A7790_CLK_SSP1		9
#define R8A7790_CLK_TMU1		11
#define R8A7790_CLK_3DG			12
#define R8A7790_CLK_2DDMAC		15
#define R8A7790_CLK_FDP1_2		17
#define R8A7790_CLK_FDP1_1		18
#define R8A7790_CLK_FDP1_0		19
#define R8A7790_CLK_TMU3		21
#define R8A7790_CLK_TMU2		22
#define R8A7790_CLK_CMT0		24
#define R8A7790_CLK_TMU0		25
#define R8A7790_CLK_VSP1_DU1		27
#define R8A7790_CLK_VSP1_DU0		28
#define R8A7790_CLK_VSP1_R		30
#define R8A7790_CLK_VSP1_S		31

/* MSTP2 */
#define R8A7790_CLK_SCIFA2		2
#define R8A7790_CLK_SCIFA1		3
#define R8A7790_CLK_SCIFA0		4
#define R8A7790_CLK_MSIOF2		5
#define R8A7790_CLK_SCIFB0		6
#define R8A7790_CLK_SCIFB1		7
#define R8A7790_CLK_MSIOF1		8
#define R8A7790_CLK_MSIOF3		15
#define R8A7790_CLK_SCIFB2		16
#define R8A7790_CLK_SYS_DMAC1		18
#define R8A7790_CLK_SYS_DMAC0		19

/* MSTP3 */
#define R8A7790_CLK_IIC2		0
#define R8A7790_CLK_TPU0		4
#define R8A7790_CLK_MMCIF1		5
#define R8A7790_CLK_SCIF2		10
#define R8A7790_CLK_SDHI3		11
#define R8A7790_CLK_SDHI2		12
#define R8A7790_CLK_SDHI1		13
#define R8A7790_CLK_SDHI0		14
#define R8A7790_CLK_MMCIF0		15
#define R8A7790_CLK_IIC0		18
#define R8A7790_CLK_PCIEC		19
#define R8A7790_CLK_IIC1		23
#define R8A7790_CLK_SSUSB		28
#define R8A7790_CLK_CMT1		29
#define R8A7790_CLK_USBDMAC0		30
#define R8A7790_CLK_USBDMAC1		31

/* MSTP4 */
#define R8A7790_CLK_IRQC		7
#define R8A7790_CLK_INTC_SYS		8

/* MSTP5 */
#define R8A7790_CLK_AUDIO_DMAC1		1
#define R8A7790_CLK_AUDIO_DMAC0		2
#define R8A7790_CLK_ADSP_MOD		6
#define R8A7790_CLK_THERMAL		22
#define R8A7790_CLK_PWM			23

/* MSTP7 */
#define R8A7790_CLK_EHCI		3
#define R8A7790_CLK_HSUSB		4
#define R8A7790_CLK_HSCIF1		16
#define R8A7790_CLK_HSCIF0		17
#define R8A7790_CLK_SCIF1		20
#define R8A7790_CLK_SCIF0		21
#define R8A7790_CLK_DU2			22
#define R8A7790_CLK_DU1			23
#define R8A7790_CLK_DU0			24
#define R8A7790_CLK_LVDS1		25
#define R8A7790_CLK_LVDS0		26

/* MSTP8 */
#define R8A7790_CLK_MLB			2
#define R8A7790_CLK_VIN3		8
#define R8A7790_CLK_VIN2		9
#define R8A7790_CLK_VIN1		10
#define R8A7790_CLK_VIN0		11
#define R8A7790_CLK_ETHERAVB		12
#define R8A7790_CLK_ETHER		13
#define R8A7790_CLK_SATA1		14
#define R8A7790_CLK_SATA0		15

/* MSTP9 */
#define R8A7790_CLK_GPIO5		7
#define R8A7790_CLK_GPIO4		8
#define R8A7790_CLK_GPIO3		9
#define R8A7790_CLK_GPIO2		10
#define R8A7790_CLK_GPIO1		11
#define R8A7790_CLK_GPIO0		12
#define R8A7790_CLK_RCAN1		15
#define R8A7790_CLK_RCAN0		16
#define R8A7790_CLK_QSPI_MOD		17
#define R8A7790_CLK_IICDVFS		26
#define R8A7790_CLK_I2C3		28
#define R8A7790_CLK_I2C2		29
#define R8A7790_CLK_I2C1		30
#define R8A7790_CLK_I2C0		31

/* MSTP10 */
#define R8A7790_CLK_SSI_ALL		5
#define R8A7790_CLK_SSI9		6
#define R8A7790_CLK_SSI8		7
#define R8A7790_CLK_SSI7		8
#define R8A7790_CLK_SSI6		9
#define R8A7790_CLK_SSI5		10
#define R8A7790_CLK_SSI4		11
#define R8A7790_CLK_SSI3		12
#define R8A7790_CLK_SSI2		13
#define R8A7790_CLK_SSI1		14
#define R8A7790_CLK_SSI0		15
#define R8A7790_CLK_SCU_ALL		17
#define R8A7790_CLK_SCU_DVC1		18
#define R8A7790_CLK_SCU_DVC0		19
#define R8A7790_CLK_SCU_CTU1_MIX1	20
#define R8A7790_CLK_SCU_CTU0_MIX0	21
#define R8A7790_CLK_SCU_SRC9		22
#define R8A7790_CLK_SCU_SRC8		23
#define R8A7790_CLK_SCU_SRC7		24
#define R8A7790_CLK_SCU_SRC6		25
#define R8A7790_CLK_SCU_SRC5		26
#define R8A7790_CLK_SCU_SRC4		27
#define R8A7790_CLK_SCU_SRC3		28
#define R8A7790_CLK_SCU_SRC2		29
#define R8A7790_CLK_SCU_SRC1		30
#define R8A7790_CLK_SCU_SRC0		31

#endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */
Commit	Line	Data
2874c5fd	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
ac991dce LP	2	/*
ac991dce LP	3	* Copyright 2013 Ideas On Board SPRL
ac991dce LP	4	*/
	5
	6	#ifndef __DT_BINDINGS_CLOCK_R8A7790_H__
	7	#define __DT_BINDINGS_CLOCK_R8A7790_H__
	8
	9	/* CPG */
	10	#define R8A7790_CLK_MAIN 0
	11	#define R8A7790_CLK_PLL0 1
	12	#define R8A7790_CLK_PLL1 2
	13	#define R8A7790_CLK_PLL3 3
	14	#define R8A7790_CLK_LB 4
	15	#define R8A7790_CLK_QSPI 5
	16	#define R8A7790_CLK_SDH 6
	17	#define R8A7790_CLK_SD0 7
	18	#define R8A7790_CLK_SD1 8
	19	#define R8A7790_CLK_Z 9
41650f40	20	#define R8A7790_CLK_RCAN 10
3453ca9e	21	#define R8A7790_CLK_ADSP 11
ac991dce	22
9d90951a LP	23	/* MSTP0 */
	24	#define R8A7790_CLK_MSIOF0 0
	25
ac991dce	26	/* MSTP1 */
4ba8f246 YH	27	#define R8A7790_CLK_VCP1 0
	28	#define R8A7790_CLK_VCP0 1
	29	#define R8A7790_CLK_VPC1 2
	30	#define R8A7790_CLK_VPC0 3
	31	#define R8A7790_CLK_JPU 6
	32	#define R8A7790_CLK_SSP1 9
ac991dce	33	#define R8A7790_CLK_TMU1 11
2284ff5f	34	#define R8A7790_CLK_3DG 12
4ba8f246 YH	35	#define R8A7790_CLK_2DDMAC 15
	36	#define R8A7790_CLK_FDP1_2 17
	37	#define R8A7790_CLK_FDP1_1 18
	38	#define R8A7790_CLK_FDP1_0 19
ac991dce LP	39	#define R8A7790_CLK_TMU3 21
	40	#define R8A7790_CLK_TMU2 22
	41	#define R8A7790_CLK_CMT0 24
	42	#define R8A7790_CLK_TMU0 25
	43	#define R8A7790_CLK_VSP1_DU1 27
	44	#define R8A7790_CLK_VSP1_DU0 28
79ea9934 LP	45	#define R8A7790_CLK_VSP1_R 30
79ea9934 LP	46	#define R8A7790_CLK_VSP1_S 31
ac991dce LP	47
	48	/* MSTP2 */
	49	#define R8A7790_CLK_SCIFA2 2
	50	#define R8A7790_CLK_SCIFA1 3
	51	#define R8A7790_CLK_SCIFA0 4
9d90951a	52	#define R8A7790_CLK_MSIOF2 5
ac991dce LP	53	#define R8A7790_CLK_SCIFB0 6
ac991dce LP	54	#define R8A7790_CLK_SCIFB1 7
9d90951a LP	55	#define R8A7790_CLK_MSIOF1 8
9d90951a LP	56	#define R8A7790_CLK_MSIOF3 15
ac991dce	57	#define R8A7790_CLK_SCIFB2 16
b998da05 SH	58	#define R8A7790_CLK_SYS_DMAC1 18
b998da05 SH	59	#define R8A7790_CLK_SYS_DMAC0 19
ac991dce LP	60
ac991dce LP	61	/* MSTP3 */
01d968e9	62	#define R8A7790_CLK_IIC2 0
ac991dce LP	63	#define R8A7790_CLK_TPU0 4
ac991dce LP	64	#define R8A7790_CLK_MMCIF1 5
38805823	65	#define R8A7790_CLK_SCIF2 10
ac991dce LP	66	#define R8A7790_CLK_SDHI3 11
	67	#define R8A7790_CLK_SDHI2 12
	68	#define R8A7790_CLK_SDHI1 13
	69	#define R8A7790_CLK_SDHI0 14
	70	#define R8A7790_CLK_MMCIF0 15
01d968e9	71	#define R8A7790_CLK_IIC0 18
ecafea8c	72	#define R8A7790_CLK_PCIEC 19
01d968e9	73	#define R8A7790_CLK_IIC1 23
ac991dce LP	74	#define R8A7790_CLK_SSUSB 28
	75	#define R8A7790_CLK_CMT1 29
	76	#define R8A7790_CLK_USBDMAC0 30
	77	#define R8A7790_CLK_USBDMAC1 31
	78
61624caf GU	79	/* MSTP4 */
61624caf GU	80	#define R8A7790_CLK_IRQC 7
9e585236	81	#define R8A7790_CLK_INTC_SYS 8
61624caf	82
ac991dce	83	/* MSTP5 */
ba3240be KM	84	#define R8A7790_CLK_AUDIO_DMAC1 1
ba3240be KM	85	#define R8A7790_CLK_AUDIO_DMAC0 2
3453ca9e	86	#define R8A7790_CLK_ADSP_MOD 6
ac991dce LP	87	#define R8A7790_CLK_THERMAL 22
	88	#define R8A7790_CLK_PWM 23
	89
	90	/* MSTP7 */
	91	#define R8A7790_CLK_EHCI 3
	92	#define R8A7790_CLK_HSUSB 4
	93	#define R8A7790_CLK_HSCIF1 16
	94	#define R8A7790_CLK_HSCIF0 17
	95	#define R8A7790_CLK_SCIF1 20
	96	#define R8A7790_CLK_SCIF0 21
	97	#define R8A7790_CLK_DU2 22
	98	#define R8A7790_CLK_DU1 23
	99	#define R8A7790_CLK_DU0 24
	100	#define R8A7790_CLK_LVDS1 25
	101	#define R8A7790_CLK_LVDS0 26
	102
	103	/* MSTP8 */
f6b5dd40	104	#define R8A7790_CLK_MLB 2
ac991dce LP	105	#define R8A7790_CLK_VIN3 8
	106	#define R8A7790_CLK_VIN2 9
	107	#define R8A7790_CLK_VIN1 10
	108	#define R8A7790_CLK_VIN0 11
63d2d750	109	#define R8A7790_CLK_ETHERAVB 12
ac991dce LP	110	#define R8A7790_CLK_ETHER 13
	111	#define R8A7790_CLK_SATA1 14
	112	#define R8A7790_CLK_SATA0 15
	113
	114	/* MSTP9 */
	115	#define R8A7790_CLK_GPIO5 7
	116	#define R8A7790_CLK_GPIO4 8
	117	#define R8A7790_CLK_GPIO3 9
	118	#define R8A7790_CLK_GPIO2 10
	119	#define R8A7790_CLK_GPIO1 11
	120	#define R8A7790_CLK_GPIO0 12
	121	#define R8A7790_CLK_RCAN1 15
	122	#define R8A7790_CLK_RCAN0 16
91b56ca1	123	#define R8A7790_CLK_QSPI_MOD 17
ac991dce LP	124	#define R8A7790_CLK_IICDVFS 26
	125	#define R8A7790_CLK_I2C3 28
	126	#define R8A7790_CLK_I2C2 29
	127	#define R8A7790_CLK_I2C1 30
	128	#define R8A7790_CLK_I2C0 31
	129
bcde3722 KM	130	/* MSTP10 */
	131	#define R8A7790_CLK_SSI_ALL 5
	132	#define R8A7790_CLK_SSI9 6
	133	#define R8A7790_CLK_SSI8 7
	134	#define R8A7790_CLK_SSI7 8
	135	#define R8A7790_CLK_SSI6 9
	136	#define R8A7790_CLK_SSI5 10
	137	#define R8A7790_CLK_SSI4 11
	138	#define R8A7790_CLK_SSI3 12
	139	#define R8A7790_CLK_SSI2 13
	140	#define R8A7790_CLK_SSI1 14
	141	#define R8A7790_CLK_SSI0 15
	142	#define R8A7790_CLK_SCU_ALL 17
	143	#define R8A7790_CLK_SCU_DVC1 18
	144	#define R8A7790_CLK_SCU_DVC0 19
a7163784 KM	145	#define R8A7790_CLK_SCU_CTU1_MIX1 20
a7163784 KM	146	#define R8A7790_CLK_SCU_CTU0_MIX0 21
bcde3722 KM	147	#define R8A7790_CLK_SCU_SRC9 22
	148	#define R8A7790_CLK_SCU_SRC8 23
	149	#define R8A7790_CLK_SCU_SRC7 24
	150	#define R8A7790_CLK_SCU_SRC6 25
	151	#define R8A7790_CLK_SCU_SRC5 26
	152	#define R8A7790_CLK_SCU_SRC4 27
	153	#define R8A7790_CLK_SCU_SRC3 28
	154	#define R8A7790_CLK_SCU_SRC2 29
	155	#define R8A7790_CLK_SCU_SRC1 30
	156	#define R8A7790_CLK_SCU_SRC0 31
	157
ac991dce	158	#endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */