[linux-block.git] / include / dt-bindings / clock / qcom,lpassaudiocc-sc7280.h

/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
 * Copyright (c) 2021, The Linux Foundation. All rights reserved.
 */

#ifndef _DT_BINDINGS_CLK_QCOM_LPASS_AUDIO_CC_SC7280_H
#define _DT_BINDINGS_CLK_QCOM_LPASS_AUDIO_CC_SC7280_H

/* LPASS_AUDIO_CC clocks */
#define LPASS_AUDIO_CC_PLL				0
#define LPASS_AUDIO_CC_PLL_OUT_AUX2			1
#define LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC		2
#define LPASS_AUDIO_CC_PLL_OUT_MAIN_DIV_CLK_SRC		3
#define LPASS_AUDIO_CC_CDIV_RX_MCLK_DIV_CLK_SRC		4
#define LPASS_AUDIO_CC_CODEC_MEM0_CLK			5
#define LPASS_AUDIO_CC_CODEC_MEM1_CLK			6
#define LPASS_AUDIO_CC_CODEC_MEM2_CLK			7
#define LPASS_AUDIO_CC_CODEC_MEM_CLK			8
#define LPASS_AUDIO_CC_EXT_MCLK0_CLK			9
#define LPASS_AUDIO_CC_EXT_MCLK0_CLK_SRC		10
#define LPASS_AUDIO_CC_EXT_MCLK1_CLK			11
#define LPASS_AUDIO_CC_EXT_MCLK1_CLK_SRC		12
#define LPASS_AUDIO_CC_RX_MCLK_2X_CLK			13
#define LPASS_AUDIO_CC_RX_MCLK_CLK			14
#define LPASS_AUDIO_CC_RX_MCLK_CLK_SRC			15

/* LPASS_AON_CC clocks */
#define LPASS_AON_CC_PLL				0
#define LPASS_AON_CC_PLL_OUT_EVEN			1
#define LPASS_AON_CC_PLL_OUT_MAIN_CDIV_DIV_CLK_SRC	2
#define LPASS_AON_CC_PLL_OUT_ODD			3
#define LPASS_AON_CC_AUDIO_HM_H_CLK			4
#define LPASS_AON_CC_CDIV_TX_MCLK_DIV_CLK_SRC		5
#define LPASS_AON_CC_MAIN_RCG_CLK_SRC			6
#define LPASS_AON_CC_TX_MCLK_2X_CLK			7
#define LPASS_AON_CC_TX_MCLK_CLK			8
#define LPASS_AON_CC_TX_MCLK_RCG_CLK_SRC		9
#define LPASS_AON_CC_VA_MEM0_CLK			10

/* LPASS_AON_CC power domains */
#define LPASS_AON_CC_LPASS_AUDIO_HM_GDSC		0

#endif
Commit	Line	Data
4185b27b TD	1	/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
	2	/*
	3	* Copyright (c) 2021, The Linux Foundation. All rights reserved.
	4	*/
	5
	6	#ifndef _DT_BINDINGS_CLK_QCOM_LPASS_AUDIO_CC_SC7280_H
	7	#define _DT_BINDINGS_CLK_QCOM_LPASS_AUDIO_CC_SC7280_H
	8
	9	/* LPASS_AUDIO_CC clocks */
	10	#define LPASS_AUDIO_CC_PLL 0
	11	#define LPASS_AUDIO_CC_PLL_OUT_AUX2 1
	12	#define LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC 2
	13	#define LPASS_AUDIO_CC_PLL_OUT_MAIN_DIV_CLK_SRC 3
	14	#define LPASS_AUDIO_CC_CDIV_RX_MCLK_DIV_CLK_SRC 4
	15	#define LPASS_AUDIO_CC_CODEC_MEM0_CLK 5
	16	#define LPASS_AUDIO_CC_CODEC_MEM1_CLK 6
	17	#define LPASS_AUDIO_CC_CODEC_MEM2_CLK 7
	18	#define LPASS_AUDIO_CC_CODEC_MEM_CLK 8
	19	#define LPASS_AUDIO_CC_EXT_MCLK0_CLK 9
	20	#define LPASS_AUDIO_CC_EXT_MCLK0_CLK_SRC 10
	21	#define LPASS_AUDIO_CC_EXT_MCLK1_CLK 11
	22	#define LPASS_AUDIO_CC_EXT_MCLK1_CLK_SRC 12
	23	#define LPASS_AUDIO_CC_RX_MCLK_2X_CLK 13
	24	#define LPASS_AUDIO_CC_RX_MCLK_CLK 14
	25	#define LPASS_AUDIO_CC_RX_MCLK_CLK_SRC 15
	26
	27	/* LPASS_AON_CC clocks */
	28	#define LPASS_AON_CC_PLL 0
	29	#define LPASS_AON_CC_PLL_OUT_EVEN 1
	30	#define LPASS_AON_CC_PLL_OUT_MAIN_CDIV_DIV_CLK_SRC 2
	31	#define LPASS_AON_CC_PLL_OUT_ODD 3
	32	#define LPASS_AON_CC_AUDIO_HM_H_CLK 4
	33	#define LPASS_AON_CC_CDIV_TX_MCLK_DIV_CLK_SRC 5
	34	#define LPASS_AON_CC_MAIN_RCG_CLK_SRC 6
	35	#define LPASS_AON_CC_TX_MCLK_2X_CLK 7
	36	#define LPASS_AON_CC_TX_MCLK_CLK 8
	37	#define LPASS_AON_CC_TX_MCLK_RCG_CLK_SRC 9
	38	#define LPASS_AON_CC_VA_MEM0_CLK 10
	39
	40	/* LPASS_AON_CC power domains */
	41	#define LPASS_AON_CC_LPASS_AUDIO_HM_GDSC 0
	42
	43	#endif