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9c92ab61 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
02824653 GD |
2 | /* |
3 | * Copyright (c) 2014, The Linux Foundation. All rights reserved. | |
02824653 GD |
4 | */ |
5 | ||
6 | #ifndef _DT_BINDINGS_CLK_APQ_GCC_8084_H | |
7 | #define _DT_BINDINGS_CLK_APQ_GCC_8084_H | |
8 | ||
9 | #define GPLL0 0 | |
10 | #define GPLL0_VOTE 1 | |
11 | #define GPLL1 2 | |
12 | #define GPLL1_VOTE 3 | |
13 | #define GPLL2 4 | |
14 | #define GPLL2_VOTE 5 | |
15 | #define GPLL3 6 | |
16 | #define GPLL3_VOTE 7 | |
17 | #define GPLL4 8 | |
18 | #define GPLL4_VOTE 9 | |
19 | #define CONFIG_NOC_CLK_SRC 10 | |
20 | #define PERIPH_NOC_CLK_SRC 11 | |
21 | #define SYSTEM_NOC_CLK_SRC 12 | |
22 | #define BLSP_UART_SIM_CLK_SRC 13 | |
23 | #define QDSS_TSCTR_CLK_SRC 14 | |
24 | #define UFS_AXI_CLK_SRC 15 | |
25 | #define RPM_CLK_SRC 16 | |
26 | #define KPSS_AHB_CLK_SRC 17 | |
27 | #define QDSS_AT_CLK_SRC 18 | |
28 | #define BIMC_DDR_CLK_SRC 19 | |
29 | #define USB30_MASTER_CLK_SRC 20 | |
30 | #define USB30_SEC_MASTER_CLK_SRC 21 | |
31 | #define USB_HSIC_AHB_CLK_SRC 22 | |
32 | #define MMSS_BIMC_GFX_CLK_SRC 23 | |
33 | #define QDSS_STM_CLK_SRC 24 | |
34 | #define ACC_CLK_SRC 25 | |
35 | #define SEC_CTRL_CLK_SRC 26 | |
36 | #define BLSP1_QUP1_I2C_APPS_CLK_SRC 27 | |
37 | #define BLSP1_QUP1_SPI_APPS_CLK_SRC 28 | |
38 | #define BLSP1_QUP2_I2C_APPS_CLK_SRC 29 | |
39 | #define BLSP1_QUP2_SPI_APPS_CLK_SRC 30 | |
40 | #define BLSP1_QUP3_I2C_APPS_CLK_SRC 31 | |
41 | #define BLSP1_QUP3_SPI_APPS_CLK_SRC 32 | |
42 | #define BLSP1_QUP4_I2C_APPS_CLK_SRC 33 | |
43 | #define BLSP1_QUP4_SPI_APPS_CLK_SRC 34 | |
44 | #define BLSP1_QUP5_I2C_APPS_CLK_SRC 35 | |
45 | #define BLSP1_QUP5_SPI_APPS_CLK_SRC 36 | |
46 | #define BLSP1_QUP6_I2C_APPS_CLK_SRC 37 | |
47 | #define BLSP1_QUP6_SPI_APPS_CLK_SRC 38 | |
48 | #define BLSP1_UART1_APPS_CLK_SRC 39 | |
49 | #define BLSP1_UART2_APPS_CLK_SRC 40 | |
50 | #define BLSP1_UART3_APPS_CLK_SRC 41 | |
51 | #define BLSP1_UART4_APPS_CLK_SRC 42 | |
52 | #define BLSP1_UART5_APPS_CLK_SRC 43 | |
53 | #define BLSP1_UART6_APPS_CLK_SRC 44 | |
54 | #define BLSP2_QUP1_I2C_APPS_CLK_SRC 45 | |
55 | #define BLSP2_QUP1_SPI_APPS_CLK_SRC 46 | |
56 | #define BLSP2_QUP2_I2C_APPS_CLK_SRC 47 | |
57 | #define BLSP2_QUP2_SPI_APPS_CLK_SRC 48 | |
58 | #define BLSP2_QUP3_I2C_APPS_CLK_SRC 49 | |
59 | #define BLSP2_QUP3_SPI_APPS_CLK_SRC 50 | |
60 | #define BLSP2_QUP4_I2C_APPS_CLK_SRC 51 | |
61 | #define BLSP2_QUP4_SPI_APPS_CLK_SRC 52 | |
62 | #define BLSP2_QUP5_I2C_APPS_CLK_SRC 53 | |
63 | #define BLSP2_QUP5_SPI_APPS_CLK_SRC 54 | |
64 | #define BLSP2_QUP6_I2C_APPS_CLK_SRC 55 | |
65 | #define BLSP2_QUP6_SPI_APPS_CLK_SRC 56 | |
66 | #define BLSP2_UART1_APPS_CLK_SRC 57 | |
67 | #define BLSP2_UART2_APPS_CLK_SRC 58 | |
68 | #define BLSP2_UART3_APPS_CLK_SRC 59 | |
69 | #define BLSP2_UART4_APPS_CLK_SRC 60 | |
70 | #define BLSP2_UART5_APPS_CLK_SRC 61 | |
71 | #define BLSP2_UART6_APPS_CLK_SRC 62 | |
72 | #define CE1_CLK_SRC 63 | |
73 | #define CE2_CLK_SRC 64 | |
74 | #define CE3_CLK_SRC 65 | |
75 | #define GP1_CLK_SRC 66 | |
76 | #define GP2_CLK_SRC 67 | |
77 | #define GP3_CLK_SRC 68 | |
78 | #define PDM2_CLK_SRC 69 | |
79 | #define QDSS_TRACECLKIN_CLK_SRC 70 | |
80 | #define RBCPR_CLK_SRC 71 | |
81 | #define SATA_ASIC0_CLK_SRC 72 | |
82 | #define SATA_PMALIVE_CLK_SRC 73 | |
83 | #define SATA_RX_CLK_SRC 74 | |
84 | #define SATA_RX_OOB_CLK_SRC 75 | |
85 | #define SDCC1_APPS_CLK_SRC 76 | |
86 | #define SDCC2_APPS_CLK_SRC 77 | |
87 | #define SDCC3_APPS_CLK_SRC 78 | |
88 | #define SDCC4_APPS_CLK_SRC 79 | |
89 | #define GCC_SNOC_BUS_TIMEOUT0_AHB_CLK 80 | |
90 | #define SPMI_AHB_CLK_SRC 81 | |
91 | #define SPMI_SER_CLK_SRC 82 | |
92 | #define TSIF_REF_CLK_SRC 83 | |
93 | #define USB30_MOCK_UTMI_CLK_SRC 84 | |
94 | #define USB30_SEC_MOCK_UTMI_CLK_SRC 85 | |
95 | #define USB_HS_SYSTEM_CLK_SRC 86 | |
96 | #define USB_HSIC_CLK_SRC 87 | |
97 | #define USB_HSIC_IO_CAL_CLK_SRC 88 | |
98 | #define USB_HSIC_MOCK_UTMI_CLK_SRC 89 | |
99 | #define USB_HSIC_SYSTEM_CLK_SRC 90 | |
100 | #define GCC_BAM_DMA_AHB_CLK 91 | |
101 | #define GCC_BAM_DMA_INACTIVITY_TIMERS_CLK 92 | |
102 | #define DDR_CLK_SRC 93 | |
103 | #define GCC_BIMC_CFG_AHB_CLK 94 | |
104 | #define GCC_BIMC_CLK 95 | |
105 | #define GCC_BIMC_KPSS_AXI_CLK 96 | |
106 | #define GCC_BIMC_SLEEP_CLK 97 | |
107 | #define GCC_BIMC_SYSNOC_AXI_CLK 98 | |
108 | #define GCC_BIMC_XO_CLK 99 | |
109 | #define GCC_BLSP1_AHB_CLK 100 | |
110 | #define GCC_BLSP1_SLEEP_CLK 101 | |
111 | #define GCC_BLSP1_QUP1_I2C_APPS_CLK 102 | |
112 | #define GCC_BLSP1_QUP1_SPI_APPS_CLK 103 | |
113 | #define GCC_BLSP1_QUP2_I2C_APPS_CLK 104 | |
114 | #define GCC_BLSP1_QUP2_SPI_APPS_CLK 105 | |
115 | #define GCC_BLSP1_QUP3_I2C_APPS_CLK 106 | |
116 | #define GCC_BLSP1_QUP3_SPI_APPS_CLK 107 | |
117 | #define GCC_BLSP1_QUP4_I2C_APPS_CLK 108 | |
118 | #define GCC_BLSP1_QUP4_SPI_APPS_CLK 109 | |
119 | #define GCC_BLSP1_QUP5_I2C_APPS_CLK 110 | |
120 | #define GCC_BLSP1_QUP5_SPI_APPS_CLK 111 | |
121 | #define GCC_BLSP1_QUP6_I2C_APPS_CLK 112 | |
122 | #define GCC_BLSP1_QUP6_SPI_APPS_CLK 113 | |
123 | #define GCC_BLSP1_UART1_APPS_CLK 114 | |
124 | #define GCC_BLSP1_UART1_SIM_CLK 115 | |
125 | #define GCC_BLSP1_UART2_APPS_CLK 116 | |
126 | #define GCC_BLSP1_UART2_SIM_CLK 117 | |
127 | #define GCC_BLSP1_UART3_APPS_CLK 118 | |
128 | #define GCC_BLSP1_UART3_SIM_CLK 119 | |
129 | #define GCC_BLSP1_UART4_APPS_CLK 120 | |
130 | #define GCC_BLSP1_UART4_SIM_CLK 121 | |
131 | #define GCC_BLSP1_UART5_APPS_CLK 122 | |
132 | #define GCC_BLSP1_UART5_SIM_CLK 123 | |
133 | #define GCC_BLSP1_UART6_APPS_CLK 124 | |
134 | #define GCC_BLSP1_UART6_SIM_CLK 125 | |
135 | #define GCC_BLSP2_AHB_CLK 126 | |
136 | #define GCC_BLSP2_SLEEP_CLK 127 | |
137 | #define GCC_BLSP2_QUP1_I2C_APPS_CLK 128 | |
138 | #define GCC_BLSP2_QUP1_SPI_APPS_CLK 129 | |
139 | #define GCC_BLSP2_QUP2_I2C_APPS_CLK 130 | |
140 | #define GCC_BLSP2_QUP2_SPI_APPS_CLK 131 | |
141 | #define GCC_BLSP2_QUP3_I2C_APPS_CLK 132 | |
142 | #define GCC_BLSP2_QUP3_SPI_APPS_CLK 133 | |
143 | #define GCC_BLSP2_QUP4_I2C_APPS_CLK 134 | |
144 | #define GCC_BLSP2_QUP4_SPI_APPS_CLK 135 | |
145 | #define GCC_BLSP2_QUP5_I2C_APPS_CLK 136 | |
146 | #define GCC_BLSP2_QUP5_SPI_APPS_CLK 137 | |
147 | #define GCC_BLSP2_QUP6_I2C_APPS_CLK 138 | |
148 | #define GCC_BLSP2_QUP6_SPI_APPS_CLK 139 | |
149 | #define GCC_BLSP2_UART1_APPS_CLK 140 | |
150 | #define GCC_BLSP2_UART1_SIM_CLK 141 | |
151 | #define GCC_BLSP2_UART2_APPS_CLK 142 | |
152 | #define GCC_BLSP2_UART2_SIM_CLK 143 | |
153 | #define GCC_BLSP2_UART3_APPS_CLK 144 | |
154 | #define GCC_BLSP2_UART3_SIM_CLK 145 | |
155 | #define GCC_BLSP2_UART4_APPS_CLK 146 | |
156 | #define GCC_BLSP2_UART4_SIM_CLK 147 | |
157 | #define GCC_BLSP2_UART5_APPS_CLK 148 | |
158 | #define GCC_BLSP2_UART5_SIM_CLK 149 | |
159 | #define GCC_BLSP2_UART6_APPS_CLK 150 | |
160 | #define GCC_BLSP2_UART6_SIM_CLK 151 | |
161 | #define GCC_BOOT_ROM_AHB_CLK 152 | |
162 | #define GCC_CE1_AHB_CLK 153 | |
163 | #define GCC_CE1_AXI_CLK 154 | |
164 | #define GCC_CE1_CLK 155 | |
165 | #define GCC_CE2_AHB_CLK 156 | |
166 | #define GCC_CE2_AXI_CLK 157 | |
167 | #define GCC_CE2_CLK 158 | |
168 | #define GCC_CE3_AHB_CLK 159 | |
169 | #define GCC_CE3_AXI_CLK 160 | |
170 | #define GCC_CE3_CLK 161 | |
171 | #define GCC_CNOC_BUS_TIMEOUT0_AHB_CLK 162 | |
172 | #define GCC_CNOC_BUS_TIMEOUT1_AHB_CLK 163 | |
173 | #define GCC_CNOC_BUS_TIMEOUT2_AHB_CLK 164 | |
174 | #define GCC_CNOC_BUS_TIMEOUT3_AHB_CLK 165 | |
175 | #define GCC_CNOC_BUS_TIMEOUT4_AHB_CLK 166 | |
176 | #define GCC_CNOC_BUS_TIMEOUT5_AHB_CLK 167 | |
177 | #define GCC_CNOC_BUS_TIMEOUT6_AHB_CLK 168 | |
178 | #define GCC_CNOC_BUS_TIMEOUT7_AHB_CLK 169 | |
179 | #define GCC_CFG_NOC_AHB_CLK 170 | |
180 | #define GCC_CFG_NOC_DDR_CFG_CLK 171 | |
181 | #define GCC_CFG_NOC_RPM_AHB_CLK 172 | |
182 | #define GCC_COPSS_SMMU_AHB_CLK 173 | |
183 | #define GCC_COPSS_SMMU_AXI_CLK 174 | |
184 | #define GCC_DCD_XO_CLK 175 | |
185 | #define GCC_BIMC_DDR_CH0_CLK 176 | |
186 | #define GCC_BIMC_DDR_CH1_CLK 177 | |
187 | #define GCC_BIMC_DDR_CPLL0_CLK 178 | |
188 | #define GCC_BIMC_DDR_CPLL1_CLK 179 | |
189 | #define GCC_BIMC_GFX_CLK 180 | |
190 | #define GCC_DDR_DIM_CFG_CLK 181 | |
191 | #define GCC_DDR_DIM_SLEEP_CLK 182 | |
192 | #define GCC_DEHR_CLK 183 | |
193 | #define GCC_AHB_CLK 184 | |
194 | #define GCC_IM_SLEEP_CLK 185 | |
195 | #define GCC_XO_CLK 186 | |
196 | #define GCC_XO_DIV4_CLK 187 | |
197 | #define GCC_GP1_CLK 188 | |
198 | #define GCC_GP2_CLK 189 | |
199 | #define GCC_GP3_CLK 190 | |
200 | #define GCC_IMEM_AXI_CLK 191 | |
201 | #define GCC_IMEM_CFG_AHB_CLK 192 | |
202 | #define GCC_KPSS_AHB_CLK 193 | |
203 | #define GCC_KPSS_AXI_CLK 194 | |
204 | #define GCC_LPASS_MPORT_AXI_CLK 195 | |
205 | #define GCC_LPASS_Q6_AXI_CLK 196 | |
206 | #define GCC_LPASS_SWAY_CLK 197 | |
207 | #define GCC_MMSS_BIMC_GFX_CLK 198 | |
208 | #define GCC_MMSS_NOC_AT_CLK 199 | |
209 | #define GCC_MMSS_NOC_CFG_AHB_CLK 200 | |
210 | #define GCC_MMSS_VPU_MAPLE_SYS_NOC_AXI_CLK 201 | |
211 | #define GCC_OCMEM_NOC_CFG_AHB_CLK 202 | |
212 | #define GCC_OCMEM_SYS_NOC_AXI_CLK 203 | |
213 | #define GCC_MPM_AHB_CLK 204 | |
214 | #define GCC_MSG_RAM_AHB_CLK 205 | |
215 | #define GCC_NOC_CONF_XPU_AHB_CLK 206 | |
216 | #define GCC_PDM2_CLK 207 | |
217 | #define GCC_PDM_AHB_CLK 208 | |
218 | #define GCC_PDM_XO4_CLK 209 | |
219 | #define GCC_PERIPH_NOC_AHB_CLK 210 | |
220 | #define GCC_PERIPH_NOC_AT_CLK 211 | |
221 | #define GCC_PERIPH_NOC_CFG_AHB_CLK 212 | |
222 | #define GCC_PERIPH_NOC_USB_HSIC_AHB_CLK 213 | |
223 | #define GCC_PERIPH_NOC_MPU_CFG_AHB_CLK 214 | |
224 | #define GCC_PERIPH_XPU_AHB_CLK 215 | |
225 | #define GCC_PNOC_BUS_TIMEOUT0_AHB_CLK 216 | |
226 | #define GCC_PNOC_BUS_TIMEOUT1_AHB_CLK 217 | |
227 | #define GCC_PNOC_BUS_TIMEOUT2_AHB_CLK 218 | |
228 | #define GCC_PNOC_BUS_TIMEOUT3_AHB_CLK 219 | |
229 | #define GCC_PNOC_BUS_TIMEOUT4_AHB_CLK 220 | |
230 | #define GCC_PRNG_AHB_CLK 221 | |
231 | #define GCC_QDSS_AT_CLK 222 | |
232 | #define GCC_QDSS_CFG_AHB_CLK 223 | |
233 | #define GCC_QDSS_DAP_AHB_CLK 224 | |
234 | #define GCC_QDSS_DAP_CLK 225 | |
235 | #define GCC_QDSS_ETR_USB_CLK 226 | |
236 | #define GCC_QDSS_STM_CLK 227 | |
237 | #define GCC_QDSS_TRACECLKIN_CLK 228 | |
238 | #define GCC_QDSS_TSCTR_DIV16_CLK 229 | |
239 | #define GCC_QDSS_TSCTR_DIV2_CLK 230 | |
240 | #define GCC_QDSS_TSCTR_DIV3_CLK 231 | |
241 | #define GCC_QDSS_TSCTR_DIV4_CLK 232 | |
242 | #define GCC_QDSS_TSCTR_DIV8_CLK 233 | |
243 | #define GCC_QDSS_RBCPR_XPU_AHB_CLK 234 | |
244 | #define GCC_RBCPR_AHB_CLK 235 | |
245 | #define GCC_RBCPR_CLK 236 | |
246 | #define GCC_RPM_BUS_AHB_CLK 237 | |
247 | #define GCC_RPM_PROC_HCLK 238 | |
248 | #define GCC_RPM_SLEEP_CLK 239 | |
249 | #define GCC_RPM_TIMER_CLK 240 | |
250 | #define GCC_SATA_ASIC0_CLK 241 | |
251 | #define GCC_SATA_AXI_CLK 242 | |
252 | #define GCC_SATA_CFG_AHB_CLK 243 | |
253 | #define GCC_SATA_PMALIVE_CLK 244 | |
254 | #define GCC_SATA_RX_CLK 245 | |
255 | #define GCC_SATA_RX_OOB_CLK 246 | |
256 | #define GCC_SDCC1_AHB_CLK 247 | |
257 | #define GCC_SDCC1_APPS_CLK 248 | |
258 | #define GCC_SDCC1_CDCCAL_FF_CLK 249 | |
259 | #define GCC_SDCC1_CDCCAL_SLEEP_CLK 250 | |
260 | #define GCC_SDCC2_AHB_CLK 251 | |
261 | #define GCC_SDCC2_APPS_CLK 252 | |
262 | #define GCC_SDCC2_INACTIVITY_TIMERS_CLK 253 | |
263 | #define GCC_SDCC3_AHB_CLK 254 | |
264 | #define GCC_SDCC3_APPS_CLK 255 | |
265 | #define GCC_SDCC3_INACTIVITY_TIMERS_CLK 256 | |
266 | #define GCC_SDCC4_AHB_CLK 257 | |
267 | #define GCC_SDCC4_APPS_CLK 258 | |
268 | #define GCC_SDCC4_INACTIVITY_TIMERS_CLK 259 | |
269 | #define GCC_SEC_CTRL_ACC_CLK 260 | |
270 | #define GCC_SEC_CTRL_AHB_CLK 261 | |
271 | #define GCC_SEC_CTRL_BOOT_ROM_PATCH_CLK 262 | |
272 | #define GCC_SEC_CTRL_CLK 263 | |
273 | #define GCC_SEC_CTRL_SENSE_CLK 264 | |
274 | #define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK 265 | |
275 | #define GCC_SNOC_BUS_TIMEOUT3_AHB_CLK 266 | |
276 | #define GCC_SPDM_BIMC_CY_CLK 267 | |
277 | #define GCC_SPDM_CFG_AHB_CLK 268 | |
278 | #define GCC_SPDM_DEBUG_CY_CLK 269 | |
279 | #define GCC_SPDM_FF_CLK 270 | |
280 | #define GCC_SPDM_MSTR_AHB_CLK 271 | |
281 | #define GCC_SPDM_PNOC_CY_CLK 272 | |
282 | #define GCC_SPDM_RPM_CY_CLK 273 | |
283 | #define GCC_SPDM_SNOC_CY_CLK 274 | |
284 | #define GCC_SPMI_AHB_CLK 275 | |
285 | #define GCC_SPMI_CNOC_AHB_CLK 276 | |
286 | #define GCC_SPMI_SER_CLK 277 | |
287 | #define GCC_SPSS_AHB_CLK 278 | |
288 | #define GCC_SNOC_CNOC_AHB_CLK 279 | |
289 | #define GCC_SNOC_PNOC_AHB_CLK 280 | |
290 | #define GCC_SYS_NOC_AT_CLK 281 | |
291 | #define GCC_SYS_NOC_AXI_CLK 282 | |
292 | #define GCC_SYS_NOC_KPSS_AHB_CLK 283 | |
293 | #define GCC_SYS_NOC_QDSS_STM_AXI_CLK 284 | |
294 | #define GCC_SYS_NOC_UFS_AXI_CLK 285 | |
295 | #define GCC_SYS_NOC_USB3_AXI_CLK 286 | |
296 | #define GCC_SYS_NOC_USB3_SEC_AXI_CLK 287 | |
297 | #define GCC_TCSR_AHB_CLK 288 | |
298 | #define GCC_TLMM_AHB_CLK 289 | |
299 | #define GCC_TLMM_CLK 290 | |
300 | #define GCC_TSIF_AHB_CLK 291 | |
301 | #define GCC_TSIF_INACTIVITY_TIMERS_CLK 292 | |
302 | #define GCC_TSIF_REF_CLK 293 | |
303 | #define GCC_UFS_AHB_CLK 294 | |
304 | #define GCC_UFS_AXI_CLK 295 | |
305 | #define GCC_UFS_RX_CFG_CLK 296 | |
306 | #define GCC_UFS_RX_SYMBOL_0_CLK 297 | |
307 | #define GCC_UFS_RX_SYMBOL_1_CLK 298 | |
308 | #define GCC_UFS_TX_CFG_CLK 299 | |
309 | #define GCC_UFS_TX_SYMBOL_0_CLK 300 | |
310 | #define GCC_UFS_TX_SYMBOL_1_CLK 301 | |
311 | #define GCC_USB2A_PHY_SLEEP_CLK 302 | |
312 | #define GCC_USB2B_PHY_SLEEP_CLK 303 | |
313 | #define GCC_USB30_MASTER_CLK 304 | |
314 | #define GCC_USB30_MOCK_UTMI_CLK 305 | |
315 | #define GCC_USB30_SLEEP_CLK 306 | |
316 | #define GCC_USB30_SEC_MASTER_CLK 307 | |
317 | #define GCC_USB30_SEC_MOCK_UTMI_CLK 308 | |
318 | #define GCC_USB30_SEC_SLEEP_CLK 309 | |
319 | #define GCC_USB_HS_AHB_CLK 310 | |
320 | #define GCC_USB_HS_INACTIVITY_TIMERS_CLK 311 | |
321 | #define GCC_USB_HS_SYSTEM_CLK 312 | |
322 | #define GCC_USB_HSIC_AHB_CLK 313 | |
323 | #define GCC_USB_HSIC_CLK 314 | |
324 | #define GCC_USB_HSIC_IO_CAL_CLK 315 | |
325 | #define GCC_USB_HSIC_IO_CAL_SLEEP_CLK 316 | |
326 | #define GCC_USB_HSIC_MOCK_UTMI_CLK 317 | |
327 | #define GCC_USB_HSIC_SYSTEM_CLK 318 | |
5424e102 GD |
328 | #define PCIE_0_AUX_CLK_SRC 319 |
329 | #define PCIE_0_PIPE_CLK_SRC 320 | |
330 | #define PCIE_1_AUX_CLK_SRC 321 | |
331 | #define PCIE_1_PIPE_CLK_SRC 322 | |
332 | #define GCC_PCIE_0_AUX_CLK 323 | |
333 | #define GCC_PCIE_0_CFG_AHB_CLK 324 | |
334 | #define GCC_PCIE_0_MSTR_AXI_CLK 325 | |
335 | #define GCC_PCIE_0_PIPE_CLK 326 | |
336 | #define GCC_PCIE_0_SLV_AXI_CLK 327 | |
337 | #define GCC_PCIE_1_AUX_CLK 328 | |
338 | #define GCC_PCIE_1_CFG_AHB_CLK 329 | |
339 | #define GCC_PCIE_1_MSTR_AXI_CLK 330 | |
340 | #define GCC_PCIE_1_PIPE_CLK 331 | |
341 | #define GCC_PCIE_1_SLV_AXI_CLK 332 | |
02824653 | 342 | |
639af949 RN |
343 | /* gdscs */ |
344 | #define USB_HS_HSIC_GDSC 0 | |
345 | #define PCIE0_GDSC 1 | |
346 | #define PCIE1_GDSC 2 | |
347 | #define USB30_GDSC 3 | |
348 | ||
02824653 | 349 | #endif |