Commit | Line | Data |
---|---|---|
b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
1ec770d9 CX |
2 | #ifndef __DTS_MARVELL_MMP2_CLOCK_H |
3 | #define __DTS_MARVELL_MMP2_CLOCK_H | |
4 | ||
5 | /* fixed clocks and plls */ | |
6 | #define MMP2_CLK_CLK32 1 | |
7 | #define MMP2_CLK_VCTCXO 2 | |
8 | #define MMP2_CLK_PLL1 3 | |
9 | #define MMP2_CLK_PLL1_2 8 | |
10 | #define MMP2_CLK_PLL1_4 9 | |
11 | #define MMP2_CLK_PLL1_8 10 | |
12 | #define MMP2_CLK_PLL1_16 11 | |
13 | #define MMP2_CLK_PLL1_3 12 | |
14 | #define MMP2_CLK_PLL1_6 13 | |
15 | #define MMP2_CLK_PLL1_12 14 | |
16 | #define MMP2_CLK_PLL1_20 15 | |
17 | #define MMP2_CLK_PLL2 16 | |
18 | #define MMP2_CLK_PLL2_2 17 | |
19 | #define MMP2_CLK_PLL2_4 18 | |
20 | #define MMP2_CLK_PLL2_8 19 | |
21 | #define MMP2_CLK_PLL2_16 20 | |
22 | #define MMP2_CLK_PLL2_3 21 | |
23 | #define MMP2_CLK_PLL2_6 22 | |
24 | #define MMP2_CLK_PLL2_12 23 | |
25 | #define MMP2_CLK_VCTCXO_2 24 | |
26 | #define MMP2_CLK_VCTCXO_4 25 | |
27 | #define MMP2_CLK_UART_PLL 26 | |
28 | #define MMP2_CLK_USB_PLL 27 | |
4d6da655 LR |
29 | #define MMP3_CLK_PLL1_P 28 |
30 | #define MMP3_CLK_PLL2_P 29 | |
31 | #define MMP3_CLK_PLL3 30 | |
edcec4a8 LR |
32 | #define MMP2_CLK_I2S0 31 |
33 | #define MMP2_CLK_I2S1 32 | |
1ec770d9 | 34 | |
6853fece | 35 | /* apb peripherals */ |
1ec770d9 CX |
36 | #define MMP2_CLK_TWSI0 60 |
37 | #define MMP2_CLK_TWSI1 61 | |
38 | #define MMP2_CLK_TWSI2 62 | |
39 | #define MMP2_CLK_TWSI3 63 | |
40 | #define MMP2_CLK_TWSI4 64 | |
41 | #define MMP2_CLK_TWSI5 65 | |
42 | #define MMP2_CLK_GPIO 66 | |
43 | #define MMP2_CLK_KPC 67 | |
44 | #define MMP2_CLK_RTC 68 | |
45 | #define MMP2_CLK_PWM0 69 | |
46 | #define MMP2_CLK_PWM1 70 | |
47 | #define MMP2_CLK_PWM2 71 | |
48 | #define MMP2_CLK_PWM3 72 | |
49 | #define MMP2_CLK_UART0 73 | |
50 | #define MMP2_CLK_UART1 74 | |
51 | #define MMP2_CLK_UART2 75 | |
52 | #define MMP2_CLK_UART3 76 | |
53 | #define MMP2_CLK_SSP0 77 | |
54 | #define MMP2_CLK_SSP1 78 | |
55 | #define MMP2_CLK_SSP2 79 | |
56 | #define MMP2_CLK_SSP3 80 | |
24c65a02 | 57 | #define MMP2_CLK_TIMER 81 |
41a86320 LR |
58 | #define MMP2_CLK_THERMAL0 82 |
59 | #define MMP3_CLK_THERMAL1 83 | |
60 | #define MMP3_CLK_THERMAL2 84 | |
61 | #define MMP3_CLK_THERMAL3 85 | |
1ec770d9 | 62 | |
6853fece | 63 | /* axi peripherals */ |
1ec770d9 CX |
64 | #define MMP2_CLK_SDH0 101 |
65 | #define MMP2_CLK_SDH1 102 | |
66 | #define MMP2_CLK_SDH2 103 | |
67 | #define MMP2_CLK_SDH3 104 | |
68 | #define MMP2_CLK_USB 105 | |
69 | #define MMP2_CLK_DISP0 106 | |
70 | #define MMP2_CLK_DISP0_MUX 107 | |
71 | #define MMP2_CLK_DISP0_SPHY 108 | |
72 | #define MMP2_CLK_DISP1 109 | |
73 | #define MMP2_CLK_DISP1_MUX 110 | |
74 | #define MMP2_CLK_CCIC_ARBITER 111 | |
75 | #define MMP2_CLK_CCIC0 112 | |
76 | #define MMP2_CLK_CCIC0_MIX 113 | |
77 | #define MMP2_CLK_CCIC0_PHY 114 | |
78 | #define MMP2_CLK_CCIC0_SPHY 115 | |
79 | #define MMP2_CLK_CCIC1 116 | |
80 | #define MMP2_CLK_CCIC1_MIX 117 | |
81 | #define MMP2_CLK_CCIC1_PHY 118 | |
82 | #define MMP2_CLK_CCIC1_SPHY 119 | |
ed11aff3 | 83 | #define MMP2_CLK_DISP0_LCDC 120 |
247aa9e4 LR |
84 | #define MMP2_CLK_USBHSIC0 121 |
85 | #define MMP2_CLK_USBHSIC1 122 | |
e3142226 LR |
86 | #define MMP2_CLK_GPU_BUS 123 |
87 | #define MMP3_CLK_GPU_BUS MMP2_CLK_GPU_BUS | |
88 | #define MMP2_CLK_GPU_3D 124 | |
89 | #define MMP3_CLK_GPU_3D MMP2_CLK_GPU_3D | |
90 | #define MMP3_CLK_GPU_2D 125 | |
c2ca122a | 91 | #define MMP3_CLK_SDH4 126 |
c227df7a | 92 | #define MMP2_CLK_AUDIO 127 |
1ec770d9 CX |
93 | |
94 | #define MMP2_NR_CLKS 200 | |
95 | #endif |