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25db146a JH |
1 | /* SPDX-License-Identifier: GPL-2.0+ OR MIT */ |
2 | /* | |
3 | * Meson-G12A clock tree IDs | |
4 | * | |
5 | * Copyright (c) 2018 Amlogic, Inc. All rights reserved. | |
6 | */ | |
7 | ||
8 | #ifndef __G12A_CLKC_H | |
9 | #define __G12A_CLKC_H | |
10 | ||
11 | #define CLKID_SYS_PLL 0 | |
12 | #define CLKID_FIXED_PLL 1 | |
13 | #define CLKID_FCLK_DIV2 2 | |
14 | #define CLKID_FCLK_DIV3 3 | |
15 | #define CLKID_FCLK_DIV4 4 | |
16 | #define CLKID_FCLK_DIV5 5 | |
17 | #define CLKID_FCLK_DIV7 6 | |
18 | #define CLKID_GP0_PLL 7 | |
19 | #define CLKID_CLK81 10 | |
20 | #define CLKID_MPLL0 11 | |
21 | #define CLKID_MPLL1 12 | |
22 | #define CLKID_MPLL2 13 | |
23 | #define CLKID_MPLL3 14 | |
24 | #define CLKID_DDR 15 | |
25 | #define CLKID_DOS 16 | |
26 | #define CLKID_AUDIO_LOCKER 17 | |
27 | #define CLKID_MIPI_DSI_HOST 18 | |
28 | #define CLKID_ETH_PHY 19 | |
29 | #define CLKID_ISA 20 | |
30 | #define CLKID_PL301 21 | |
31 | #define CLKID_PERIPHS 22 | |
32 | #define CLKID_SPICC0 23 | |
33 | #define CLKID_I2C 24 | |
34 | #define CLKID_SANA 25 | |
35 | #define CLKID_SD 26 | |
36 | #define CLKID_RNG0 27 | |
37 | #define CLKID_UART0 28 | |
38 | #define CLKID_SPICC1 29 | |
39 | #define CLKID_HIU_IFACE 30 | |
40 | #define CLKID_MIPI_DSI_PHY 31 | |
41 | #define CLKID_ASSIST_MISC 32 | |
42 | #define CLKID_SD_EMMC_A 33 | |
43 | #define CLKID_SD_EMMC_B 34 | |
44 | #define CLKID_SD_EMMC_C 35 | |
45 | #define CLKID_AUDIO_CODEC 36 | |
46 | #define CLKID_AUDIO 37 | |
47 | #define CLKID_ETH 38 | |
48 | #define CLKID_DEMUX 39 | |
49 | #define CLKID_AUDIO_IFIFO 40 | |
50 | #define CLKID_ADC 41 | |
51 | #define CLKID_UART1 42 | |
52 | #define CLKID_G2D 43 | |
53 | #define CLKID_RESET 44 | |
54 | #define CLKID_PCIE_COMB 45 | |
55 | #define CLKID_PARSER 46 | |
56 | #define CLKID_USB 47 | |
57 | #define CLKID_PCIE_PHY 48 | |
58 | #define CLKID_AHB_ARB0 49 | |
59 | #define CLKID_AHB_DATA_BUS 50 | |
60 | #define CLKID_AHB_CTRL_BUS 51 | |
61 | #define CLKID_HTX_HDCP22 52 | |
62 | #define CLKID_HTX_PCLK 53 | |
63 | #define CLKID_BT656 54 | |
64 | #define CLKID_USB1_DDR_BRIDGE 55 | |
65 | #define CLKID_MMC_PCLK 56 | |
66 | #define CLKID_UART2 57 | |
67 | #define CLKID_VPU_INTR 58 | |
68 | #define CLKID_GIC 59 | |
69 | #define CLKID_SD_EMMC_A_CLK0 60 | |
70 | #define CLKID_SD_EMMC_B_CLK0 61 | |
71 | #define CLKID_SD_EMMC_C_CLK0 62 | |
72 | #define CLKID_HIFI_PLL 74 | |
73 | #define CLKID_VCLK2_VENCI0 80 | |
74 | #define CLKID_VCLK2_VENCI1 81 | |
75 | #define CLKID_VCLK2_VENCP0 82 | |
76 | #define CLKID_VCLK2_VENCP1 83 | |
77 | #define CLKID_VCLK2_VENCT0 84 | |
78 | #define CLKID_VCLK2_VENCT1 85 | |
79 | #define CLKID_VCLK2_OTHER 86 | |
80 | #define CLKID_VCLK2_ENCI 87 | |
81 | #define CLKID_VCLK2_ENCP 88 | |
82 | #define CLKID_DAC_CLK 89 | |
83 | #define CLKID_AOCLK 90 | |
84 | #define CLKID_IEC958 91 | |
85 | #define CLKID_ENC480P 92 | |
86 | #define CLKID_RNG1 93 | |
87 | #define CLKID_VCLK2_ENCT 94 | |
88 | #define CLKID_VCLK2_ENCL 95 | |
89 | #define CLKID_VCLK2_VENCLMMC 96 | |
90 | #define CLKID_VCLK2_VENCL 97 | |
91 | #define CLKID_VCLK2_OTHER1 98 | |
92 | #define CLKID_FCLK_DIV2P5 99 | |
93 | #define CLKID_DMA 105 | |
94 | #define CLKID_EFUSE 106 | |
95 | #define CLKID_ROM_BOOT 107 | |
96 | #define CLKID_RESET_SEC 108 | |
97 | #define CLKID_SEC_AHB_APB3 109 | |
98 | #define CLKID_VPU_0_SEL 110 | |
99 | #define CLKID_VPU_0 112 | |
100 | #define CLKID_VPU_1_SEL 113 | |
101 | #define CLKID_VPU_1 115 | |
102 | #define CLKID_VPU 116 | |
103 | #define CLKID_VAPB_0_SEL 117 | |
104 | #define CLKID_VAPB_0 119 | |
105 | #define CLKID_VAPB_1_SEL 120 | |
106 | #define CLKID_VAPB_1 122 | |
107 | #define CLKID_VAPB_SEL 123 | |
108 | #define CLKID_VAPB 124 | |
109 | #define CLKID_HDMI_PLL 128 | |
110 | #define CLKID_VID_PLL 129 | |
111 | #define CLKID_VCLK 138 | |
112 | #define CLKID_VCLK2 139 | |
113 | #define CLKID_VCLK_DIV1 148 | |
114 | #define CLKID_VCLK_DIV2 149 | |
115 | #define CLKID_VCLK_DIV4 150 | |
116 | #define CLKID_VCLK_DIV6 151 | |
117 | #define CLKID_VCLK_DIV12 152 | |
118 | #define CLKID_VCLK2_DIV1 153 | |
119 | #define CLKID_VCLK2_DIV2 154 | |
120 | #define CLKID_VCLK2_DIV4 155 | |
121 | #define CLKID_VCLK2_DIV6 156 | |
122 | #define CLKID_VCLK2_DIV12 157 | |
123 | #define CLKID_CTS_ENCI 162 | |
124 | #define CLKID_CTS_ENCP 163 | |
125 | #define CLKID_CTS_VDAC 164 | |
126 | #define CLKID_HDMI_TX 165 | |
127 | #define CLKID_HDMI 168 | |
128 | #define CLKID_MALI_0_SEL 169 | |
129 | #define CLKID_MALI_0 171 | |
130 | #define CLKID_MALI_1_SEL 172 | |
131 | #define CLKID_MALI_1 174 | |
132 | #define CLKID_MALI 175 | |
e63b063e | 133 | #define CLKID_MPLL_50M 177 |
58b5c8ac | 134 | #define CLKID_CPU_CLK 187 |
17750f52 | 135 | #define CLKID_PCIE_PLL 201 |
19478907 MJ |
136 | #define CLKID_VDEC_1 204 |
137 | #define CLKID_VDEC_HEVC 207 | |
138 | #define CLKID_VDEC_HEVCF 210 | |
6e47ef34 | 139 | #define CLKID_TS 212 |
85ab9d95 | 140 | #define CLKID_CPUB_CLK 224 |
cda45691 NA |
141 | #define CLKID_GP1_PLL 243 |
142 | #define CLKID_DSU_CLK 252 | |
143 | #define CLKID_CPU1_CLK 253 | |
144 | #define CLKID_CPU2_CLK 254 | |
145 | #define CLKID_CPU3_CLK 255 | |
42be7c41 NA |
146 | #define CLKID_SPICC0_SCLK 258 |
147 | #define CLKID_SPICC1_SCLK 261 | |
df062301 DS |
148 | #define CLKID_NNA_AXI_CLK 264 |
149 | #define CLKID_NNA_CORE_CLK 267 | |
31248979 NA |
150 | #define CLKID_MIPI_DSI_PXCLK_SEL 269 |
151 | #define CLKID_MIPI_DSI_PXCLK 270 | |
25db146a JH |
152 | |
153 | #endif /* __G12A_CLKC_H */ |