projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 9c92ab61 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| ae263d52 TK |
2 | /* |
| 3 | * Copyright 2017 Texas Instruments, Inc. | |
| ae263d52 TK |
4 | */ |
| 5 | #ifndef __DT_BINDINGS_CLK_DRA7_H | |
| 6 | #define __DT_BINDINGS_CLK_DRA7_H | |
| 7 | ||
| 8 | #define DRA7_CLKCTRL_OFFSET 0x20 | |
| 9 | #define DRA7_CLKCTRL_INDEX(offset) ((offset) - DRA7_CLKCTRL_OFFSET) | |
| 10 | ||
| 8fa45095 TK |
11 | /* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */ |
| 12 | ||
| ae263d52 TK |
13 | /* mpu clocks */ |
| 14 | #define DRA7_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) | |
| 15 | ||
| 16 | /* ipu clocks */ | |
| 8fa45095 TK |
17 | #define _DRA7_IPU_CLKCTRL_OFFSET 0x40 |
| 18 | #define _DRA7_IPU_CLKCTRL_INDEX(offset) ((offset) - _DRA7_IPU_CLKCTRL_OFFSET) | |
| 19 | #define DRA7_MCASP1_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x50) | |
| 20 | #define DRA7_TIMER5_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x58) | |
| 21 | #define DRA7_TIMER6_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x60) | |
| 22 | #define DRA7_TIMER7_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x68) | |
| 23 | #define DRA7_TIMER8_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x70) | |
| 24 | #define DRA7_I2C5_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x78) | |
| 25 | #define DRA7_UART6_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x80) | |
| ae263d52 TK |
26 | |
| 27 | /* rtc clocks */ | |
| 28 | #define DRA7_RTC_CLKCTRL_OFFSET 0x40 | |
| 29 | #define DRA7_RTC_CLKCTRL_INDEX(offset) ((offset) - DRA7_RTC_CLKCTRL_OFFSET) | |
| 30 | #define DRA7_RTCSS_CLKCTRL DRA7_RTC_CLKCTRL_INDEX(0x44) | |
| 31 | ||
| 32 | /* coreaon clocks */ | |
| 33 | #define DRA7_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) | |
| 34 | #define DRA7_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38) | |
| 35 | ||
| 36 | /* l3main1 clocks */ | |
| 37 | #define DRA7_L3_MAIN_1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) | |
| 38 | #define DRA7_GPMC_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) | |
| 39 | #define DRA7_TPCC_CLKCTRL DRA7_CLKCTRL_INDEX(0x70) | |
| 40 | #define DRA7_TPTC0_CLKCTRL DRA7_CLKCTRL_INDEX(0x78) | |
| 41 | #define DRA7_TPTC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) | |
| 42 | #define DRA7_VCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) | |
| 43 | #define DRA7_VCP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x90) | |
| 44 | ||
| 45 | /* dma clocks */ | |
| 46 | #define DRA7_DMA_SYSTEM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) | |
| 47 | ||
| 48 | /* emif clocks */ | |
| 49 | #define DRA7_DMM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) | |
| 50 | ||
| 51 | /* atl clocks */ | |
| 52 | #define DRA7_ATL_CLKCTRL_OFFSET 0x0 | |
| 53 | #define DRA7_ATL_CLKCTRL_INDEX(offset) ((offset) - DRA7_ATL_CLKCTRL_OFFSET) | |
| 54 | #define DRA7_ATL_CLKCTRL DRA7_ATL_CLKCTRL_INDEX(0x0) | |
| 55 | ||
| 56 | /* l4cfg clocks */ | |
| 57 | #define DRA7_L4_CFG_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) | |
| 58 | #define DRA7_SPINLOCK_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) | |
| 59 | #define DRA7_MAILBOX1_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) | |
| 60 | #define DRA7_MAILBOX2_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) | |
| 61 | #define DRA7_MAILBOX3_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) | |
| 62 | #define DRA7_MAILBOX4_CLKCTRL DRA7_CLKCTRL_INDEX(0x58) | |
| 63 | #define DRA7_MAILBOX5_CLKCTRL DRA7_CLKCTRL_INDEX(0x60) | |
| 64 | #define DRA7_MAILBOX6_CLKCTRL DRA7_CLKCTRL_INDEX(0x68) | |
| 65 | #define DRA7_MAILBOX7_CLKCTRL DRA7_CLKCTRL_INDEX(0x70) | |
| 66 | #define DRA7_MAILBOX8_CLKCTRL DRA7_CLKCTRL_INDEX(0x78) | |
| 67 | #define DRA7_MAILBOX9_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) | |
| 68 | #define DRA7_MAILBOX10_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) | |
| 69 | #define DRA7_MAILBOX11_CLKCTRL DRA7_CLKCTRL_INDEX(0x90) | |
| 70 | #define DRA7_MAILBOX12_CLKCTRL DRA7_CLKCTRL_INDEX(0x98) | |
| 71 | #define DRA7_MAILBOX13_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0) | |
| 72 | ||
| 73 | /* l3instr clocks */ | |
| 74 | #define DRA7_L3_MAIN_2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) | |
| 75 | #define DRA7_L3_INSTR_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) | |
| 76 | ||
| 77 | /* dss clocks */ | |
| 78 | #define DRA7_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) | |
| 79 | #define DRA7_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) | |
| 80 | ||
| 81 | /* l3init clocks */ | |
| 82 | #define DRA7_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) | |
| 83 | #define DRA7_MMC2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) | |
| 84 | #define DRA7_USB_OTG_SS2_CLKCTRL DRA7_CLKCTRL_INDEX(0x40) | |
| 85 | #define DRA7_USB_OTG_SS3_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) | |
| 86 | #define DRA7_USB_OTG_SS4_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) | |
| 87 | #define DRA7_SATA_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) | |
| 88 | #define DRA7_PCIE1_CLKCTRL DRA7_CLKCTRL_INDEX(0xb0) | |
| 89 | #define DRA7_PCIE2_CLKCTRL DRA7_CLKCTRL_INDEX(0xb8) | |
| 90 | #define DRA7_GMAC_CLKCTRL DRA7_CLKCTRL_INDEX(0xd0) | |
| 91 | #define DRA7_OCP2SCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0xe0) | |
| 92 | #define DRA7_OCP2SCP3_CLKCTRL DRA7_CLKCTRL_INDEX(0xe8) | |
| 93 | #define DRA7_USB_OTG_SS1_CLKCTRL DRA7_CLKCTRL_INDEX(0xf0) | |
| 94 | ||
| 95 | /* l4per clocks */ | |
| 8fa45095 TK |
96 | #define _DRA7_L4PER_CLKCTRL_OFFSET 0x0 |
| 97 | #define _DRA7_L4PER_CLKCTRL_INDEX(offset) ((offset) - _DRA7_L4PER_CLKCTRL_OFFSET) | |
| 98 | #define DRA7_L4_PER2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc) | |
| 99 | #define DRA7_L4_PER3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x14) | |
| 100 | #define DRA7_TIMER10_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x28) | |
| 101 | #define DRA7_TIMER11_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x30) | |
| 102 | #define DRA7_TIMER2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x38) | |
| 103 | #define DRA7_TIMER3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x40) | |
| 104 | #define DRA7_TIMER4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x48) | |
| 105 | #define DRA7_TIMER9_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x50) | |
| 106 | #define DRA7_ELM_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x58) | |
| 107 | #define DRA7_GPIO2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x60) | |
| 108 | #define DRA7_GPIO3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x68) | |
| 109 | #define DRA7_GPIO4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x70) | |
| 110 | #define DRA7_GPIO5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x78) | |
| 111 | #define DRA7_GPIO6_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x80) | |
| 112 | #define DRA7_HDQ1W_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x88) | |
| 113 | #define DRA7_EPWMSS1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x90) | |
| 114 | #define DRA7_EPWMSS2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x98) | |
| 115 | #define DRA7_I2C1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xa0) | |
| 116 | #define DRA7_I2C2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xa8) | |
| 117 | #define DRA7_I2C3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xb0) | |
| 118 | #define DRA7_I2C4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xb8) | |
| 119 | #define DRA7_L4_PER1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc0) | |
| 120 | #define DRA7_EPWMSS0_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc4) | |
| 121 | #define DRA7_TIMER13_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc8) | |
| 122 | #define DRA7_TIMER14_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xd0) | |
| 123 | #define DRA7_TIMER15_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xd8) | |
| 124 | #define DRA7_MCSPI1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xf0) | |
| 125 | #define DRA7_MCSPI2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xf8) | |
| 126 | #define DRA7_MCSPI3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x100) | |
| 127 | #define DRA7_MCSPI4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x108) | |
| 128 | #define DRA7_GPIO7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x110) | |
| 129 | #define DRA7_GPIO8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x118) | |
| 130 | #define DRA7_MMC3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x120) | |
| 131 | #define DRA7_MMC4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x128) | |
| 132 | #define DRA7_TIMER16_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x130) | |
| 133 | #define DRA7_QSPI_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x138) | |
| 134 | #define DRA7_UART1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x140) | |
| 135 | #define DRA7_UART2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x148) | |
| 136 | #define DRA7_UART3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x150) | |
| 137 | #define DRA7_UART4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x158) | |
| 138 | #define DRA7_MCASP2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x160) | |
| 139 | #define DRA7_MCASP3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x168) | |
| 140 | #define DRA7_UART5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x170) | |
| 141 | #define DRA7_MCASP5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x178) | |
| 142 | #define DRA7_MCASP8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x190) | |
| 143 | #define DRA7_MCASP4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x198) | |
| 144 | #define DRA7_AES1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1a0) | |
| 145 | #define DRA7_AES2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1a8) | |
| 146 | #define DRA7_DES_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1b0) | |
| 147 | #define DRA7_RNG_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1c0) | |
| 148 | #define DRA7_SHAM_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1c8) | |
| 149 | #define DRA7_UART7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1d0) | |
| 150 | #define DRA7_UART8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1e0) | |
| 151 | #define DRA7_UART9_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1e8) | |
| 152 | #define DRA7_DCAN2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1f0) | |
| 153 | #define DRA7_MCASP6_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x204) | |
| 154 | #define DRA7_MCASP7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x208) | |
| ae263d52 TK |
155 | |
| 156 | /* wkupaon clocks */ | |
| 157 | #define DRA7_L4_WKUP_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) | |
| 158 | #define DRA7_WD_TIMER2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) | |
| 159 | #define DRA7_GPIO1_CLKCTRL DRA7_CLKCTRL_INDEX(0x38) | |
| 160 | #define DRA7_TIMER1_CLKCTRL DRA7_CLKCTRL_INDEX(0x40) | |
| 161 | #define DRA7_TIMER12_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) | |
| 162 | #define DRA7_COUNTER_32K_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) | |
| 163 | #define DRA7_UART10_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) | |
| 164 | #define DRA7_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) | |
| 91c17a70 | 165 | #define DRA7_ADC_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0) |
| ae263d52 | 166 | |
| 8fa45095 TK |
167 | /* XXX: Compatibility part end. */ |
| 168 | ||
| 169 | /* mpu clocks */ | |
| 170 | #define DRA7_MPU_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) | |
| 171 | ||
| 172 | /* dsp1 clocks */ | |
| 173 | #define DRA7_DSP1_MMU0_DSP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) | |
| 174 | ||
| 175 | /* ipu1 clocks */ | |
| 176 | #define DRA7_IPU1_MMU_IPU1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) | |
| 177 | ||
| 178 | /* ipu clocks */ | |
| 179 | #define DRA7_IPU_CLKCTRL_OFFSET 0x50 | |
| 180 | #define DRA7_IPU_CLKCTRL_INDEX(offset) ((offset) - DRA7_IPU_CLKCTRL_OFFSET) | |
| 181 | #define DRA7_IPU_MCASP1_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x50) | |
| 182 | #define DRA7_IPU_TIMER5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x58) | |
| 183 | #define DRA7_IPU_TIMER6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x60) | |
| 184 | #define DRA7_IPU_TIMER7_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x68) | |
| 185 | #define DRA7_IPU_TIMER8_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x70) | |
| 186 | #define DRA7_IPU_I2C5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x78) | |
| 187 | #define DRA7_IPU_UART6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x80) | |
| 188 | ||
| 189 | /* dsp2 clocks */ | |
| 190 | #define DRA7_DSP2_MMU0_DSP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) | |
| 191 | ||
| 192 | /* rtc clocks */ | |
| 193 | #define DRA7_RTC_RTCSS_CLKCTRL DRA7_CLKCTRL_INDEX(0x44) | |
| 194 | ||
| 195 | /* coreaon clocks */ | |
| 196 | #define DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) | |
| 197 | #define DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38) | |
| 198 | ||
| 199 | /* l3main1 clocks */ | |
| 200 | #define DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) | |
| 201 | #define DRA7_L3MAIN1_GPMC_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) | |
| 202 | #define DRA7_L3MAIN1_TPCC_CLKCTRL DRA7_CLKCTRL_INDEX(0x70) | |
| 203 | #define DRA7_L3MAIN1_TPTC0_CLKCTRL DRA7_CLKCTRL_INDEX(0x78) | |
| 204 | #define DRA7_L3MAIN1_TPTC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) | |
| 205 | #define DRA7_L3MAIN1_VCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) | |
| 206 | #define DRA7_L3MAIN1_VCP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x90) | |
| 207 | ||
| 208 | /* ipu2 clocks */ | |
| 209 | #define DRA7_IPU2_MMU_IPU2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) | |
| 210 | ||
| 211 | /* dma clocks */ | |
| 212 | #define DRA7_DMA_DMA_SYSTEM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) | |
| 213 | ||
| 214 | /* emif clocks */ | |
| 215 | #define DRA7_EMIF_DMM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) | |
| 216 | ||
| 217 | /* atl clocks */ | |
| 218 | #define DRA7_ATL_CLKCTRL_OFFSET 0x0 | |
| 219 | #define DRA7_ATL_CLKCTRL_INDEX(offset) ((offset) - DRA7_ATL_CLKCTRL_OFFSET) | |
| 220 | #define DRA7_ATL_ATL_CLKCTRL DRA7_ATL_CLKCTRL_INDEX(0x0) | |
| 221 | ||
| 222 | /* l4cfg clocks */ | |
| 223 | #define DRA7_L4CFG_L4_CFG_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) | |
| 224 | #define DRA7_L4CFG_SPINLOCK_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) | |
| 225 | #define DRA7_L4CFG_MAILBOX1_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) | |
| 226 | #define DRA7_L4CFG_MAILBOX2_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) | |
| 227 | #define DRA7_L4CFG_MAILBOX3_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) | |
| 228 | #define DRA7_L4CFG_MAILBOX4_CLKCTRL DRA7_CLKCTRL_INDEX(0x58) | |
| 229 | #define DRA7_L4CFG_MAILBOX5_CLKCTRL DRA7_CLKCTRL_INDEX(0x60) | |
| 230 | #define DRA7_L4CFG_MAILBOX6_CLKCTRL DRA7_CLKCTRL_INDEX(0x68) | |
| 231 | #define DRA7_L4CFG_MAILBOX7_CLKCTRL DRA7_CLKCTRL_INDEX(0x70) | |
| 232 | #define DRA7_L4CFG_MAILBOX8_CLKCTRL DRA7_CLKCTRL_INDEX(0x78) | |
| 233 | #define DRA7_L4CFG_MAILBOX9_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) | |
| 234 | #define DRA7_L4CFG_MAILBOX10_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) | |
| 235 | #define DRA7_L4CFG_MAILBOX11_CLKCTRL DRA7_CLKCTRL_INDEX(0x90) | |
| 236 | #define DRA7_L4CFG_MAILBOX12_CLKCTRL DRA7_CLKCTRL_INDEX(0x98) | |
| 237 | #define DRA7_L4CFG_MAILBOX13_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0) | |
| 238 | ||
| 239 | /* l3instr clocks */ | |
| 240 | #define DRA7_L3INSTR_L3_MAIN_2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) | |
| 241 | #define DRA7_L3INSTR_L3_INSTR_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) | |
| 242 | ||
| 243 | /* dss clocks */ | |
| 244 | #define DRA7_DSS_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) | |
| 245 | #define DRA7_DSS_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) | |
| 246 | ||
| 247 | /* l3init clocks */ | |
| 248 | #define DRA7_L3INIT_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) | |
| 249 | #define DRA7_L3INIT_MMC2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) | |
| 250 | #define DRA7_L3INIT_USB_OTG_SS2_CLKCTRL DRA7_CLKCTRL_INDEX(0x40) | |
| 251 | #define DRA7_L3INIT_USB_OTG_SS3_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) | |
| 252 | #define DRA7_L3INIT_USB_OTG_SS4_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) | |
| 253 | #define DRA7_L3INIT_SATA_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) | |
| 254 | #define DRA7_L3INIT_OCP2SCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0xe0) | |
| 255 | #define DRA7_L3INIT_OCP2SCP3_CLKCTRL DRA7_CLKCTRL_INDEX(0xe8) | |
| 256 | #define DRA7_L3INIT_USB_OTG_SS1_CLKCTRL DRA7_CLKCTRL_INDEX(0xf0) | |
| 257 | ||
| 258 | /* pcie clocks */ | |
| 259 | #define DRA7_PCIE_CLKCTRL_OFFSET 0xb0 | |
| 260 | #define DRA7_PCIE_CLKCTRL_INDEX(offset) ((offset) - DRA7_PCIE_CLKCTRL_OFFSET) | |
| 261 | #define DRA7_PCIE_PCIE1_CLKCTRL DRA7_PCIE_CLKCTRL_INDEX(0xb0) | |
| 262 | #define DRA7_PCIE_PCIE2_CLKCTRL DRA7_PCIE_CLKCTRL_INDEX(0xb8) | |
| 263 | ||
| 264 | /* gmac clocks */ | |
| 265 | #define DRA7_GMAC_CLKCTRL_OFFSET 0xd0 | |
| 266 | #define DRA7_GMAC_CLKCTRL_INDEX(offset) ((offset) - DRA7_GMAC_CLKCTRL_OFFSET) | |
| 267 | #define DRA7_GMAC_GMAC_CLKCTRL DRA7_GMAC_CLKCTRL_INDEX(0xd0) | |
| 268 | ||
| 269 | /* l4per clocks */ | |
| 270 | #define DRA7_L4PER_CLKCTRL_OFFSET 0x28 | |
| 271 | #define DRA7_L4PER_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER_CLKCTRL_OFFSET) | |
| 272 | #define DRA7_L4PER_TIMER10_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x28) | |
| 273 | #define DRA7_L4PER_TIMER11_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x30) | |
| 274 | #define DRA7_L4PER_TIMER2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x38) | |
| 275 | #define DRA7_L4PER_TIMER3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x40) | |
| 276 | #define DRA7_L4PER_TIMER4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x48) | |
| 277 | #define DRA7_L4PER_TIMER9_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x50) | |
| 278 | #define DRA7_L4PER_ELM_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x58) | |
| 279 | #define DRA7_L4PER_GPIO2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x60) | |
| 280 | #define DRA7_L4PER_GPIO3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x68) | |
| 281 | #define DRA7_L4PER_GPIO4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x70) | |
| 282 | #define DRA7_L4PER_GPIO5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x78) | |
| 283 | #define DRA7_L4PER_GPIO6_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x80) | |
| 284 | #define DRA7_L4PER_HDQ1W_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x88) | |
| 285 | #define DRA7_L4PER_I2C1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa0) | |
| 286 | #define DRA7_L4PER_I2C2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa8) | |
| 287 | #define DRA7_L4PER_I2C3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb0) | |
| 288 | #define DRA7_L4PER_I2C4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb8) | |
| 289 | #define DRA7_L4PER_L4_PER1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc0) | |
| 290 | #define DRA7_L4PER_MCSPI1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf0) | |
| 291 | #define DRA7_L4PER_MCSPI2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf8) | |
| 292 | #define DRA7_L4PER_MCSPI3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x100) | |
| 293 | #define DRA7_L4PER_MCSPI4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x108) | |
| 294 | #define DRA7_L4PER_GPIO7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x110) | |
| 295 | #define DRA7_L4PER_GPIO8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x118) | |
| 296 | #define DRA7_L4PER_MMC3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x120) | |
| 297 | #define DRA7_L4PER_MMC4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x128) | |
| 298 | #define DRA7_L4PER_UART1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x140) | |
| 299 | #define DRA7_L4PER_UART2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x148) | |
| 300 | #define DRA7_L4PER_UART3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x150) | |
| 301 | #define DRA7_L4PER_UART4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x158) | |
| 302 | #define DRA7_L4PER_UART5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x170) | |
| 303 | ||
| 304 | /* l4sec clocks */ | |
| 305 | #define DRA7_L4SEC_CLKCTRL_OFFSET 0x1a0 | |
| 306 | #define DRA7_L4SEC_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4SEC_CLKCTRL_OFFSET) | |
| 307 | #define DRA7_L4SEC_AES1_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1a0) | |
| 308 | #define DRA7_L4SEC_AES2_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1a8) | |
| 309 | #define DRA7_L4SEC_DES_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1b0) | |
| 310 | #define DRA7_L4SEC_RNG_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1c0) | |
| 311 | #define DRA7_L4SEC_SHAM_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1c8) | |
| 312 | ||
| 313 | /* l4per2 clocks */ | |
| 314 | #define DRA7_L4PER2_CLKCTRL_OFFSET 0xc | |
| 315 | #define DRA7_L4PER2_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER2_CLKCTRL_OFFSET) | |
| 316 | #define DRA7_L4PER2_L4_PER2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0xc) | |
| 317 | #define DRA7_L4PER2_PRUSS1_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x18) | |
| 318 | #define DRA7_L4PER2_PRUSS2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x20) | |
| 319 | #define DRA7_L4PER2_EPWMSS1_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x90) | |
| 320 | #define DRA7_L4PER2_EPWMSS2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x98) | |
| 321 | #define DRA7_L4PER2_EPWMSS0_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0xc4) | |
| 322 | #define DRA7_L4PER2_QSPI_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x138) | |
| 323 | #define DRA7_L4PER2_MCASP2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x160) | |
| 324 | #define DRA7_L4PER2_MCASP3_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x168) | |
| 325 | #define DRA7_L4PER2_MCASP5_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x178) | |
| 326 | #define DRA7_L4PER2_MCASP8_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x190) | |
| 327 | #define DRA7_L4PER2_MCASP4_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x198) | |
| 328 | #define DRA7_L4PER2_UART7_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1d0) | |
| 329 | #define DRA7_L4PER2_UART8_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1e0) | |
| 330 | #define DRA7_L4PER2_UART9_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1e8) | |
| 331 | #define DRA7_L4PER2_DCAN2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1f0) | |
| 332 | #define DRA7_L4PER2_MCASP6_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x204) | |
| 333 | #define DRA7_L4PER2_MCASP7_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x208) | |
| 334 | ||
| 335 | /* l4per3 clocks */ | |
| 336 | #define DRA7_L4PER3_CLKCTRL_OFFSET 0x14 | |
| 337 | #define DRA7_L4PER3_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER3_CLKCTRL_OFFSET) | |
| 338 | #define DRA7_L4PER3_L4_PER3_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0x14) | |
| 339 | #define DRA7_L4PER3_TIMER13_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0xc8) | |
| 340 | #define DRA7_L4PER3_TIMER14_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0xd0) | |
| 341 | #define DRA7_L4PER3_TIMER15_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0xd8) | |
| 342 | #define DRA7_L4PER3_TIMER16_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0x130) | |
| 343 | ||
| 344 | /* wkupaon clocks */ | |
| 345 | #define DRA7_WKUPAON_L4_WKUP_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) | |
| 346 | #define DRA7_WKUPAON_WD_TIMER2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) | |
| 347 | #define DRA7_WKUPAON_GPIO1_CLKCTRL DRA7_CLKCTRL_INDEX(0x38) | |
| 348 | #define DRA7_WKUPAON_TIMER1_CLKCTRL DRA7_CLKCTRL_INDEX(0x40) | |
| 349 | #define DRA7_WKUPAON_TIMER12_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) | |
| 350 | #define DRA7_WKUPAON_COUNTER_32K_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) | |
| 351 | #define DRA7_WKUPAON_UART10_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) | |
| 352 | #define DRA7_WKUPAON_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) | |
| 353 | #define DRA7_WKUPAON_ADC_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0) | |
| 354 | ||
| ae263d52 | 355 | #endif |