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1 | /* |
2 | * Copyright 2005 Stephane Marchesin. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | */ | |
24 | ||
25 | #ifndef __NOUVEAU_DRM_H__ | |
26 | #define __NOUVEAU_DRM_H__ | |
27 | ||
a1606a95 | 28 | #define NOUVEAU_DRM_HEADER_PATCHLEVEL 16 |
6ee73861 BS |
29 | |
30 | struct drm_nouveau_channel_alloc { | |
31 | uint32_t fb_ctxdma_handle; | |
32 | uint32_t tt_ctxdma_handle; | |
33 | ||
34 | int channel; | |
a1606a95 | 35 | uint32_t pushbuf_domains; |
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36 | |
37 | /* Notifier memory */ | |
38 | uint32_t notifier_handle; | |
39 | ||
40 | /* DRM-enforced subchannel assignments */ | |
41 | struct { | |
42 | uint32_t handle; | |
43 | uint32_t grclass; | |
44 | } subchan[8]; | |
45 | uint32_t nr_subchan; | |
46 | }; | |
47 | ||
48 | struct drm_nouveau_channel_free { | |
49 | int channel; | |
50 | }; | |
51 | ||
52 | struct drm_nouveau_grobj_alloc { | |
53 | int channel; | |
54 | uint32_t handle; | |
55 | int class; | |
56 | }; | |
57 | ||
58 | struct drm_nouveau_notifierobj_alloc { | |
59 | uint32_t channel; | |
60 | uint32_t handle; | |
61 | uint32_t size; | |
62 | uint32_t offset; | |
63 | }; | |
64 | ||
65 | struct drm_nouveau_gpuobj_free { | |
66 | int channel; | |
67 | uint32_t handle; | |
68 | }; | |
69 | ||
70 | /* FIXME : maybe unify {GET,SET}PARAMs */ | |
71 | #define NOUVEAU_GETPARAM_PCI_VENDOR 3 | |
72 | #define NOUVEAU_GETPARAM_PCI_DEVICE 4 | |
73 | #define NOUVEAU_GETPARAM_BUS_TYPE 5 | |
74 | #define NOUVEAU_GETPARAM_FB_PHYSICAL 6 | |
75 | #define NOUVEAU_GETPARAM_AGP_PHYSICAL 7 | |
76 | #define NOUVEAU_GETPARAM_FB_SIZE 8 | |
77 | #define NOUVEAU_GETPARAM_AGP_SIZE 9 | |
78 | #define NOUVEAU_GETPARAM_PCI_PHYSICAL 10 | |
79 | #define NOUVEAU_GETPARAM_CHIPSET_ID 11 | |
80 | #define NOUVEAU_GETPARAM_VM_VRAM_BASE 12 | |
69c9700b | 81 | #define NOUVEAU_GETPARAM_GRAPH_UNITS 13 |
7fc74f17 | 82 | #define NOUVEAU_GETPARAM_PTIMER_TIME 14 |
6ee73861 BS |
83 | struct drm_nouveau_getparam { |
84 | uint64_t param; | |
85 | uint64_t value; | |
86 | }; | |
87 | ||
88 | struct drm_nouveau_setparam { | |
89 | uint64_t param; | |
90 | uint64_t value; | |
91 | }; | |
92 | ||
93 | #define NOUVEAU_GEM_DOMAIN_CPU (1 << 0) | |
94 | #define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1) | |
95 | #define NOUVEAU_GEM_DOMAIN_GART (1 << 2) | |
96 | #define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3) | |
97 | ||
98 | struct drm_nouveau_gem_info { | |
99 | uint32_t handle; | |
100 | uint32_t domain; | |
101 | uint64_t size; | |
102 | uint64_t offset; | |
103 | uint64_t map_handle; | |
104 | uint32_t tile_mode; | |
105 | uint32_t tile_flags; | |
106 | }; | |
107 | ||
108 | struct drm_nouveau_gem_new { | |
109 | struct drm_nouveau_gem_info info; | |
110 | uint32_t channel_hint; | |
111 | uint32_t align; | |
112 | }; | |
113 | ||
a1606a95 BS |
114 | #define NOUVEAU_GEM_MAX_BUFFERS 1024 |
115 | struct drm_nouveau_gem_pushbuf_bo_presumed { | |
116 | uint32_t valid; | |
117 | uint32_t domain; | |
118 | uint64_t offset; | |
119 | }; | |
120 | ||
6ee73861 BS |
121 | struct drm_nouveau_gem_pushbuf_bo { |
122 | uint64_t user_priv; | |
123 | uint32_t handle; | |
124 | uint32_t read_domains; | |
125 | uint32_t write_domains; | |
126 | uint32_t valid_domains; | |
a1606a95 | 127 | struct drm_nouveau_gem_pushbuf_bo_presumed presumed; |
6ee73861 BS |
128 | }; |
129 | ||
130 | #define NOUVEAU_GEM_RELOC_LOW (1 << 0) | |
131 | #define NOUVEAU_GEM_RELOC_HIGH (1 << 1) | |
132 | #define NOUVEAU_GEM_RELOC_OR (1 << 2) | |
a1606a95 | 133 | #define NOUVEAU_GEM_MAX_RELOCS 1024 |
6ee73861 | 134 | struct drm_nouveau_gem_pushbuf_reloc { |
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135 | uint32_t reloc_bo_index; |
136 | uint32_t reloc_bo_offset; | |
6ee73861 | 137 | uint32_t bo_index; |
6ee73861 BS |
138 | uint32_t flags; |
139 | uint32_t data; | |
140 | uint32_t vor; | |
141 | uint32_t tor; | |
142 | }; | |
143 | ||
a1606a95 BS |
144 | #define NOUVEAU_GEM_MAX_PUSH 512 |
145 | struct drm_nouveau_gem_pushbuf_push { | |
146 | uint32_t bo_index; | |
147 | uint32_t pad; | |
148 | uint64_t offset; | |
149 | uint64_t length; | |
150 | }; | |
6ee73861 BS |
151 | |
152 | struct drm_nouveau_gem_pushbuf { | |
153 | uint32_t channel; | |
6ee73861 | 154 | uint32_t nr_buffers; |
6ee73861 | 155 | uint64_t buffers; |
6ee73861 | 156 | uint32_t nr_relocs; |
a1606a95 | 157 | uint32_t nr_push; |
6ee73861 | 158 | uint64_t relocs; |
a1606a95 | 159 | uint64_t push; |
6ee73861 BS |
160 | uint32_t suffix0; |
161 | uint32_t suffix1; | |
6ee73861 BS |
162 | uint64_t vram_available; |
163 | uint64_t gart_available; | |
164 | }; | |
165 | ||
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166 | #define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001 |
167 | #define NOUVEAU_GEM_CPU_PREP_NOBLOCK 0x00000002 | |
168 | #define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004 | |
169 | struct drm_nouveau_gem_cpu_prep { | |
170 | uint32_t handle; | |
171 | uint32_t flags; | |
172 | }; | |
173 | ||
174 | struct drm_nouveau_gem_cpu_fini { | |
175 | uint32_t handle; | |
176 | }; | |
177 | ||
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178 | enum nouveau_bus_type { |
179 | NV_AGP = 0, | |
180 | NV_PCI = 1, | |
181 | NV_PCIE = 2, | |
182 | }; | |
183 | ||
184 | struct drm_nouveau_sarea { | |
185 | }; | |
186 | ||
a1606a95 BS |
187 | #define DRM_NOUVEAU_GETPARAM 0x00 |
188 | #define DRM_NOUVEAU_SETPARAM 0x01 | |
189 | #define DRM_NOUVEAU_CHANNEL_ALLOC 0x02 | |
190 | #define DRM_NOUVEAU_CHANNEL_FREE 0x03 | |
191 | #define DRM_NOUVEAU_GROBJ_ALLOC 0x04 | |
192 | #define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05 | |
193 | #define DRM_NOUVEAU_GPUOBJ_FREE 0x06 | |
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194 | #define DRM_NOUVEAU_GEM_NEW 0x40 |
195 | #define DRM_NOUVEAU_GEM_PUSHBUF 0x41 | |
a1606a95 BS |
196 | #define DRM_NOUVEAU_GEM_CPU_PREP 0x42 |
197 | #define DRM_NOUVEAU_GEM_CPU_FINI 0x43 | |
198 | #define DRM_NOUVEAU_GEM_INFO 0x44 | |
6ee73861 BS |
199 | |
200 | #endif /* __NOUVEAU_DRM_H__ */ |