drm/panel: otm8009a: add a 60 fps mode
[linux-block.git] / include / drm / gpu_scheduler.h
CommitLineData
1b1f42d8
LS
1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef _DRM_GPU_SCHEDULER_H_
25#define _DRM_GPU_SCHEDULER_H_
26
27#include <drm/spsc_queue.h>
28#include <linux/dma-fence.h>
dc10218d 29#include <linux/completion.h>
ebd5f742 30#include <linux/xarray.h>
1b1f42d8 31
741f01e6
AG
32#define MAX_WAIT_SCHED_ENTITY_Q_EMPTY msecs_to_jiffies(1000)
33
ebd5f742
DV
34struct drm_gem_object;
35
1b1f42d8
LS
36struct drm_gpu_scheduler;
37struct drm_sched_rq;
38
e2d732fd
LT
39/* These are often used as an (initial) index
40 * to an array, and as such should start at 0.
41 */
1b1f42d8
LS
42enum drm_sched_priority {
43 DRM_SCHED_PRIORITY_MIN,
1b1f42d8 44 DRM_SCHED_PRIORITY_NORMAL,
e2d732fd 45 DRM_SCHED_PRIORITY_HIGH,
1b1f42d8 46 DRM_SCHED_PRIORITY_KERNEL,
e2d732fd
LT
47
48 DRM_SCHED_PRIORITY_COUNT,
1b1f42d8
LS
49 DRM_SCHED_PRIORITY_UNSET = -2
50};
51
52/**
2d33948e
ND
53 * struct drm_sched_entity - A wrapper around a job queue (typically
54 * attached to the DRM file_priv).
55 *
1a61ee07
EA
56 * Entities will emit jobs in order to their corresponding hardware
57 * ring, and the scheduler will alternate between entities based on
58 * scheduling policy.
2d33948e 59 */
1b1f42d8 60struct drm_sched_entity {
981b04d9
DV
61 /**
62 * @list:
63 *
64 * Used to append this struct to the list of entities in the runqueue
65 * @rq under &drm_sched_rq.entities.
66 *
67 * Protected by &drm_sched_rq.lock of @rq.
68 */
1b1f42d8 69 struct list_head list;
981b04d9
DV
70
71 /**
72 * @rq:
73 *
74 * Runqueue on which this entity is currently scheduled.
75 *
76 * FIXME: Locking is very unclear for this. Writers are protected by
77 * @rq_lock, but readers are generally lockless and seem to just race
78 * with not even a READ_ONCE.
79 */
1b1f42d8 80 struct drm_sched_rq *rq;
981b04d9
DV
81
82 /**
83 * @sched_list:
84 *
85 * A list of schedulers (struct drm_gpu_scheduler). Jobs from this entity can
86 * be scheduled on any scheduler on this list.
87 *
88 * This can be modified by calling drm_sched_entity_modify_sched().
89 * Locking is entirely up to the driver, see the above function for more
90 * details.
91 *
92 * This will be set to NULL if &num_sched_list equals 1 and @rq has been
93 * set already.
94 *
95 * FIXME: This means priority changes through
96 * drm_sched_entity_set_priority() will be lost henceforth in this case.
97 */
b3ac1766 98 struct drm_gpu_scheduler **sched_list;
981b04d9
DV
99
100 /**
101 * @num_sched_list:
102 *
103 * Number of drm_gpu_schedulers in the @sched_list.
104 */
9e3e90c5 105 unsigned int num_sched_list;
981b04d9
DV
106
107 /**
108 * @priority:
109 *
110 * Priority of the entity. This can be modified by calling
111 * drm_sched_entity_set_priority(). Protected by &rq_lock.
112 */
b3ac1766 113 enum drm_sched_priority priority;
981b04d9
DV
114
115 /**
116 * @rq_lock:
117 *
118 * Lock to modify the runqueue to which this entity belongs.
119 */
1b1f42d8 120 spinlock_t rq_lock;
1b1f42d8 121
981b04d9
DV
122 /**
123 * @job_queue: the list of jobs of this entity.
124 */
1b1f42d8
LS
125 struct spsc_queue job_queue;
126
981b04d9
DV
127 /**
128 * @fence_seq:
129 *
130 * A linearly increasing seqno incremented with each new
131 * &drm_sched_fence which is part of the entity.
132 *
133 * FIXME: Callers of drm_sched_job_arm() need to ensure correct locking,
134 * this doesn't need to be atomic.
135 */
1b1f42d8 136 atomic_t fence_seq;
981b04d9
DV
137
138 /**
139 * @fence_context:
140 *
141 * A unique context for all the fences which belong to this entity. The
142 * &drm_sched_fence.scheduled uses the fence_context but
143 * &drm_sched_fence.finished uses fence_context + 1.
144 */
1b1f42d8
LS
145 uint64_t fence_context;
146
981b04d9
DV
147 /**
148 * @dependency:
149 *
150 * The dependency fence of the job which is on the top of the job queue.
151 */
1b1f42d8 152 struct dma_fence *dependency;
981b04d9
DV
153
154 /**
155 * @cb:
156 *
157 * Callback for the dependency fence above.
158 */
1b1f42d8 159 struct dma_fence_cb cb;
981b04d9
DV
160
161 /**
162 * @guilty:
163 *
164 * Points to entities' guilty.
165 */
2d33948e 166 atomic_t *guilty;
981b04d9
DV
167
168 /**
169 * @last_scheduled:
170 *
171 * Points to the finished fence of the last scheduled job. Only written
172 * by the scheduler thread, can be accessed locklessly from
173 * drm_sched_job_arm() iff the queue is empty.
174 */
2d33948e 175 struct dma_fence *last_scheduled;
981b04d9
DV
176
177 /**
178 * @last_user: last group leader pushing a job into the entity.
179 */
43bce41c 180 struct task_struct *last_user;
981b04d9
DV
181
182 /**
183 * @stopped:
184 *
185 * Marks the enity as removed from rq and destined for
186 * termination. This is set by calling drm_sched_entity_flush() and by
187 * drm_sched_fini().
188 */
62347a33 189 bool stopped;
981b04d9
DV
190
191 /**
192 * @entity_idle:
193 *
194 * Signals when entity is not in use, used to sequence entity cleanup in
195 * drm_sched_entity_fini().
196 */
83a7772b 197 struct completion entity_idle;
1b1f42d8
LS
198};
199
200/**
2d33948e
ND
201 * struct drm_sched_rq - queue of entities to be scheduled.
202 *
203 * @lock: to modify the entities list.
8dc9fbbf 204 * @sched: the scheduler to which this rq belongs to.
2d33948e
ND
205 * @entities: list of the entities to be scheduled.
206 * @current_entity: the entity which is to be scheduled.
207 *
1b1f42d8
LS
208 * Run queue is a set of entities scheduling command submissions for
209 * one specific ring. It implements the scheduling policy that selects
210 * the next entity to emit commands from.
2d33948e 211 */
1b1f42d8
LS
212struct drm_sched_rq {
213 spinlock_t lock;
8dc9fbbf 214 struct drm_gpu_scheduler *sched;
1b1f42d8
LS
215 struct list_head entities;
216 struct drm_sched_entity *current_entity;
217};
218
2d33948e
ND
219/**
220 * struct drm_sched_fence - fences corresponding to the scheduling of a job.
221 */
1b1f42d8 222struct drm_sched_fence {
2d33948e
ND
223 /**
224 * @scheduled: this fence is what will be signaled by the scheduler
225 * when the job is scheduled.
226 */
1b1f42d8 227 struct dma_fence scheduled;
1a61ee07 228
2d33948e
ND
229 /**
230 * @finished: this fence is what will be signaled by the scheduler
231 * when the job is completed.
232 *
233 * When setting up an out fence for the job, you should use
234 * this, since it's available immediately upon
235 * drm_sched_job_init(), and the fence returned by the driver
236 * from run_job() won't be created until the dependencies have
237 * resolved.
238 */
1b1f42d8 239 struct dma_fence finished;
1a61ee07 240
2d33948e
ND
241 /**
242 * @parent: the fence returned by &drm_sched_backend_ops.run_job
243 * when scheduling the job on hardware. We signal the
244 * &drm_sched_fence.finished fence once parent is signalled.
245 */
1b1f42d8 246 struct dma_fence *parent;
2d33948e
ND
247 /**
248 * @sched: the scheduler instance to which the job having this struct
249 * belongs to.
250 */
1b1f42d8 251 struct drm_gpu_scheduler *sched;
2d33948e
ND
252 /**
253 * @lock: the lock used by the scheduled and the finished fences.
254 */
1b1f42d8 255 spinlock_t lock;
2d33948e
ND
256 /**
257 * @owner: job owner for debugging
258 */
1b1f42d8
LS
259 void *owner;
260};
261
262struct drm_sched_fence *to_drm_sched_fence(struct dma_fence *f);
263
1a61ee07 264/**
2d33948e
ND
265 * struct drm_sched_job - A job to be run by an entity.
266 *
267 * @queue_node: used to append this struct to the queue of jobs in an entity.
c365d304 268 * @list: a job participates in a "pending" and "done" lists.
2d33948e
ND
269 * @sched: the scheduler instance on which this job is scheduled.
270 * @s_fence: contains the fences for the scheduling of job.
271 * @finish_cb: the callback for the finished fence.
2d33948e
ND
272 * @id: a unique id assigned to each job scheduled on the scheduler.
273 * @karma: increment on every hang caused by this job. If this exceeds the hang
274 * limit of the scheduler then the job is marked guilty and will not
275 * be scheduled further.
276 * @s_priority: the priority of the job.
277 * @entity: the entity to which this job belongs.
3741540e 278 * @cb: the callback for the parent fence in s_fence.
1a61ee07
EA
279 *
280 * A job is created by the driver using drm_sched_job_init(), and
281 * should call drm_sched_entity_push_job() once it wants the scheduler
282 * to schedule the job.
283 */
1b1f42d8
LS
284struct drm_sched_job {
285 struct spsc_node queue_node;
8935ff00 286 struct list_head list;
1b1f42d8
LS
287 struct drm_gpu_scheduler *sched;
288 struct drm_sched_fence *s_fence;
289 struct dma_fence_cb finish_cb;
1b1f42d8
LS
290 uint64_t id;
291 atomic_t karma;
292 enum drm_sched_priority s_priority;
8935ff00 293 struct drm_sched_entity *entity;
3741540e 294 struct dma_fence_cb cb;
ebd5f742
DV
295 /**
296 * @dependencies:
297 *
298 * Contains the dependencies as struct dma_fence for this job, see
299 * drm_sched_job_add_dependency() and
300 * drm_sched_job_add_implicit_dependencies().
301 */
302 struct xarray dependencies;
303
304 /** @last_dependency: tracks @dependencies as they signal */
305 unsigned long last_dependency;
1b1f42d8
LS
306};
307
308static inline bool drm_sched_invalidate_job(struct drm_sched_job *s_job,
309 int threshold)
310{
6efa4b46 311 return s_job && atomic_inc_return(&s_job->karma) > threshold;
1b1f42d8
LS
312}
313
a6a1f036
LT
314enum drm_gpu_sched_stat {
315 DRM_GPU_SCHED_STAT_NONE, /* Reserve 0 */
316 DRM_GPU_SCHED_STAT_NOMINAL,
317 DRM_GPU_SCHED_STAT_ENODEV,
318};
319
1b1f42d8 320/**
2d33948e
ND
321 * struct drm_sched_backend_ops
322 *
1b1f42d8 323 * Define the backend operations called by the scheduler,
2d33948e
ND
324 * these functions should be implemented in driver side.
325 */
1b1f42d8 326struct drm_sched_backend_ops {
2d33948e 327 /**
ebd5f742
DV
328 * @dependency:
329 *
330 * Called when the scheduler is considering scheduling this job next, to
331 * get another struct dma_fence for this job to block on. Once it
332 * returns NULL, run_job() may be called.
333 *
334 * If a driver exclusively uses drm_sched_job_add_dependency() and
335 * drm_sched_job_add_implicit_dependencies() this can be ommitted and
336 * left as NULL.
1a61ee07 337 */
1b1f42d8
LS
338 struct dma_fence *(*dependency)(struct drm_sched_job *sched_job,
339 struct drm_sched_entity *s_entity);
1a61ee07 340
2d33948e
ND
341 /**
342 * @run_job: Called to execute the job once all of the dependencies
343 * have been resolved. This may be called multiple times, if
1a61ee07
EA
344 * timedout_job() has happened and drm_sched_job_recovery()
345 * decides to try it again.
346 */
1b1f42d8 347 struct dma_fence *(*run_job)(struct drm_sched_job *sched_job);
1a61ee07 348
2d33948e 349 /**
a6a1f036
LT
350 * @timedout_job: Called when a job has taken too long to execute,
351 * to trigger GPU recovery.
352 *
1fad1b7e
BB
353 * This method is called in a workqueue context.
354 *
355 * Drivers typically issue a reset to recover from GPU hangs, and this
356 * procedure usually follows the following workflow:
357 *
358 * 1. Stop the scheduler using drm_sched_stop(). This will park the
359 * scheduler thread and cancel the timeout work, guaranteeing that
360 * nothing is queued while we reset the hardware queue
361 * 2. Try to gracefully stop non-faulty jobs (optional)
362 * 3. Issue a GPU reset (driver-specific)
363 * 4. Re-submit jobs using drm_sched_resubmit_jobs()
364 * 5. Restart the scheduler using drm_sched_start(). At that point, new
365 * jobs can be queued, and the scheduler thread is unblocked
366 *
78efe21b
BB
367 * Note that some GPUs have distinct hardware queues but need to reset
368 * the GPU globally, which requires extra synchronization between the
369 * timeout handler of the different &drm_gpu_scheduler. One way to
370 * achieve this synchronization is to create an ordered workqueue
371 * (using alloc_ordered_workqueue()) at the driver level, and pass this
372 * queue to drm_sched_init(), to guarantee that timeout handlers are
373 * executed sequentially. The above workflow needs to be slightly
374 * adjusted in that case:
375 *
376 * 1. Stop all schedulers impacted by the reset using drm_sched_stop()
377 * 2. Try to gracefully stop non-faulty jobs on all queues impacted by
378 * the reset (optional)
379 * 3. Issue a GPU reset on all faulty queues (driver-specific)
380 * 4. Re-submit jobs on all schedulers impacted by the reset using
381 * drm_sched_resubmit_jobs()
382 * 5. Restart all schedulers that were stopped in step #1 using
383 * drm_sched_start()
384 *
a6a1f036
LT
385 * Return DRM_GPU_SCHED_STAT_NOMINAL, when all is normal,
386 * and the underlying driver has started or completed recovery.
387 *
388 * Return DRM_GPU_SCHED_STAT_ENODEV, if the device is no longer
389 * available, i.e. has been unplugged.
1a61ee07 390 */
a6a1f036 391 enum drm_gpu_sched_stat (*timedout_job)(struct drm_sched_job *sched_job);
1a61ee07 392
2d33948e
ND
393 /**
394 * @free_job: Called once the job's finished fence has been signaled
395 * and it's time to clean it up.
1a61ee07 396 */
1b1f42d8
LS
397 void (*free_job)(struct drm_sched_job *sched_job);
398};
399
400/**
2d33948e
ND
401 * struct drm_gpu_scheduler
402 *
403 * @ops: backend operations provided by the driver.
404 * @hw_submission_limit: the max size of the hardware queue.
405 * @timeout: the time after which a job is removed from the scheduler.
406 * @name: name of the ring for which this scheduler is being used.
407 * @sched_rq: priority wise array of run queues.
408 * @wake_up_worker: the wait queue on which the scheduler sleeps until a job
409 * is ready to be scheduled.
410 * @job_scheduled: once @drm_sched_entity_do_release is called the scheduler
411 * waits on this wait queue until all the scheduled jobs are
412 * finished.
413 * @hw_rq_count: the number of jobs currently in the hardware queue.
414 * @job_id_count: used to assign unique id to the each job.
78efe21b 415 * @timeout_wq: workqueue used to queue @work_tdr
6a962430
ND
416 * @work_tdr: schedules a delayed call to @drm_sched_job_timedout after the
417 * timeout interval is over.
2d33948e 418 * @thread: the kthread on which the scheduler which run.
6efa4b46
LT
419 * @pending_list: the list of jobs which are currently in the job queue.
420 * @job_list_lock: lock to protect the pending_list.
2d33948e 421 * @hang_limit: once the hangs by a job crosses this limit then it is marked
95b2151f 422 * guilty and it will no longer be considered for scheduling.
d41a39dd 423 * @score: score to help loadbalancer pick a idle sched
be318fd8 424 * @_score: score used when the driver doesn't provide one
faf6e1a8 425 * @ready: marks if the underlying HW is ready to work
a5343b8a 426 * @free_guilty: A hit to time out handler to free the guilty job.
2d33948e
ND
427 *
428 * One scheduler is implemented for each hardware ring.
429 */
1b1f42d8
LS
430struct drm_gpu_scheduler {
431 const struct drm_sched_backend_ops *ops;
432 uint32_t hw_submission_limit;
433 long timeout;
434 const char *name;
e2d732fd 435 struct drm_sched_rq sched_rq[DRM_SCHED_PRIORITY_COUNT];
1b1f42d8
LS
436 wait_queue_head_t wake_up_worker;
437 wait_queue_head_t job_scheduled;
438 atomic_t hw_rq_count;
439 atomic64_t job_id_count;
78efe21b 440 struct workqueue_struct *timeout_wq;
6a962430 441 struct delayed_work work_tdr;
1b1f42d8 442 struct task_struct *thread;
6efa4b46 443 struct list_head pending_list;
1b1f42d8
LS
444 spinlock_t job_list_lock;
445 int hang_limit;
f2f12eb9
CK
446 atomic_t *score;
447 atomic_t _score;
d41a39dd 448 bool ready;
a5343b8a 449 bool free_guilty;
1b1f42d8
LS
450};
451
452int drm_sched_init(struct drm_gpu_scheduler *sched,
453 const struct drm_sched_backend_ops *ops,
78efe21b
BB
454 uint32_t hw_submission, unsigned hang_limit,
455 long timeout, struct workqueue_struct *timeout_wq,
f2f12eb9 456 atomic_t *score, const char *name);
faf6e1a8 457
1b1f42d8 458void drm_sched_fini(struct drm_gpu_scheduler *sched);
620e762f
CK
459int drm_sched_job_init(struct drm_sched_job *job,
460 struct drm_sched_entity *entity,
461 void *owner);
dbe48d03 462void drm_sched_job_arm(struct drm_sched_job *job);
ebd5f742
DV
463int drm_sched_job_add_dependency(struct drm_sched_job *job,
464 struct dma_fence *fence);
465int drm_sched_job_add_implicit_dependencies(struct drm_sched_job *job,
466 struct drm_gem_object *obj,
467 bool write);
468
469
b37aced3
ND
470void drm_sched_entity_modify_sched(struct drm_sched_entity *entity,
471 struct drm_gpu_scheduler **sched_list,
472 unsigned int num_sched_list);
473
26efecf9 474void drm_sched_job_cleanup(struct drm_sched_job *job);
620e762f 475void drm_sched_wakeup(struct drm_gpu_scheduler *sched);
5918045c 476void drm_sched_stop(struct drm_gpu_scheduler *sched, struct drm_sched_job *bad);
222b5f04
AG
477void drm_sched_start(struct drm_gpu_scheduler *sched, bool full_recovery);
478void drm_sched_resubmit_jobs(struct drm_gpu_scheduler *sched);
e6c6338f 479void drm_sched_resubmit_jobs_ext(struct drm_gpu_scheduler *sched, int max);
222b5f04 480void drm_sched_increase_karma(struct drm_sched_job *bad);
e6c6338f
JZ
481void drm_sched_reset_karma(struct drm_sched_job *bad);
482void drm_sched_increase_karma_ext(struct drm_sched_job *bad, int type);
620e762f
CK
483bool drm_sched_dependency_optimized(struct dma_fence* fence,
484 struct drm_sched_entity *entity);
8fe159b0 485void drm_sched_fault(struct drm_gpu_scheduler *sched);
620e762f
CK
486void drm_sched_job_kickout(struct drm_sched_job *s_job);
487
488void drm_sched_rq_add_entity(struct drm_sched_rq *rq,
489 struct drm_sched_entity *entity);
490void drm_sched_rq_remove_entity(struct drm_sched_rq *rq,
491 struct drm_sched_entity *entity);
1b1f42d8 492
aa16b6c6 493int drm_sched_entity_init(struct drm_sched_entity *entity,
b3ac1766
ND
494 enum drm_sched_priority priority,
495 struct drm_gpu_scheduler **sched_list,
9e3e90c5 496 unsigned int num_sched_list,
8344c53f 497 atomic_t *guilty);
cdc50176
ND
498long drm_sched_entity_flush(struct drm_sched_entity *entity, long timeout);
499void drm_sched_entity_fini(struct drm_sched_entity *entity);
500void drm_sched_entity_destroy(struct drm_sched_entity *entity);
620e762f
CK
501void drm_sched_entity_select_rq(struct drm_sched_entity *entity);
502struct drm_sched_job *drm_sched_entity_pop_job(struct drm_sched_entity *entity);
0e10e9a1 503void drm_sched_entity_push_job(struct drm_sched_job *sched_job);
7febe4bf
CK
504void drm_sched_entity_set_priority(struct drm_sched_entity *entity,
505 enum drm_sched_priority priority);
620e762f
CK
506bool drm_sched_entity_is_ready(struct drm_sched_entity *entity);
507
dbe48d03 508struct drm_sched_fence *drm_sched_fence_alloc(
1b1f42d8 509 struct drm_sched_entity *s_entity, void *owner);
dbe48d03
DV
510void drm_sched_fence_init(struct drm_sched_fence *fence,
511 struct drm_sched_entity *entity);
512void drm_sched_fence_free(struct rcu_head *rcu);
513
1b1f42d8
LS
514void drm_sched_fence_scheduled(struct drm_sched_fence *fence);
515void drm_sched_fence_finished(struct drm_sched_fence *fence);
1b1f42d8 516
1db8c142
SM
517unsigned long drm_sched_suspend_timeout(struct drm_gpu_scheduler *sched);
518void drm_sched_resume_timeout(struct drm_gpu_scheduler *sched,
519 unsigned long remaining);
ec2edcc2
ND
520struct drm_gpu_scheduler *
521drm_sched_pick_best(struct drm_gpu_scheduler **sched_list,
522 unsigned int num_sched_list);
1db8c142 523
1b1f42d8 524#endif