[linux-2.6-block.git] / include / drm / drm_mode.h

/*
 * Copyright (c) 2007 Dave Airlie <airlied@linux.ie>
 * Copyright (c) 2007 Jakob Bornecrantz <wallbraker@gmail.com>
 * Copyright (c) 2008 Red Hat Inc.
 * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA
 * Copyright (c) 2007-2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 */

#ifndef _DRM_MODE_H
#define _DRM_MODE_H

#define DRM_DISPLAY_INFO_LEN	32
#define DRM_CONNECTOR_NAME_LEN	32
#define DRM_DISPLAY_MODE_LEN	32
#define DRM_PROP_NAME_LEN	32

#define DRM_MODE_TYPE_BUILTIN	(1<<0)
#define DRM_MODE_TYPE_CLOCK_C	((1<<1) | DRM_MODE_TYPE_BUILTIN)
#define DRM_MODE_TYPE_CRTC_C	((1<<2) | DRM_MODE_TYPE_BUILTIN)
#define DRM_MODE_TYPE_PREFERRED	(1<<3)
#define DRM_MODE_TYPE_DEFAULT	(1<<4)
#define DRM_MODE_TYPE_USERDEF	(1<<5)
#define DRM_MODE_TYPE_DRIVER	(1<<6)

/* Video mode flags */
/* bit compatible with the xorg definitions. */
#define DRM_MODE_FLAG_PHSYNC	(1<<0)
#define DRM_MODE_FLAG_NHSYNC	(1<<1)
#define DRM_MODE_FLAG_PVSYNC	(1<<2)
#define DRM_MODE_FLAG_NVSYNC	(1<<3)
#define DRM_MODE_FLAG_INTERLACE	(1<<4)
#define DRM_MODE_FLAG_DBLSCAN	(1<<5)
#define DRM_MODE_FLAG_CSYNC	(1<<6)
#define DRM_MODE_FLAG_PCSYNC	(1<<7)
#define DRM_MODE_FLAG_NCSYNC	(1<<8)
#define DRM_MODE_FLAG_HSKEW	(1<<9) /* hskew provided */
#define DRM_MODE_FLAG_BCAST	(1<<10)
#define DRM_MODE_FLAG_PIXMUX	(1<<11)
#define DRM_MODE_FLAG_DBLCLK	(1<<12)
#define DRM_MODE_FLAG_CLKDIV2	(1<<13)

/* DPMS flags */
/* bit compatible with the xorg definitions. */
#define DRM_MODE_DPMS_ON	0
#define DRM_MODE_DPMS_STANDBY	1
#define DRM_MODE_DPMS_SUSPEND	2
#define DRM_MODE_DPMS_OFF	3

/* Scaling mode options */
#define DRM_MODE_SCALE_NONE		0 /* Unmodified timing (display or
					     software can still scale) */
#define DRM_MODE_SCALE_FULLSCREEN	1 /* Full screen, ignore aspect */
#define DRM_MODE_SCALE_CENTER		2 /* Centered, no scaling */
#define DRM_MODE_SCALE_ASPECT		3 /* Full screen, preserve aspect */

/* Dithering mode options */
#define DRM_MODE_DITHERING_OFF	0
#define DRM_MODE_DITHERING_ON	1

/* Dirty info options */
#define DRM_MODE_DIRTY_OFF      0
#define DRM_MODE_DIRTY_ON       1
#define DRM_MODE_DIRTY_ANNOTATE 2

struct drm_mode_modeinfo {
	__u32 clock;
	__u16 hdisplay, hsync_start, hsync_end, htotal, hskew;
	__u16 vdisplay, vsync_start, vsync_end, vtotal, vscan;

	__u32 vrefresh; /* vertical refresh * 1000 */

	__u32 flags;
	__u32 type;
	char name[DRM_DISPLAY_MODE_LEN];
};

struct drm_mode_card_res {
	__u64 fb_id_ptr;
	__u64 crtc_id_ptr;
	__u64 connector_id_ptr;
	__u64 encoder_id_ptr;
	__u32 count_fbs;
	__u32 count_crtcs;
	__u32 count_connectors;
	__u32 count_encoders;
	__u32 min_width, max_width;
	__u32 min_height, max_height;
};

struct drm_mode_crtc {
	__u64 set_connectors_ptr;
	__u32 count_connectors;

	__u32 crtc_id; /**< Id */
	__u32 fb_id; /**< Id of framebuffer */

	__u32 x, y; /**< Position on the frameuffer */

	__u32 gamma_size;
	__u32 mode_valid;
	struct drm_mode_modeinfo mode;
};

#define DRM_MODE_ENCODER_NONE	0
#define DRM_MODE_ENCODER_DAC	1
#define DRM_MODE_ENCODER_TMDS	2
#define DRM_MODE_ENCODER_LVDS	3
#define DRM_MODE_ENCODER_TVDAC	4

struct drm_mode_get_encoder {
	__u32 encoder_id;
	__u32 encoder_type;

	__u32 crtc_id; /**< Id of crtc */

	__u32 possible_crtcs;
	__u32 possible_clones;
};

/* This is for connectors with multiple signal types. */
/* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */
#define DRM_MODE_SUBCONNECTOR_Automatic	0
#define DRM_MODE_SUBCONNECTOR_Unknown	0
#define DRM_MODE_SUBCONNECTOR_DVID	3
#define DRM_MODE_SUBCONNECTOR_DVIA	4
#define DRM_MODE_SUBCONNECTOR_Composite	5
#define DRM_MODE_SUBCONNECTOR_SVIDEO	6
#define DRM_MODE_SUBCONNECTOR_Component	8
#define DRM_MODE_SUBCONNECTOR_SCART	9

#define DRM_MODE_CONNECTOR_Unknown	0
#define DRM_MODE_CONNECTOR_VGA		1
#define DRM_MODE_CONNECTOR_DVII		2
#define DRM_MODE_CONNECTOR_DVID		3
#define DRM_MODE_CONNECTOR_DVIA		4
#define DRM_MODE_CONNECTOR_Composite	5
#define DRM_MODE_CONNECTOR_SVIDEO	6
#define DRM_MODE_CONNECTOR_LVDS		7
#define DRM_MODE_CONNECTOR_Component	8
#define DRM_MODE_CONNECTOR_9PinDIN	9
#define DRM_MODE_CONNECTOR_DisplayPort	10
#define DRM_MODE_CONNECTOR_HDMIA	11
#define DRM_MODE_CONNECTOR_HDMIB	12
#define DRM_MODE_CONNECTOR_TV		13
#define DRM_MODE_CONNECTOR_eDP		14

struct drm_mode_get_connector {

	__u64 encoders_ptr;
	__u64 modes_ptr;
	__u64 props_ptr;
	__u64 prop_values_ptr;

	__u32 count_modes;
	__u32 count_props;
	__u32 count_encoders;

	__u32 encoder_id; /**< Current Encoder */
	__u32 connector_id; /**< Id */
	__u32 connector_type;
	__u32 connector_type_id;

	__u32 connection;
	__u32 mm_width, mm_height; /**< HxW in millimeters */
	__u32 subpixel;
};

#define DRM_MODE_PROP_PENDING	(1<<0)
#define DRM_MODE_PROP_RANGE	(1<<1)
#define DRM_MODE_PROP_IMMUTABLE	(1<<2)
#define DRM_MODE_PROP_ENUM	(1<<3) /* enumerated type with text strings */
#define DRM_MODE_PROP_BLOB	(1<<4)

struct drm_mode_property_enum {
	__u64 value;
	char name[DRM_PROP_NAME_LEN];
};

struct drm_mode_get_property {
	__u64 values_ptr; /* values and blob lengths */
	__u64 enum_blob_ptr; /* enum and blob id ptrs */

	__u32 prop_id;
	__u32 flags;
	char name[DRM_PROP_NAME_LEN];

	__u32 count_values;
	__u32 count_enum_blobs;
};

struct drm_mode_connector_set_property {
	__u64 value;
	__u32 prop_id;
	__u32 connector_id;
};

struct drm_mode_get_blob {
	__u32 blob_id;
	__u32 length;
	__u64 data;
};

struct drm_mode_fb_cmd {
	__u32 fb_id;
	__u32 width, height;
	__u32 pitch;
	__u32 bpp;
	__u32 depth;
	/* driver specific handle */
	__u32 handle;
};

#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01
#define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02
#define DRM_MODE_FB_DIRTY_FLAGS         0x03

/*
 * Mark a region of a framebuffer as dirty.
 *
 * Some hardware does not automatically update display contents
 * as a hardware or software draw to a framebuffer. This ioctl
 * allows userspace to tell the kernel and the hardware what
 * regions of the framebuffer have changed.
 *
 * The kernel or hardware is free to update more then just the
 * region specified by the clip rects. The kernel or hardware
 * may also delay and/or coalesce several calls to dirty into a
 * single update.
 *
 * Userspace may annotate the updates, the annotates are a
 * promise made by the caller that the change is either a copy
 * of pixels or a fill of a single color in the region specified.
 *
 * If the DRM_MODE_FB_DIRTY_ANNOTATE_COPY flag is given then
 * the number of updated regions are half of num_clips given,
 * where the clip rects are paired in src and dst. The width and
 * height of each one of the pairs must match.
 *
 * If the DRM_MODE_FB_DIRTY_ANNOTATE_FILL flag is given the caller
 * promises that the region specified of the clip rects is filled
 * completely with a single color as given in the color argument.
 */

struct drm_mode_fb_dirty_cmd {
	__u32 fb_id;
	__u32 flags;
	__u32 color;
	__u32 num_clips;
	__u64 clips_ptr;
};

struct drm_mode_mode_cmd {
	__u32 connector_id;
	struct drm_mode_modeinfo mode;
};

#define DRM_MODE_CURSOR_BO	(1<<0)
#define DRM_MODE_CURSOR_MOVE	(1<<1)

/*
 * depending on the value in flags diffrent members are used.
 *
 * CURSOR_BO uses
 *    crtc
 *    width
 *    height
 *    handle - if 0 turns the cursor of
 *
 * CURSOR_MOVE uses
 *    crtc
 *    x
 *    y
 */
struct drm_mode_cursor {
	__u32 flags;
	__u32 crtc_id;
	__s32 x;
	__s32 y;
	__u32 width;
	__u32 height;
	/* driver specific handle */
	__u32 handle;
};

struct drm_mode_crtc_lut {
	__u32 crtc_id;
	__u32 gamma_size;

	/* pointers to arrays */
	__u64 red;
	__u64 green;
	__u64 blue;
};

#define DRM_MODE_PAGE_FLIP_EVENT 0x01
#define DRM_MODE_PAGE_FLIP_FLAGS DRM_MODE_PAGE_FLIP_EVENT

/*
 * Request a page flip on the specified crtc.
 *
 * This ioctl will ask KMS to schedule a page flip for the specified
 * crtc.  Once any pending rendering targeting the specified fb (as of
 * ioctl time) has completed, the crtc will be reprogrammed to display
 * that fb after the next vertical refresh.  The ioctl returns
 * immediately, but subsequent rendering to the current fb will block
 * in the execbuffer ioctl until the page flip happens.  If a page
 * flip is already pending as the ioctl is called, EBUSY will be
 * returned.
 *
 * The ioctl supports one flag, DRM_MODE_PAGE_FLIP_EVENT, which will
 * request that drm sends back a vblank event (see drm.h: struct
 * drm_event_vblank) when the page flip is done.  The user_data field
 * passed in with this ioctl will be returned as the user_data field
 * in the vblank event struct.
 *
 * The reserved field must be zero until we figure out something
 * clever to use it for.
 */

struct drm_mode_crtc_page_flip {
	__u32 crtc_id;
	__u32 fb_id;
	__u32 flags;
	__u32 reserved;
	__u64 user_data;
};

#endif
Commit	Line	Data
f453ba04 DA	1	/*
	2	* Copyright (c) 2007 Dave Airlie <airlied@linux.ie>
	3	* Copyright (c) 2007 Jakob Bornecrantz <wallbraker@gmail.com>
	4	* Copyright (c) 2008 Red Hat Inc.
	5	* Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA
	6	* Copyright (c) 2007-2008 Intel Corporation
	7	*
	8	* Permission is hereby granted, free of charge, to any person obtaining a
	9	* copy of this software and associated documentation files (the "Software"),
	10	* to deal in the Software without restriction, including without limitation
	11	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	12	* and/or sell copies of the Software, and to permit persons to whom the
	13	* Software is furnished to do so, subject to the following conditions:
	14	*
	15	* The above copyright notice and this permission notice shall be included in
	16	* all copies or substantial portions of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	20	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
	21	* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	22	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	23	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	24	* IN THE SOFTWARE.
	25	*/
	26
	27	#ifndef _DRM_MODE_H
	28	#define _DRM_MODE_H
	29
e0c8463a JB	30	#define DRM_DISPLAY_INFO_LEN 32
	31	#define DRM_CONNECTOR_NAME_LEN 32
	32	#define DRM_DISPLAY_MODE_LEN 32
	33	#define DRM_PROP_NAME_LEN 32
f453ba04 DA	34
	35	#define DRM_MODE_TYPE_BUILTIN (1<<0)
	36	#define DRM_MODE_TYPE_CLOCK_C ((1<<1) \| DRM_MODE_TYPE_BUILTIN)
	37	#define DRM_MODE_TYPE_CRTC_C ((1<<2) \| DRM_MODE_TYPE_BUILTIN)
	38	#define DRM_MODE_TYPE_PREFERRED (1<<3)
	39	#define DRM_MODE_TYPE_DEFAULT (1<<4)
	40	#define DRM_MODE_TYPE_USERDEF (1<<5)
	41	#define DRM_MODE_TYPE_DRIVER (1<<6)
	42
	43	/* Video mode flags */
	44	/* bit compatible with the xorg definitions. */
	45	#define DRM_MODE_FLAG_PHSYNC (1<<0)
	46	#define DRM_MODE_FLAG_NHSYNC (1<<1)
	47	#define DRM_MODE_FLAG_PVSYNC (1<<2)
	48	#define DRM_MODE_FLAG_NVSYNC (1<<3)
	49	#define DRM_MODE_FLAG_INTERLACE (1<<4)
	50	#define DRM_MODE_FLAG_DBLSCAN (1<<5)
	51	#define DRM_MODE_FLAG_CSYNC (1<<6)
	52	#define DRM_MODE_FLAG_PCSYNC (1<<7)
	53	#define DRM_MODE_FLAG_NCSYNC (1<<8)
	54	#define DRM_MODE_FLAG_HSKEW (1<<9) /* hskew provided */
	55	#define DRM_MODE_FLAG_BCAST (1<<10)
	56	#define DRM_MODE_FLAG_PIXMUX (1<<11)
	57	#define DRM_MODE_FLAG_DBLCLK (1<<12)
	58	#define DRM_MODE_FLAG_CLKDIV2 (1<<13)
	59
	60	/* DPMS flags */
	61	/* bit compatible with the xorg definitions. */
e0c8463a JB	62	#define DRM_MODE_DPMS_ON 0
	63	#define DRM_MODE_DPMS_STANDBY 1
	64	#define DRM_MODE_DPMS_SUSPEND 2
	65	#define DRM_MODE_DPMS_OFF 3
f453ba04 DA	66
f453ba04 DA	67	/* Scaling mode options */
53bd8389 JB	68	#define DRM_MODE_SCALE_NONE 0 /* Unmodified timing (display or
	69	software can still scale) */
	70	#define DRM_MODE_SCALE_FULLSCREEN 1 /* Full screen, ignore aspect */
	71	#define DRM_MODE_SCALE_CENTER 2 /* Centered, no scaling */
	72	#define DRM_MODE_SCALE_ASPECT 3 /* Full screen, preserve aspect */
f453ba04 DA	73
f453ba04 DA	74	/* Dithering mode options */
e0c8463a JB	75	#define DRM_MODE_DITHERING_OFF 0
e0c8463a JB	76	#define DRM_MODE_DITHERING_ON 1
f453ba04	77
884840aa JB	78	/* Dirty info options */
	79	#define DRM_MODE_DIRTY_OFF 0
	80	#define DRM_MODE_DIRTY_ON 1
	81	#define DRM_MODE_DIRTY_ANNOTATE 2
	82
f453ba04	83	struct drm_mode_modeinfo {
1d7f83d5 AB	84	__u32 clock;
	85	__u16 hdisplay, hsync_start, hsync_end, htotal, hskew;
	86	__u16 vdisplay, vsync_start, vsync_end, vtotal, vscan;
f453ba04	87
1d7f83d5	88	__u32 vrefresh; /* vertical refresh * 1000 */
f453ba04	89
1d7f83d5 AB	90	__u32 flags;
1d7f83d5 AB	91	__u32 type;
f453ba04 DA	92	char name[DRM_DISPLAY_MODE_LEN];
	93	};
	94
	95	struct drm_mode_card_res {
1d7f83d5 AB	96	__u64 fb_id_ptr;
	97	__u64 crtc_id_ptr;
	98	__u64 connector_id_ptr;
	99	__u64 encoder_id_ptr;
	100	__u32 count_fbs;
	101	__u32 count_crtcs;
	102	__u32 count_connectors;
	103	__u32 count_encoders;
	104	__u32 min_width, max_width;
	105	__u32 min_height, max_height;
f453ba04 DA	106	};
	107
	108	struct drm_mode_crtc {
1d7f83d5 AB	109	__u64 set_connectors_ptr;
1d7f83d5 AB	110	__u32 count_connectors;
f453ba04	111
1d7f83d5 AB	112	__u32 crtc_id; /*< Id /
1d7f83d5 AB	113	__u32 fb_id; /*< Id of framebuffer /
f453ba04	114
1d7f83d5	115	__u32 x, y; /*< Position on the frameuffer /
f453ba04	116
1d7f83d5 AB	117	__u32 gamma_size;
1d7f83d5 AB	118	__u32 mode_valid;
f453ba04 DA	119	struct drm_mode_modeinfo mode;
	120	};
	121
e0c8463a JB	122	#define DRM_MODE_ENCODER_NONE 0
	123	#define DRM_MODE_ENCODER_DAC 1
	124	#define DRM_MODE_ENCODER_TMDS 2
	125	#define DRM_MODE_ENCODER_LVDS 3
	126	#define DRM_MODE_ENCODER_TVDAC 4
f453ba04 DA	127
f453ba04 DA	128	struct drm_mode_get_encoder {
1d7f83d5 AB	129	__u32 encoder_id;
1d7f83d5 AB	130	__u32 encoder_type;
f453ba04	131
1d7f83d5	132	__u32 crtc_id; /*< Id of crtc /
f453ba04	133
1d7f83d5 AB	134	__u32 possible_crtcs;
1d7f83d5 AB	135	__u32 possible_clones;
f453ba04 DA	136	};
	137
	138	/* This is for connectors with multiple signal types. */
	139	/* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */
e0c8463a JB	140	#define DRM_MODE_SUBCONNECTOR_Automatic 0
	141	#define DRM_MODE_SUBCONNECTOR_Unknown 0
	142	#define DRM_MODE_SUBCONNECTOR_DVID 3
	143	#define DRM_MODE_SUBCONNECTOR_DVIA 4
	144	#define DRM_MODE_SUBCONNECTOR_Composite 5
	145	#define DRM_MODE_SUBCONNECTOR_SVIDEO 6
	146	#define DRM_MODE_SUBCONNECTOR_Component 8
aeaa1ad3	147	#define DRM_MODE_SUBCONNECTOR_SCART 9
e0c8463a JB	148
	149	#define DRM_MODE_CONNECTOR_Unknown 0
	150	#define DRM_MODE_CONNECTOR_VGA 1
	151	#define DRM_MODE_CONNECTOR_DVII 2
	152	#define DRM_MODE_CONNECTOR_DVID 3
	153	#define DRM_MODE_CONNECTOR_DVIA 4
	154	#define DRM_MODE_CONNECTOR_Composite 5
	155	#define DRM_MODE_CONNECTOR_SVIDEO 6
	156	#define DRM_MODE_CONNECTOR_LVDS 7
	157	#define DRM_MODE_CONNECTOR_Component 8
	158	#define DRM_MODE_CONNECTOR_9PinDIN 9
	159	#define DRM_MODE_CONNECTOR_DisplayPort 10
	160	#define DRM_MODE_CONNECTOR_HDMIA 11
	161	#define DRM_MODE_CONNECTOR_HDMIB 12
74bd3c26	162	#define DRM_MODE_CONNECTOR_TV 13
7970e677	163	#define DRM_MODE_CONNECTOR_eDP 14
f453ba04 DA	164
	165	struct drm_mode_get_connector {
	166
1d7f83d5 AB	167	__u64 encoders_ptr;
	168	__u64 modes_ptr;
	169	__u64 props_ptr;
	170	__u64 prop_values_ptr;
f453ba04	171
1d7f83d5 AB	172	__u32 count_modes;
	173	__u32 count_props;
	174	__u32 count_encoders;
f453ba04	175
1d7f83d5 AB	176	__u32 encoder_id; /*< Current Encoder /
	177	__u32 connector_id; /*< Id /
	178	__u32 connector_type;
	179	__u32 connector_type_id;
f453ba04	180
1d7f83d5 AB	181	__u32 connection;
	182	__u32 mm_width, mm_height; /*< HxW in millimeters /
	183	__u32 subpixel;
f453ba04 DA	184	};
f453ba04 DA	185
e0c8463a JB	186	#define DRM_MODE_PROP_PENDING (1<<0)
	187	#define DRM_MODE_PROP_RANGE (1<<1)
	188	#define DRM_MODE_PROP_IMMUTABLE (1<<2)
	189	#define DRM_MODE_PROP_ENUM (1<<3) /* enumerated type with text strings */
	190	#define DRM_MODE_PROP_BLOB (1<<4)
f453ba04 DA	191
f453ba04 DA	192	struct drm_mode_property_enum {
1d7f83d5	193	__u64 value;
e0c8463a	194	char name[DRM_PROP_NAME_LEN];
f453ba04 DA	195	};
	196
	197	struct drm_mode_get_property {
1d7f83d5 AB	198	__u64 values_ptr; /* values and blob lengths */
1d7f83d5 AB	199	__u64 enum_blob_ptr; /* enum and blob id ptrs */
f453ba04	200
1d7f83d5 AB	201	__u32 prop_id;
1d7f83d5 AB	202	__u32 flags;
e0c8463a	203	char name[DRM_PROP_NAME_LEN];
f453ba04	204
1d7f83d5 AB	205	__u32 count_values;
1d7f83d5 AB	206	__u32 count_enum_blobs;
f453ba04 DA	207	};
	208
	209	struct drm_mode_connector_set_property {
1d7f83d5 AB	210	__u64 value;
	211	__u32 prop_id;
	212	__u32 connector_id;
f453ba04 DA	213	};
	214
	215	struct drm_mode_get_blob {
1d7f83d5 AB	216	__u32 blob_id;
	217	__u32 length;
	218	__u64 data;
f453ba04 DA	219	};
	220
	221	struct drm_mode_fb_cmd {
1d7f83d5 AB	222	__u32 fb_id;
	223	__u32 width, height;
	224	__u32 pitch;
	225	__u32 bpp;
	226	__u32 depth;
e0c8463a	227	/* driver specific handle */
1d7f83d5	228	__u32 handle;
f453ba04 DA	229	};
f453ba04 DA	230
884840aa JB	231	#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01
	232	#define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02
	233	#define DRM_MODE_FB_DIRTY_FLAGS 0x03
	234
	235	/*
	236	* Mark a region of a framebuffer as dirty.
	237	*
	238	* Some hardware does not automatically update display contents
	239	* as a hardware or software draw to a framebuffer. This ioctl
	240	* allows userspace to tell the kernel and the hardware what
	241	* regions of the framebuffer have changed.
	242	*
	243	* The kernel or hardware is free to update more then just the
	244	* region specified by the clip rects. The kernel or hardware
	245	* may also delay and/or coalesce several calls to dirty into a
	246	* single update.
	247	*
	248	* Userspace may annotate the updates, the annotates are a
	249	* promise made by the caller that the change is either a copy
	250	* of pixels or a fill of a single color in the region specified.
	251	*
	252	* If the DRM_MODE_FB_DIRTY_ANNOTATE_COPY flag is given then
	253	* the number of updated regions are half of num_clips given,
	254	* where the clip rects are paired in src and dst. The width and
	255	* height of each one of the pairs must match.
	256	*
	257	* If the DRM_MODE_FB_DIRTY_ANNOTATE_FILL flag is given the caller
	258	* promises that the region specified of the clip rects is filled
	259	* completely with a single color as given in the color argument.
	260	*/
	261
	262	struct drm_mode_fb_dirty_cmd {
	263	__u32 fb_id;
	264	__u32 flags;
	265	__u32 color;
	266	__u32 num_clips;
	267	__u64 clips_ptr;
	268	};
	269
f453ba04	270	struct drm_mode_mode_cmd {
1d7f83d5	271	__u32 connector_id;
f453ba04 DA	272	struct drm_mode_modeinfo mode;
	273	};
	274
e0c8463a JB	275	#define DRM_MODE_CURSOR_BO (1<<0)
e0c8463a JB	276	#define DRM_MODE_CURSOR_MOVE (1<<1)
f453ba04 DA	277
	278	/*
	279	* depending on the value in flags diffrent members are used.
	280	*
	281	* CURSOR_BO uses
	282	* crtc
	283	* width
	284	* height
	285	* handle - if 0 turns the cursor of
	286	*
	287	* CURSOR_MOVE uses
	288	* crtc
	289	* x
	290	* y
	291	*/
	292	struct drm_mode_cursor {
1d7f83d5 AB	293	__u32 flags;
	294	__u32 crtc_id;
	295	__s32 x;
	296	__s32 y;
	297	__u32 width;
	298	__u32 height;
e0c8463a	299	/* driver specific handle */
1d7f83d5	300	__u32 handle;
f453ba04 DA	301	};
	302
	303	struct drm_mode_crtc_lut {
1d7f83d5 AB	304	__u32 crtc_id;
1d7f83d5 AB	305	__u32 gamma_size;
f453ba04 DA	306
f453ba04 DA	307	/* pointers to arrays */
1d7f83d5 AB	308	__u64 red;
	309	__u64 green;
	310	__u64 blue;
f453ba04 DA	311	};
f453ba04 DA	312
d91d8a3f KH	313	#define DRM_MODE_PAGE_FLIP_EVENT 0x01
	314	#define DRM_MODE_PAGE_FLIP_FLAGS DRM_MODE_PAGE_FLIP_EVENT
	315
	316	/*
	317	* Request a page flip on the specified crtc.
	318	*
	319	* This ioctl will ask KMS to schedule a page flip for the specified
	320	* crtc. Once any pending rendering targeting the specified fb (as of
	321	* ioctl time) has completed, the crtc will be reprogrammed to display
	322	* that fb after the next vertical refresh. The ioctl returns
	323	* immediately, but subsequent rendering to the current fb will block
	324	* in the execbuffer ioctl until the page flip happens. If a page
	325	* flip is already pending as the ioctl is called, EBUSY will be
	326	* returned.
	327	*
	328	* The ioctl supports one flag, DRM_MODE_PAGE_FLIP_EVENT, which will
	329	* request that drm sends back a vblank event (see drm.h: struct
	330	* drm_event_vblank) when the page flip is done. The user_data field
	331	* passed in with this ioctl will be returned as the user_data field
	332	* in the vblank event struct.
	333	*
	334	* The reserved field must be zero until we figure out something
	335	* clever to use it for.
	336	*/
	337
	338	struct drm_mode_crtc_page_flip {
	339	__u32 crtc_id;
	340	__u32 fb_id;
	341	__u32 flags;
	342	__u32 reserved;
	343	__u64 user_data;
	344	};
	345
f453ba04	346	#endif