[linux-block.git] / include / drm / drm_edid.h

/*
 * Copyright © 2007-2008 Intel Corporation
 *   Jesse Barnes <jesse.barnes@intel.com>
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 */
#ifndef __DRM_EDID_H__
#define __DRM_EDID_H__

#include <linux/types.h>
#include <linux/hdmi.h>
#include <drm/drm_mode.h>

struct drm_device;
struct i2c_adapter;

#define EDID_LENGTH 128
#define DDC_ADDR 0x50
#define DDC_ADDR2 0x52 /* E-DDC 1.2 - where DisplayID can hide */

#define CEA_EXT	    0x02
#define VTB_EXT	    0x10
#define DI_EXT	    0x40
#define LS_EXT	    0x50
#define MI_EXT	    0x60
#define DISPLAYID_EXT 0x70

struct est_timings {
	u8 t1;
	u8 t2;
	u8 mfg_rsvd;
} __attribute__((packed));

/* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */
#define EDID_TIMING_ASPECT_SHIFT 6
#define EDID_TIMING_ASPECT_MASK  (0x3 << EDID_TIMING_ASPECT_SHIFT)

/* need to add 60 */
#define EDID_TIMING_VFREQ_SHIFT  0
#define EDID_TIMING_VFREQ_MASK   (0x3f << EDID_TIMING_VFREQ_SHIFT)

struct std_timing {
	u8 hsize; /* need to multiply by 8 then add 248 */
	u8 vfreq_aspect;
} __attribute__((packed));

#define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1)
#define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2)
#define DRM_EDID_PT_SEPARATE_SYNC  (3 << 3)
#define DRM_EDID_PT_STEREO         (1 << 5)
#define DRM_EDID_PT_INTERLACED     (1 << 7)

/* If detailed data is pixel timing */
struct detailed_pixel_timing {
	u8 hactive_lo;
	u8 hblank_lo;
	u8 hactive_hblank_hi;
	u8 vactive_lo;
	u8 vblank_lo;
	u8 vactive_vblank_hi;
	u8 hsync_offset_lo;
	u8 hsync_pulse_width_lo;
	u8 vsync_offset_pulse_width_lo;
	u8 hsync_vsync_offset_pulse_width_hi;
	u8 width_mm_lo;
	u8 height_mm_lo;
	u8 width_height_mm_hi;
	u8 hborder;
	u8 vborder;
	u8 misc;
} __attribute__((packed));

/* If it's not pixel timing, it'll be one of the below */
struct detailed_data_string {
	u8 str[13];
} __attribute__((packed));

#define DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG   0x00
#define DRM_EDID_RANGE_LIMITS_ONLY_FLAG     0x01
#define DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG 0x02
#define DRM_EDID_CVT_SUPPORT_FLAG           0x04

struct detailed_data_monitor_range {
	u8 min_vfreq;
	u8 max_vfreq;
	u8 min_hfreq_khz;
	u8 max_hfreq_khz;
	u8 pixel_clock_mhz; /* need to multiply by 10 */
	u8 flags;
	union {
		struct {
			u8 reserved;
			u8 hfreq_start_khz; /* need to multiply by 2 */
			u8 c; /* need to divide by 2 */
			__le16 m;
			u8 k;
			u8 j; /* need to divide by 2 */
		} __attribute__((packed)) gtf2;
		struct {
			u8 version;
			u8 data1; /* high 6 bits: extra clock resolution */
			u8 data2; /* plus low 2 of above: max hactive */
			u8 supported_aspects;
			u8 flags; /* preferred aspect and blanking support */
			u8 supported_scalings;
			u8 preferred_refresh;
		} __attribute__((packed)) cvt;
	} formula;
} __attribute__((packed));

struct detailed_data_wpindex {
	u8 white_yx_lo; /* Lower 2 bits each */
	u8 white_x_hi;
	u8 white_y_hi;
	u8 gamma; /* need to divide by 100 then add 1 */
} __attribute__((packed));

struct detailed_data_color_point {
	u8 windex1;
	u8 wpindex1[3];
	u8 windex2;
	u8 wpindex2[3];
} __attribute__((packed));

struct cvt_timing {
	u8 code[3];
} __attribute__((packed));

struct detailed_non_pixel {
	u8 pad1;
	u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name
		    fb=color point data, fa=standard timing data,
		    f9=undefined, f8=mfg. reserved */
	u8 pad2;
	union {
		struct detailed_data_string str;
		struct detailed_data_monitor_range range;
		struct detailed_data_wpindex color;
		struct std_timing timings[6];
		struct cvt_timing cvt[4];
	} data;
} __attribute__((packed));

#define EDID_DETAIL_EST_TIMINGS 0xf7
#define EDID_DETAIL_CVT_3BYTE 0xf8
#define EDID_DETAIL_COLOR_MGMT_DATA 0xf9
#define EDID_DETAIL_STD_MODES 0xfa
#define EDID_DETAIL_MONITOR_CPDATA 0xfb
#define EDID_DETAIL_MONITOR_NAME 0xfc
#define EDID_DETAIL_MONITOR_RANGE 0xfd
#define EDID_DETAIL_MONITOR_STRING 0xfe
#define EDID_DETAIL_MONITOR_SERIAL 0xff

struct detailed_timing {
	__le16 pixel_clock; /* need to multiply by 10 KHz */
	union {
		struct detailed_pixel_timing pixel_data;
		struct detailed_non_pixel other_data;
	} data;
} __attribute__((packed));

#define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0)
#define DRM_EDID_INPUT_SYNC_ON_GREEN   (1 << 1)
#define DRM_EDID_INPUT_COMPOSITE_SYNC  (1 << 2)
#define DRM_EDID_INPUT_SEPARATE_SYNCS  (1 << 3)
#define DRM_EDID_INPUT_BLANK_TO_BLACK  (1 << 4)
#define DRM_EDID_INPUT_VIDEO_LEVEL     (3 << 5)
#define DRM_EDID_INPUT_DIGITAL         (1 << 7)
#define DRM_EDID_DIGITAL_DEPTH_MASK    (7 << 4) /* 1.4 */
#define DRM_EDID_DIGITAL_DEPTH_UNDEF   (0 << 4) /* 1.4 */
#define DRM_EDID_DIGITAL_DEPTH_6       (1 << 4) /* 1.4 */
#define DRM_EDID_DIGITAL_DEPTH_8       (2 << 4) /* 1.4 */
#define DRM_EDID_DIGITAL_DEPTH_10      (3 << 4) /* 1.4 */
#define DRM_EDID_DIGITAL_DEPTH_12      (4 << 4) /* 1.4 */
#define DRM_EDID_DIGITAL_DEPTH_14      (5 << 4) /* 1.4 */
#define DRM_EDID_DIGITAL_DEPTH_16      (6 << 4) /* 1.4 */
#define DRM_EDID_DIGITAL_DEPTH_RSVD    (7 << 4) /* 1.4 */
#define DRM_EDID_DIGITAL_TYPE_MASK     (7 << 0) /* 1.4 */
#define DRM_EDID_DIGITAL_TYPE_UNDEF    (0 << 0) /* 1.4 */
#define DRM_EDID_DIGITAL_TYPE_DVI      (1 << 0) /* 1.4 */
#define DRM_EDID_DIGITAL_TYPE_HDMI_A   (2 << 0) /* 1.4 */
#define DRM_EDID_DIGITAL_TYPE_HDMI_B   (3 << 0) /* 1.4 */
#define DRM_EDID_DIGITAL_TYPE_MDDI     (4 << 0) /* 1.4 */
#define DRM_EDID_DIGITAL_TYPE_DP       (5 << 0) /* 1.4 */
#define DRM_EDID_DIGITAL_DFP_1_X       (1 << 0) /* 1.3 */

#define DRM_EDID_FEATURE_DEFAULT_GTF      (1 << 0)
#define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1)
#define DRM_EDID_FEATURE_STANDARD_COLOR   (1 << 2)
/* If analog */
#define DRM_EDID_FEATURE_DISPLAY_TYPE     (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */
/* If digital */
#define DRM_EDID_FEATURE_COLOR_MASK	  (3 << 3)
#define DRM_EDID_FEATURE_RGB		  (0 << 3)
#define DRM_EDID_FEATURE_RGB_YCRCB444	  (1 << 3)
#define DRM_EDID_FEATURE_RGB_YCRCB422	  (2 << 3)
#define DRM_EDID_FEATURE_RGB_YCRCB	  (3 << 3) /* both 4:4:4 and 4:2:2 */

#define DRM_EDID_FEATURE_PM_ACTIVE_OFF    (1 << 5)
#define DRM_EDID_FEATURE_PM_SUSPEND       (1 << 6)
#define DRM_EDID_FEATURE_PM_STANDBY       (1 << 7)

#define DRM_EDID_HDMI_DC_48               (1 << 6)
#define DRM_EDID_HDMI_DC_36               (1 << 5)
#define DRM_EDID_HDMI_DC_30               (1 << 4)
#define DRM_EDID_HDMI_DC_Y444             (1 << 3)

/* YCBCR 420 deep color modes */
#define DRM_EDID_YCBCR420_DC_48		  (1 << 2)
#define DRM_EDID_YCBCR420_DC_36		  (1 << 1)
#define DRM_EDID_YCBCR420_DC_30		  (1 << 0)
#define DRM_EDID_YCBCR420_DC_MASK (DRM_EDID_YCBCR420_DC_48 | \
				    DRM_EDID_YCBCR420_DC_36 | \
				    DRM_EDID_YCBCR420_DC_30)

/* ELD Header Block */
#define DRM_ELD_HEADER_BLOCK_SIZE	4

#define DRM_ELD_VER			0
# define DRM_ELD_VER_SHIFT		3
# define DRM_ELD_VER_MASK		(0x1f << 3)
# define DRM_ELD_VER_CEA861D		(2 << 3) /* supports 861D or below */
# define DRM_ELD_VER_CANNED		(0x1f << 3)

#define DRM_ELD_BASELINE_ELD_LEN	2	/* in dwords! */

/* ELD Baseline Block for ELD_Ver == 2 */
#define DRM_ELD_CEA_EDID_VER_MNL	4
# define DRM_ELD_CEA_EDID_VER_SHIFT	5
# define DRM_ELD_CEA_EDID_VER_MASK	(7 << 5)
# define DRM_ELD_CEA_EDID_VER_NONE	(0 << 5)
# define DRM_ELD_CEA_EDID_VER_CEA861	(1 << 5)
# define DRM_ELD_CEA_EDID_VER_CEA861A	(2 << 5)
# define DRM_ELD_CEA_EDID_VER_CEA861BCD	(3 << 5)
# define DRM_ELD_MNL_SHIFT		0
# define DRM_ELD_MNL_MASK		(0x1f << 0)

#define DRM_ELD_SAD_COUNT_CONN_TYPE	5
# define DRM_ELD_SAD_COUNT_SHIFT	4
# define DRM_ELD_SAD_COUNT_MASK		(0xf << 4)
# define DRM_ELD_CONN_TYPE_SHIFT	2
# define DRM_ELD_CONN_TYPE_MASK		(3 << 2)
# define DRM_ELD_CONN_TYPE_HDMI		(0 << 2)
# define DRM_ELD_CONN_TYPE_DP		(1 << 2)
# define DRM_ELD_SUPPORTS_AI		(1 << 1)
# define DRM_ELD_SUPPORTS_HDCP		(1 << 0)

#define DRM_ELD_AUD_SYNCH_DELAY		6	/* in units of 2 ms */
# define DRM_ELD_AUD_SYNCH_DELAY_MAX	0xfa	/* 500 ms */

#define DRM_ELD_SPEAKER			7
# define DRM_ELD_SPEAKER_MASK		0x7f
# define DRM_ELD_SPEAKER_RLRC		(1 << 6)
# define DRM_ELD_SPEAKER_FLRC		(1 << 5)
# define DRM_ELD_SPEAKER_RC		(1 << 4)
# define DRM_ELD_SPEAKER_RLR		(1 << 3)
# define DRM_ELD_SPEAKER_FC		(1 << 2)
# define DRM_ELD_SPEAKER_LFE		(1 << 1)
# define DRM_ELD_SPEAKER_FLR		(1 << 0)

#define DRM_ELD_PORT_ID			8	/* offsets 8..15 inclusive */
# define DRM_ELD_PORT_ID_LEN		8

#define DRM_ELD_MANUFACTURER_NAME0	16
#define DRM_ELD_MANUFACTURER_NAME1	17

#define DRM_ELD_PRODUCT_CODE0		18
#define DRM_ELD_PRODUCT_CODE1		19

#define DRM_ELD_MONITOR_NAME_STRING	20	/* offsets 20..(20+mnl-1) inclusive */

#define DRM_ELD_CEA_SAD(mnl, sad)	(20 + (mnl) + 3 * (sad))

struct edid {
	u8 header[8];
	/* Vendor & product info */
	u8 mfg_id[2];
	u8 prod_code[2];
	u32 serial; /* FIXME: byte order */
	u8 mfg_week;
	u8 mfg_year;
	/* EDID version */
	u8 version;
	u8 revision;
	/* Display info: */
	u8 input;
	u8 width_cm;
	u8 height_cm;
	u8 gamma;
	u8 features;
	/* Color characteristics */
	u8 red_green_lo;
	u8 black_white_lo;
	u8 red_x;
	u8 red_y;
	u8 green_x;
	u8 green_y;
	u8 blue_x;
	u8 blue_y;
	u8 white_x;
	u8 white_y;
	/* Est. timings and mfg rsvd timings*/
	struct est_timings established_timings;
	/* Standard timings 1-8*/
	struct std_timing standard_timings[8];
	/* Detailing timings 1-4 */
	struct detailed_timing detailed_timings[4];
	/* Number of 128 byte ext. blocks */
	u8 extensions;
	/* Checksum */
	u8 checksum;
} __attribute__((packed));

#define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8))

/* Short Audio Descriptor */
struct cea_sad {
	u8 format;
	u8 channels; /* max number of channels - 1 */
	u8 freq;
	u8 byte2; /* meaning depends on format */
};

struct drm_encoder;
struct drm_connector;
struct drm_connector_state;
struct drm_display_mode;

int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads);
int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb);
int drm_av_sync_delay(struct drm_connector *connector,
		      const struct drm_display_mode *mode);

#ifdef CONFIG_DRM_LOAD_EDID_FIRMWARE
struct edid *drm_load_edid_firmware(struct drm_connector *connector);
int __drm_set_edid_firmware_path(const char *path);
int __drm_get_edid_firmware_path(char *buf, size_t bufsize);
#else
static inline struct edid *
drm_load_edid_firmware(struct drm_connector *connector)
{
	return ERR_PTR(-ENOENT);
}
#endif

bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2);

int
drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
					 const struct drm_connector *connector,
					 const struct drm_display_mode *mode);
int
drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
					    const struct drm_connector *connector,
					    const struct drm_display_mode *mode);

void
drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
				  const struct drm_connector_state *conn_state);

void
drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame,
			    const struct drm_connector_state *conn_state);

void
drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
				   const struct drm_connector *connector,
				   const struct drm_display_mode *mode,
				   enum hdmi_quantization_range rgb_quant_range);

int
drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame,
				    const struct drm_connector_state *conn_state);

/**
 * drm_eld_mnl - Get ELD monitor name length in bytes.
 * @eld: pointer to an eld memory structure with mnl set
 */
static inline int drm_eld_mnl(const uint8_t *eld)
{
	return (eld[DRM_ELD_CEA_EDID_VER_MNL] & DRM_ELD_MNL_MASK) >> DRM_ELD_MNL_SHIFT;
}

/**
 * drm_eld_sad - Get ELD SAD structures.
 * @eld: pointer to an eld memory structure with sad_count set
 */
static inline const uint8_t *drm_eld_sad(const uint8_t *eld)
{
	unsigned int ver, mnl;

	ver = (eld[DRM_ELD_VER] & DRM_ELD_VER_MASK) >> DRM_ELD_VER_SHIFT;
	if (ver != 2 && ver != 31)
		return NULL;

	mnl = drm_eld_mnl(eld);
	if (mnl > 16)
		return NULL;

	return eld + DRM_ELD_CEA_SAD(mnl, 0);
}

/**
 * drm_eld_sad_count - Get ELD SAD count.
 * @eld: pointer to an eld memory structure with sad_count set
 */
static inline int drm_eld_sad_count(const uint8_t *eld)
{
	return (eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_SAD_COUNT_MASK) >>
		DRM_ELD_SAD_COUNT_SHIFT;
}

/**
 * drm_eld_calc_baseline_block_size - Calculate baseline block size in bytes
 * @eld: pointer to an eld memory structure with mnl and sad_count set
 *
 * This is a helper for determining the payload size of the baseline block, in
 * bytes, for e.g. setting the Baseline_ELD_Len field in the ELD header block.
 */
static inline int drm_eld_calc_baseline_block_size(const uint8_t *eld)
{
	return DRM_ELD_MONITOR_NAME_STRING - DRM_ELD_HEADER_BLOCK_SIZE +
		drm_eld_mnl(eld) + drm_eld_sad_count(eld) * 3;
}

/**
 * drm_eld_size - Get ELD size in bytes
 * @eld: pointer to a complete eld memory structure
 *
 * The returned value does not include the vendor block. It's vendor specific,
 * and comprises of the remaining bytes in the ELD memory buffer after
 * drm_eld_size() bytes of header and baseline block.
 *
 * The returned value is guaranteed to be a multiple of 4.
 */
static inline int drm_eld_size(const uint8_t *eld)
{
	return DRM_ELD_HEADER_BLOCK_SIZE + eld[DRM_ELD_BASELINE_ELD_LEN] * 4;
}

/**
 * drm_eld_get_spk_alloc - Get speaker allocation
 * @eld: pointer to an ELD memory structure
 *
 * The returned value is the speakers mask. User has to use %DRM_ELD_SPEAKER
 * field definitions to identify speakers.
 */
static inline u8 drm_eld_get_spk_alloc(const uint8_t *eld)
{
	return eld[DRM_ELD_SPEAKER] & DRM_ELD_SPEAKER_MASK;
}

/**
 * drm_eld_get_conn_type - Get device type hdmi/dp connected
 * @eld: pointer to an ELD memory structure
 *
 * The caller need to use %DRM_ELD_CONN_TYPE_HDMI or %DRM_ELD_CONN_TYPE_DP to
 * identify the display type connected.
 */
static inline u8 drm_eld_get_conn_type(const uint8_t *eld)
{
	return eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_CONN_TYPE_MASK;
}

bool drm_probe_ddc(struct i2c_adapter *adapter);
struct edid *drm_do_get_edid(struct drm_connector *connector,
	int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
			      size_t len),
	void *data);
struct edid *drm_get_edid(struct drm_connector *connector,
			  struct i2c_adapter *adapter);
struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
				     struct i2c_adapter *adapter);
struct edid *drm_edid_duplicate(const struct edid *edid);
int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid);
int drm_add_override_edid_modes(struct drm_connector *connector);

u8 drm_match_cea_mode(const struct drm_display_mode *to_match);
bool drm_detect_hdmi_monitor(struct edid *edid);
bool drm_detect_monitor_audio(struct edid *edid);
enum hdmi_quantization_range
drm_default_rgb_quant_range(const struct drm_display_mode *mode);
int drm_add_modes_noedid(struct drm_connector *connector,
			 int hdisplay, int vdisplay);
void drm_set_preferred_mode(struct drm_connector *connector,
			    int hpref, int vpref);

int drm_edid_header_is_valid(const u8 *raw_edid);
bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
			  bool *edid_corrupt);
bool drm_edid_is_valid(struct edid *edid);
void drm_edid_get_monitor_name(struct edid *edid, char *name,
			       int buflen);
struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
					   int hsize, int vsize, int fresh,
					   bool rb);
struct drm_display_mode *
drm_display_mode_from_cea_vic(struct drm_device *dev,
			      u8 video_code);

#endif /* __DRM_EDID_H__ */
Commit	Line	Data
f453ba04 DA	1	/*
	2	* Copyright © 2007-2008 Intel Corporation
	3	* Jesse Barnes <jesse.barnes@intel.com>
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the "Software"),
	7	* to deal in the Software without restriction, including without limitation
	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	9	* and/or sell copies of the Software, and to permit persons to whom the
	10	* Software is furnished to do so, subject to the following conditions:
	11	*
	12	* The above copyright notice and this permission notice shall be included in
	13	* all copies or substantial portions of the Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	21	* OTHER DEALINGS IN THE SOFTWARE.
	22	*/
	23	#ifndef __DRM_EDID_H__
	24	#define __DRM_EDID_H__
	25
	26	#include <linux/types.h>
00147934	27	#include <linux/hdmi.h>
2cdbfd66	28	#include <drm/drm_mode.h>
f453ba04	29
cdc3d09f DV	30	struct drm_device;
	31	struct i2c_adapter;
	32
f453ba04 DA	33	#define EDID_LENGTH 128
f453ba04 DA	34	#define DDC_ADDR 0x50
b49b55bd	35	#define DDC_ADDR2 0x52 /* E-DDC 1.2 - where DisplayID can hide */
f453ba04	36
4d76a221 AJ	37	#define CEA_EXT 0x02
	38	#define VTB_EXT 0x10
	39	#define DI_EXT 0x40
	40	#define LS_EXT 0x50
	41	#define MI_EXT 0x60
b49b55bd	42	#define DISPLAYID_EXT 0x70
4d76a221	43
f453ba04 DA	44	struct est_timings {
	45	u8 t1;
	46	u8 t2;
	47	u8 mfg_rsvd;
	48	} __attribute__((packed));
	49
0454beab	50	/* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */
e14cbee4	51	#define EDID_TIMING_ASPECT_SHIFT 6
0454beab MD	52	#define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT)
	53
	54	/* need to add 60 */
e14cbee4	55	#define EDID_TIMING_VFREQ_SHIFT 0
0454beab MD	56	#define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT)
0454beab MD	57
f453ba04 DA	58	struct std_timing {
f453ba04 DA	59	u8 hsize; /* need to multiply by 8 then add 248 */
0454beab	60	u8 vfreq_aspect;
f453ba04 DA	61	} __attribute__((packed));
f453ba04 DA	62
e14cbee4 MD	63	#define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1)
e14cbee4 MD	64	#define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2)
0454beab	65	#define DRM_EDID_PT_SEPARATE_SYNC (3 << 3)
e14cbee4 MD	66	#define DRM_EDID_PT_STEREO (1 << 5)
e14cbee4 MD	67	#define DRM_EDID_PT_INTERLACED (1 << 7)
0454beab	68
f453ba04 DA	69	/* If detailed data is pixel timing */
	70	struct detailed_pixel_timing {
	71	u8 hactive_lo;
	72	u8 hblank_lo;
0454beab	73	u8 hactive_hblank_hi;
f453ba04 DA	74	u8 vactive_lo;
f453ba04 DA	75	u8 vblank_lo;
0454beab	76	u8 vactive_vblank_hi;
f453ba04 DA	77	u8 hsync_offset_lo;
f453ba04 DA	78	u8 hsync_pulse_width_lo;
0454beab MD	79	u8 vsync_offset_pulse_width_lo;
0454beab MD	80	u8 hsync_vsync_offset_pulse_width_hi;
f453ba04 DA	81	u8 width_mm_lo;
f453ba04 DA	82	u8 height_mm_lo;
0454beab	83	u8 width_height_mm_hi;
f453ba04 DA	84	u8 hborder;
f453ba04 DA	85	u8 vborder;
0454beab	86	u8 misc;
f453ba04 DA	87	} __attribute__((packed));
	88
	89	/* If it's not pixel timing, it'll be one of the below */
	90	struct detailed_data_string {
	91	u8 str[13];
	92	} __attribute__((packed));
	93
f1ce9876 MN	94	#define DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG 0x00
	95	#define DRM_EDID_RANGE_LIMITS_ONLY_FLAG 0x01
	96	#define DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG 0x02
	97	#define DRM_EDID_CVT_SUPPORT_FLAG 0x04
	98
f453ba04 DA	99	struct detailed_data_monitor_range {
	100	u8 min_vfreq;
	101	u8 max_vfreq;
	102	u8 min_hfreq_khz;
	103	u8 max_hfreq_khz;
	104	u8 pixel_clock_mhz; /* need to multiply by 10 */
eeefa4be AJ	105	u8 flags;
	106	union {
	107	struct {
	108	u8 reserved;
	109	u8 hfreq_start_khz; /* need to multiply by 2 */
	110	u8 c; /* need to divide by 2 */
	111	__le16 m;
	112	u8 k;
	113	u8 j; /* need to divide by 2 */
8353e6c6	114	} __attribute__((packed)) gtf2;
eeefa4be AJ	115	struct {
	116	u8 version;
	117	u8 data1; /* high 6 bits: extra clock resolution */
	118	u8 data2; /* plus low 2 of above: max hactive */
	119	u8 supported_aspects;
	120	u8 flags; /* preferred aspect and blanking support */
	121	u8 supported_scalings;
	122	u8 preferred_refresh;
8353e6c6	123	} __attribute__((packed)) cvt;
eeefa4be	124	} formula;
f453ba04 DA	125	} __attribute__((packed));
	126
	127	struct detailed_data_wpindex {
e14cbee4	128	u8 white_yx_lo; /* Lower 2 bits each */
f453ba04 DA	129	u8 white_x_hi;
	130	u8 white_y_hi;
	131	u8 gamma; /* need to divide by 100 then add 1 */
	132	} __attribute__((packed));
	133
	134	struct detailed_data_color_point {
	135	u8 windex1;
	136	u8 wpindex1[3];
	137	u8 windex2;
	138	u8 wpindex2[3];
	139	} __attribute__((packed));
	140
9340d8cf AJ	141	struct cvt_timing {
	142	u8 code[3];
	143	} __attribute__((packed));
	144
f453ba04 DA	145	struct detailed_non_pixel {
	146	u8 pad1;
	147	u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name
	148	fb=color point data, fa=standard timing data,
	149	f9=undefined, f8=mfg. reserved */
	150	u8 pad2;
	151	union {
	152	struct detailed_data_string str;
	153	struct detailed_data_monitor_range range;
	154	struct detailed_data_wpindex color;
96525a2f	155	struct std_timing timings[6];
9340d8cf	156	struct cvt_timing cvt[4];
f453ba04 DA	157	} data;
	158	} __attribute__((packed));
	159
2dbdc52c AJ	160	#define EDID_DETAIL_EST_TIMINGS 0xf7
	161	#define EDID_DETAIL_CVT_3BYTE 0xf8
	162	#define EDID_DETAIL_COLOR_MGMT_DATA 0xf9
f453ba04 DA	163	#define EDID_DETAIL_STD_MODES 0xfa
	164	#define EDID_DETAIL_MONITOR_CPDATA 0xfb
	165	#define EDID_DETAIL_MONITOR_NAME 0xfc
	166	#define EDID_DETAIL_MONITOR_RANGE 0xfd
	167	#define EDID_DETAIL_MONITOR_STRING 0xfe
	168	#define EDID_DETAIL_MONITOR_SERIAL 0xff
	169
	170	struct detailed_timing {
0454beab	171	__le16 pixel_clock; /* need to multiply by 10 KHz */
f453ba04 DA	172	union {
	173	struct detailed_pixel_timing pixel_data;
	174	struct detailed_non_pixel other_data;
	175	} data;
	176	} __attribute__((packed));
	177
e14cbee4 MD	178	#define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0)
	179	#define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 1)
	180	#define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 2)
0454beab	181	#define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3)
e14cbee4 MD	182	#define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 4)
e14cbee4 MD	183	#define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 5)
3b11228b	184	#define DRM_EDID_INPUT_DIGITAL (1 << 7)
382d2af6 VS	185	#define DRM_EDID_DIGITAL_DEPTH_MASK (7 << 4) /* 1.4 */
	186	#define DRM_EDID_DIGITAL_DEPTH_UNDEF (0 << 4) /* 1.4 */
	187	#define DRM_EDID_DIGITAL_DEPTH_6 (1 << 4) /* 1.4 */
	188	#define DRM_EDID_DIGITAL_DEPTH_8 (2 << 4) /* 1.4 */
	189	#define DRM_EDID_DIGITAL_DEPTH_10 (3 << 4) /* 1.4 */
	190	#define DRM_EDID_DIGITAL_DEPTH_12 (4 << 4) /* 1.4 */
	191	#define DRM_EDID_DIGITAL_DEPTH_14 (5 << 4) /* 1.4 */
	192	#define DRM_EDID_DIGITAL_DEPTH_16 (6 << 4) /* 1.4 */
	193	#define DRM_EDID_DIGITAL_DEPTH_RSVD (7 << 4) /* 1.4 */
	194	#define DRM_EDID_DIGITAL_TYPE_MASK (7 << 0) /* 1.4 */
	195	#define DRM_EDID_DIGITAL_TYPE_UNDEF (0 << 0) /* 1.4 */
	196	#define DRM_EDID_DIGITAL_TYPE_DVI (1 << 0) /* 1.4 */
	197	#define DRM_EDID_DIGITAL_TYPE_HDMI_A (2 << 0) /* 1.4 */
	198	#define DRM_EDID_DIGITAL_TYPE_HDMI_B (3 << 0) /* 1.4 */
	199	#define DRM_EDID_DIGITAL_TYPE_MDDI (4 << 0) /* 1.4 */
	200	#define DRM_EDID_DIGITAL_TYPE_DP (5 << 0) /* 1.4 */
	201	#define DRM_EDID_DIGITAL_DFP_1_X (1 << 0) /* 1.3 */
0454beab	202
e14cbee4 MD	203	#define DRM_EDID_FEATURE_DEFAULT_GTF (1 << 0)
	204	#define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1)
	205	#define DRM_EDID_FEATURE_STANDARD_COLOR (1 << 2)
da05a5a7	206	/* If analog */
0454beab	207	#define DRM_EDID_FEATURE_DISPLAY_TYPE (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */
da05a5a7 JB	208	/* If digital */
	209	#define DRM_EDID_FEATURE_COLOR_MASK (3 << 3)
	210	#define DRM_EDID_FEATURE_RGB (0 << 3)
	211	#define DRM_EDID_FEATURE_RGB_YCRCB444 (1 << 3)
	212	#define DRM_EDID_FEATURE_RGB_YCRCB422 (2 << 3)
	213	#define DRM_EDID_FEATURE_RGB_YCRCB (3 << 3) /* both 4:4:4 and 4:2:2 */
	214
e14cbee4 MD	215	#define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 << 5)
	216	#define DRM_EDID_FEATURE_PM_SUSPEND (1 << 6)
	217	#define DRM_EDID_FEATURE_PM_STANDBY (1 << 7)
0454beab	218
d0c94692 MK	219	#define DRM_EDID_HDMI_DC_48 (1 << 6)
	220	#define DRM_EDID_HDMI_DC_36 (1 << 5)
	221	#define DRM_EDID_HDMI_DC_30 (1 << 4)
	222	#define DRM_EDID_HDMI_DC_Y444 (1 << 3)
	223
e6a9a2c3	224	/* YCBCR 420 deep color modes */
9068e02f CT	225	#define DRM_EDID_YCBCR420_DC_48 (1 << 2)
	226	#define DRM_EDID_YCBCR420_DC_36 (1 << 1)
	227	#define DRM_EDID_YCBCR420_DC_30 (1 << 0)
e6a9a2c3 SS	228	#define DRM_EDID_YCBCR420_DC_MASK (DRM_EDID_YCBCR420_DC_48 \| \
	229	DRM_EDID_YCBCR420_DC_36 \| \
	230	DRM_EDID_YCBCR420_DC_30)
	231
babc9493 JN	232	/* ELD Header Block */
	233	#define DRM_ELD_HEADER_BLOCK_SIZE 4
	234
	235	#define DRM_ELD_VER 0
	236	# define DRM_ELD_VER_SHIFT 3
	237	# define DRM_ELD_VER_MASK (0x1f << 3)
1b54bdb8 JN	238	# define DRM_ELD_VER_CEA861D (2 << 3) /* supports 861D or below */
1b54bdb8 JN	239	# define DRM_ELD_VER_CANNED (0x1f << 3)
babc9493 JN	240
	241	#define DRM_ELD_BASELINE_ELD_LEN 2 /* in dwords! */
	242
	243	/* ELD Baseline Block for ELD_Ver == 2 */
	244	#define DRM_ELD_CEA_EDID_VER_MNL 4
	245	# define DRM_ELD_CEA_EDID_VER_SHIFT 5
	246	# define DRM_ELD_CEA_EDID_VER_MASK (7 << 5)
	247	# define DRM_ELD_CEA_EDID_VER_NONE (0 << 5)
	248	# define DRM_ELD_CEA_EDID_VER_CEA861 (1 << 5)
	249	# define DRM_ELD_CEA_EDID_VER_CEA861A (2 << 5)
	250	# define DRM_ELD_CEA_EDID_VER_CEA861BCD (3 << 5)
	251	# define DRM_ELD_MNL_SHIFT 0
	252	# define DRM_ELD_MNL_MASK (0x1f << 0)
	253
	254	#define DRM_ELD_SAD_COUNT_CONN_TYPE 5
	255	# define DRM_ELD_SAD_COUNT_SHIFT 4
	256	# define DRM_ELD_SAD_COUNT_MASK (0xf << 4)
	257	# define DRM_ELD_CONN_TYPE_SHIFT 2
	258	# define DRM_ELD_CONN_TYPE_MASK (3 << 2)
	259	# define DRM_ELD_CONN_TYPE_HDMI (0 << 2)
	260	# define DRM_ELD_CONN_TYPE_DP (1 << 2)
	261	# define DRM_ELD_SUPPORTS_AI (1 << 1)
	262	# define DRM_ELD_SUPPORTS_HDCP (1 << 0)
	263
	264	#define DRM_ELD_AUD_SYNCH_DELAY 6 /* in units of 2 ms */
	265	# define DRM_ELD_AUD_SYNCH_DELAY_MAX 0xfa /* 500 ms */
	266
	267	#define DRM_ELD_SPEAKER 7
c82dbe5c	268	# define DRM_ELD_SPEAKER_MASK 0x7f
babc9493 JN	269	# define DRM_ELD_SPEAKER_RLRC (1 << 6)
	270	# define DRM_ELD_SPEAKER_FLRC (1 << 5)
	271	# define DRM_ELD_SPEAKER_RC (1 << 4)
	272	# define DRM_ELD_SPEAKER_RLR (1 << 3)
	273	# define DRM_ELD_SPEAKER_FC (1 << 2)
	274	# define DRM_ELD_SPEAKER_LFE (1 << 1)
	275	# define DRM_ELD_SPEAKER_FLR (1 << 0)
	276
	277	#define DRM_ELD_PORT_ID 8 /* offsets 8..15 inclusive */
	278	# define DRM_ELD_PORT_ID_LEN 8
	279
	280	#define DRM_ELD_MANUFACTURER_NAME0 16
	281	#define DRM_ELD_MANUFACTURER_NAME1 17
	282
	283	#define DRM_ELD_PRODUCT_CODE0 18
	284	#define DRM_ELD_PRODUCT_CODE1 19
	285
	286	#define DRM_ELD_MONITOR_NAME_STRING 20 /* offsets 20..(20+mnl-1) inclusive */
	287
	288	#define DRM_ELD_CEA_SAD(mnl, sad) (20 + (mnl) + 3 * (sad))
	289
f453ba04 DA	290	struct edid {
	291	u8 header[8];
	292	/* Vendor & product info */
	293	u8 mfg_id[2];
	294	u8 prod_code[2];
	295	u32 serial; /* FIXME: byte order */
	296	u8 mfg_week;
	297	u8 mfg_year;
	298	/* EDID version */
	299	u8 version;
	300	u8 revision;
	301	/* Display info: */
0454beab	302	u8 input;
f453ba04 DA	303	u8 width_cm;
	304	u8 height_cm;
	305	u8 gamma;
0454beab	306	u8 features;
f453ba04 DA	307	/* Color characteristics */
	308	u8 red_green_lo;
	309	u8 black_white_lo;
	310	u8 red_x;
	311	u8 red_y;
	312	u8 green_x;
	313	u8 green_y;
	314	u8 blue_x;
	315	u8 blue_y;
	316	u8 white_x;
	317	u8 white_y;
	318	/* Est. timings and mfg rsvd timings*/
	319	struct est_timings established_timings;
	320	/* Standard timings 1-8*/
	321	struct std_timing standard_timings[8];
	322	/* Detailing timings 1-4 */
	323	struct detailed_timing detailed_timings[4];
	324	/* Number of 128 byte ext. blocks */
	325	u8 extensions;
	326	/* Checksum */
	327	u8 checksum;
	328	} __attribute__((packed));
	329
f453ba04 DA	330	#define EDID_PRODUCT_ID(e) ((e)->prod_code[0] \| ((e)->prod_code[1] << 8))
f453ba04 DA	331
fe214163 RM	332	/* Short Audio Descriptor */
	333	struct cea_sad {
	334	u8 format;
	335	u8 channels; /* max number of channels - 1 */
	336	u8 freq;
	337	u8 byte2; /* meaning depends on format */
	338	};
	339
76adaa34 WF	340	struct drm_encoder;
76adaa34 WF	341	struct drm_connector;
0d68b887	342	struct drm_connector_state;
76adaa34	343	struct drm_display_mode;
10a85120	344
fe214163	345	int drm_edid_to_sad(struct edid edid, struct cea_sad *sads);
d105f476	346	int drm_edid_to_speaker_allocation(struct edid edid, u8 *sadb);
76adaa34	347	int drm_av_sync_delay(struct drm_connector *connector,
3a818d35	348	const struct drm_display_mode *mode);
ba34d58c EG	349
ba34d58c EG	350	#ifdef CONFIG_DRM_LOAD_EDID_FIRMWARE
07c2b84b	351	struct edid drm_load_edid_firmware(struct drm_connector connector);
ac6c35a4 JN	352	int __drm_set_edid_firmware_path(const char *path);
ac6c35a4 JN	353	int __drm_get_edid_firmware_path(char *buf, size_t bufsize);
ba34d58c	354	#else
07c2b84b JN	355	static inline struct edid *
07c2b84b JN	356	drm_load_edid_firmware(struct drm_connector *connector)
ba34d58c	357	{
07c2b84b	358	return ERR_PTR(-ENOENT);
ba34d58c EG	359	}
ba34d58c EG	360	#endif
76adaa34	361
536faa45 SL	362	bool drm_edid_are_equal(const struct edid edid1, const struct edid edid2);
536faa45 SL	363
10a85120 TR	364	int
10a85120 TR	365	drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
192a3aa0	366	const struct drm_connector *connector,
13d0add3	367	const struct drm_display_mode *mode);
83dd0008 LD	368	int
83dd0008 LD	369	drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
192a3aa0	370	const struct drm_connector *connector,
83dd0008	371	const struct drm_display_mode *mode);
0d68b887 US	372
	373	void
	374	drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
	375	const struct drm_connector_state *conn_state);
	376
076d9a5d VS	377	void
	378	drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame,
	379	const struct drm_connector_state *conn_state);
	380
a2ce26f8 VS	381	void
a2ce26f8 VS	382	drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
192a3aa0	383	const struct drm_connector *connector,
779c4c28	384	const struct drm_display_mode *mode,
1581b2df	385	enum hdmi_quantization_range rgb_quant_range);
10a85120	386
2cdbfd66 US	387	int
	388	drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame,
	389	const struct drm_connector_state *conn_state);
	390
babc9493 JN	391	/**
	392	* drm_eld_mnl - Get ELD monitor name length in bytes.
	393	* @eld: pointer to an eld memory structure with mnl set
	394	*/
	395	static inline int drm_eld_mnl(const uint8_t *eld)
	396	{
	397	return (eld[DRM_ELD_CEA_EDID_VER_MNL] & DRM_ELD_MNL_MASK) >> DRM_ELD_MNL_SHIFT;
	398	}
	399
1c73d3b1 RK	400	/**
	401	* drm_eld_sad - Get ELD SAD structures.
	402	* @eld: pointer to an eld memory structure with sad_count set
	403	*/
	404	static inline const uint8_t drm_eld_sad(const uint8_t eld)
	405	{
	406	unsigned int ver, mnl;
	407
	408	ver = (eld[DRM_ELD_VER] & DRM_ELD_VER_MASK) >> DRM_ELD_VER_SHIFT;
	409	if (ver != 2 && ver != 31)
	410	return NULL;
	411
	412	mnl = drm_eld_mnl(eld);
	413	if (mnl > 16)
	414	return NULL;
	415
	416	return eld + DRM_ELD_CEA_SAD(mnl, 0);
	417	}
	418
babc9493 JN	419	/**
	420	* drm_eld_sad_count - Get ELD SAD count.
	421	* @eld: pointer to an eld memory structure with sad_count set
	422	*/
	423	static inline int drm_eld_sad_count(const uint8_t *eld)
	424	{
	425	return (eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_SAD_COUNT_MASK) >>
	426	DRM_ELD_SAD_COUNT_SHIFT;
	427	}
	428
	429	/**
	430	* drm_eld_calc_baseline_block_size - Calculate baseline block size in bytes
	431	* @eld: pointer to an eld memory structure with mnl and sad_count set
	432	*
	433	* This is a helper for determining the payload size of the baseline block, in
	434	* bytes, for e.g. setting the Baseline_ELD_Len field in the ELD header block.
	435	*/
	436	static inline int drm_eld_calc_baseline_block_size(const uint8_t *eld)
	437	{
	438	return DRM_ELD_MONITOR_NAME_STRING - DRM_ELD_HEADER_BLOCK_SIZE +
	439	drm_eld_mnl(eld) + drm_eld_sad_count(eld) * 3;
	440	}
	441
	442	/**
	443	* drm_eld_size - Get ELD size in bytes
	444	* @eld: pointer to a complete eld memory structure
	445	*
	446	* The returned value does not include the vendor block. It's vendor specific,
	447	* and comprises of the remaining bytes in the ELD memory buffer after
	448	* drm_eld_size() bytes of header and baseline block.
	449	*
	450	* The returned value is guaranteed to be a multiple of 4.
	451	*/
	452	static inline int drm_eld_size(const uint8_t *eld)
	453	{
	454	return DRM_ELD_HEADER_BLOCK_SIZE + eld[DRM_ELD_BASELINE_ELD_LEN] * 4;
	455	}
	456
c82dbe5c AP	457	/**
	458	* drm_eld_get_spk_alloc - Get speaker allocation
	459	* @eld: pointer to an ELD memory structure
	460	*
	461	* The returned value is the speakers mask. User has to use %DRM_ELD_SPEAKER
	462	* field definitions to identify speakers.
	463	*/
	464	static inline u8 drm_eld_get_spk_alloc(const uint8_t *eld)
	465	{
	466	return eld[DRM_ELD_SPEAKER] & DRM_ELD_SPEAKER_MASK;
	467	}
	468
1aa8ec25 SP	469	/**
	470	* drm_eld_get_conn_type - Get device type hdmi/dp connected
	471	* @eld: pointer to an ELD memory structure
	472	*
	473	* The caller need to use %DRM_ELD_CONN_TYPE_HDMI or %DRM_ELD_CONN_TYPE_DP to
	474	* identify the display type connected.
	475	*/
	476	static inline u8 drm_eld_get_conn_type(const uint8_t *eld)
	477	{
	478	return eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_CONN_TYPE_MASK;
	479	}
	480
cdc3d09f	481	bool drm_probe_ddc(struct i2c_adapter *adapter);
18df89fe LPC	482	struct edid drm_do_get_edid(struct drm_connector connector,
	483	int (get_edid_block)(void data, u8 *buf, unsigned int block,
	484	size_t len),
	485	void *data);
cdc3d09f DV	486	struct edid drm_get_edid(struct drm_connector connector,
	487	struct i2c_adapter *adapter);
	488	struct edid drm_get_edid_switcheroo(struct drm_connector connector,
	489	struct i2c_adapter *adapter);
	490	struct edid drm_edid_duplicate(const struct edid edid);
	491	int drm_add_edid_modes(struct drm_connector connector, struct edid edid);
48eaeb76	492	int drm_add_override_edid_modes(struct drm_connector *connector);
cdc3d09f DV	493
cdc3d09f DV	494	u8 drm_match_cea_mode(const struct drm_display_mode *to_match);
cdc3d09f DV	495	bool drm_detect_hdmi_monitor(struct edid *edid);
cdc3d09f DV	496	bool drm_detect_monitor_audio(struct edid *edid);
c8127cf0 VS	497	enum hdmi_quantization_range
c8127cf0 VS	498	drm_default_rgb_quant_range(const struct drm_display_mode *mode);
cdc3d09f DV	499	int drm_add_modes_noedid(struct drm_connector *connector,
	500	int hdisplay, int vdisplay);
	501	void drm_set_preferred_mode(struct drm_connector *connector,
	502	int hpref, int vpref);
	503
	504	int drm_edid_header_is_valid(const u8 *raw_edid);
	505	bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
	506	bool *edid_corrupt);
	507	bool drm_edid_is_valid(struct edid *edid);
	508	void drm_edid_get_monitor_name(struct edid edid, char name,
	509	int buflen);
	510	struct drm_display_mode drm_mode_find_dmt(struct drm_device dev,
	511	int hsize, int vsize, int fresh,
	512	bool rb);
7af655bc VS	513	struct drm_display_mode *
	514	drm_display_mode_from_cea_vic(struct drm_device *dev,
	515	u8 video_code);
	516
f453ba04	517	#endif /* __DRM_EDID_H__ */