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f453ba04 DA |
1 | /* |
2 | * Copyright © 2007-2008 Intel Corporation | |
3 | * Jesse Barnes <jesse.barnes@intel.com> | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice shall be included in | |
13 | * all copies or substantial portions of the Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
21 | * OTHER DEALINGS IN THE SOFTWARE. | |
22 | */ | |
23 | #ifndef __DRM_EDID_H__ | |
24 | #define __DRM_EDID_H__ | |
25 | ||
26 | #include <linux/types.h> | |
27 | ||
28 | #define EDID_LENGTH 128 | |
29 | #define DDC_ADDR 0x50 | |
30 | ||
4d76a221 AJ |
31 | #define CEA_EXT 0x02 |
32 | #define VTB_EXT 0x10 | |
33 | #define DI_EXT 0x40 | |
34 | #define LS_EXT 0x50 | |
35 | #define MI_EXT 0x60 | |
36 | ||
f453ba04 DA |
37 | struct est_timings { |
38 | u8 t1; | |
39 | u8 t2; | |
40 | u8 mfg_rsvd; | |
41 | } __attribute__((packed)); | |
42 | ||
0454beab | 43 | /* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */ |
e14cbee4 | 44 | #define EDID_TIMING_ASPECT_SHIFT 6 |
0454beab MD |
45 | #define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT) |
46 | ||
47 | /* need to add 60 */ | |
e14cbee4 | 48 | #define EDID_TIMING_VFREQ_SHIFT 0 |
0454beab MD |
49 | #define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT) |
50 | ||
f453ba04 DA |
51 | struct std_timing { |
52 | u8 hsize; /* need to multiply by 8 then add 248 */ | |
0454beab | 53 | u8 vfreq_aspect; |
f453ba04 DA |
54 | } __attribute__((packed)); |
55 | ||
e14cbee4 MD |
56 | #define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1) |
57 | #define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2) | |
0454beab | 58 | #define DRM_EDID_PT_SEPARATE_SYNC (3 << 3) |
e14cbee4 MD |
59 | #define DRM_EDID_PT_STEREO (1 << 5) |
60 | #define DRM_EDID_PT_INTERLACED (1 << 7) | |
0454beab | 61 | |
f453ba04 DA |
62 | /* If detailed data is pixel timing */ |
63 | struct detailed_pixel_timing { | |
64 | u8 hactive_lo; | |
65 | u8 hblank_lo; | |
0454beab | 66 | u8 hactive_hblank_hi; |
f453ba04 DA |
67 | u8 vactive_lo; |
68 | u8 vblank_lo; | |
0454beab | 69 | u8 vactive_vblank_hi; |
f453ba04 DA |
70 | u8 hsync_offset_lo; |
71 | u8 hsync_pulse_width_lo; | |
0454beab MD |
72 | u8 vsync_offset_pulse_width_lo; |
73 | u8 hsync_vsync_offset_pulse_width_hi; | |
f453ba04 DA |
74 | u8 width_mm_lo; |
75 | u8 height_mm_lo; | |
0454beab | 76 | u8 width_height_mm_hi; |
f453ba04 DA |
77 | u8 hborder; |
78 | u8 vborder; | |
0454beab | 79 | u8 misc; |
f453ba04 DA |
80 | } __attribute__((packed)); |
81 | ||
82 | /* If it's not pixel timing, it'll be one of the below */ | |
83 | struct detailed_data_string { | |
84 | u8 str[13]; | |
85 | } __attribute__((packed)); | |
86 | ||
87 | struct detailed_data_monitor_range { | |
88 | u8 min_vfreq; | |
89 | u8 max_vfreq; | |
90 | u8 min_hfreq_khz; | |
91 | u8 max_hfreq_khz; | |
92 | u8 pixel_clock_mhz; /* need to multiply by 10 */ | |
0454beab | 93 | __le16 sec_gtf_toggle; /* A000=use above, 20=use below */ |
f453ba04 DA |
94 | u8 hfreq_start_khz; /* need to multiply by 2 */ |
95 | u8 c; /* need to divide by 2 */ | |
0454beab | 96 | __le16 m; |
f453ba04 DA |
97 | u8 k; |
98 | u8 j; /* need to divide by 2 */ | |
99 | } __attribute__((packed)); | |
100 | ||
101 | struct detailed_data_wpindex { | |
e14cbee4 | 102 | u8 white_yx_lo; /* Lower 2 bits each */ |
f453ba04 DA |
103 | u8 white_x_hi; |
104 | u8 white_y_hi; | |
105 | u8 gamma; /* need to divide by 100 then add 1 */ | |
106 | } __attribute__((packed)); | |
107 | ||
108 | struct detailed_data_color_point { | |
109 | u8 windex1; | |
110 | u8 wpindex1[3]; | |
111 | u8 windex2; | |
112 | u8 wpindex2[3]; | |
113 | } __attribute__((packed)); | |
114 | ||
9340d8cf AJ |
115 | struct cvt_timing { |
116 | u8 code[3]; | |
117 | } __attribute__((packed)); | |
118 | ||
f453ba04 DA |
119 | struct detailed_non_pixel { |
120 | u8 pad1; | |
121 | u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name | |
122 | fb=color point data, fa=standard timing data, | |
123 | f9=undefined, f8=mfg. reserved */ | |
124 | u8 pad2; | |
125 | union { | |
126 | struct detailed_data_string str; | |
127 | struct detailed_data_monitor_range range; | |
128 | struct detailed_data_wpindex color; | |
96525a2f | 129 | struct std_timing timings[6]; |
9340d8cf | 130 | struct cvt_timing cvt[4]; |
f453ba04 DA |
131 | } data; |
132 | } __attribute__((packed)); | |
133 | ||
2dbdc52c AJ |
134 | #define EDID_DETAIL_EST_TIMINGS 0xf7 |
135 | #define EDID_DETAIL_CVT_3BYTE 0xf8 | |
136 | #define EDID_DETAIL_COLOR_MGMT_DATA 0xf9 | |
f453ba04 DA |
137 | #define EDID_DETAIL_STD_MODES 0xfa |
138 | #define EDID_DETAIL_MONITOR_CPDATA 0xfb | |
139 | #define EDID_DETAIL_MONITOR_NAME 0xfc | |
140 | #define EDID_DETAIL_MONITOR_RANGE 0xfd | |
141 | #define EDID_DETAIL_MONITOR_STRING 0xfe | |
142 | #define EDID_DETAIL_MONITOR_SERIAL 0xff | |
143 | ||
144 | struct detailed_timing { | |
0454beab | 145 | __le16 pixel_clock; /* need to multiply by 10 KHz */ |
f453ba04 DA |
146 | union { |
147 | struct detailed_pixel_timing pixel_data; | |
148 | struct detailed_non_pixel other_data; | |
149 | } data; | |
150 | } __attribute__((packed)); | |
151 | ||
e14cbee4 MD |
152 | #define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0) |
153 | #define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 1) | |
154 | #define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 2) | |
0454beab | 155 | #define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3) |
e14cbee4 MD |
156 | #define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 4) |
157 | #define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 5) | |
158 | #define DRM_EDID_INPUT_DIGITAL (1 << 7) /* bits below must be zero if set */ | |
0454beab | 159 | |
e14cbee4 MD |
160 | #define DRM_EDID_FEATURE_DEFAULT_GTF (1 << 0) |
161 | #define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1) | |
162 | #define DRM_EDID_FEATURE_STANDARD_COLOR (1 << 2) | |
0454beab | 163 | #define DRM_EDID_FEATURE_DISPLAY_TYPE (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */ |
e14cbee4 MD |
164 | #define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 << 5) |
165 | #define DRM_EDID_FEATURE_PM_SUSPEND (1 << 6) | |
166 | #define DRM_EDID_FEATURE_PM_STANDBY (1 << 7) | |
0454beab | 167 | |
f453ba04 DA |
168 | struct edid { |
169 | u8 header[8]; | |
170 | /* Vendor & product info */ | |
171 | u8 mfg_id[2]; | |
172 | u8 prod_code[2]; | |
173 | u32 serial; /* FIXME: byte order */ | |
174 | u8 mfg_week; | |
175 | u8 mfg_year; | |
176 | /* EDID version */ | |
177 | u8 version; | |
178 | u8 revision; | |
179 | /* Display info: */ | |
0454beab | 180 | u8 input; |
f453ba04 DA |
181 | u8 width_cm; |
182 | u8 height_cm; | |
183 | u8 gamma; | |
0454beab | 184 | u8 features; |
f453ba04 DA |
185 | /* Color characteristics */ |
186 | u8 red_green_lo; | |
187 | u8 black_white_lo; | |
188 | u8 red_x; | |
189 | u8 red_y; | |
190 | u8 green_x; | |
191 | u8 green_y; | |
192 | u8 blue_x; | |
193 | u8 blue_y; | |
194 | u8 white_x; | |
195 | u8 white_y; | |
196 | /* Est. timings and mfg rsvd timings*/ | |
197 | struct est_timings established_timings; | |
198 | /* Standard timings 1-8*/ | |
199 | struct std_timing standard_timings[8]; | |
200 | /* Detailing timings 1-4 */ | |
201 | struct detailed_timing detailed_timings[4]; | |
202 | /* Number of 128 byte ext. blocks */ | |
203 | u8 extensions; | |
204 | /* Checksum */ | |
205 | u8 checksum; | |
206 | } __attribute__((packed)); | |
207 | ||
f453ba04 DA |
208 | #define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8)) |
209 | ||
210 | #endif /* __DRM_EDID_H__ */ |