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drm: bridge: dw-hdmi: Report connector status using callback
[linux-2.6-block.git] / include / drm / bridge / dw_hdmi.h
CommitLineData
2874c5fd 1/* SPDX-License-Identifier: GPL-2.0-or-later */
b21f4b65
AY		 2/*
3 * Copyright (C) 2011 Freescale Semiconductor, Inc.
b21f4b65
AY		 4 */
5
6#ifndef __DW_HDMI__
7#define __DW_HDMI__
8
a9c82d63
CYC		 9#include <sound/hdmi-codec.h>
10
428747ae
SR		 11struct drm_connector;
12struct drm_display_mode;
13struct drm_encoder;
b5814fff 14struct dw_hdmi;
428747ae 15struct platform_device;
b5814fff 16
def23aa7
NA		 17/**
18 * DOC: Supported input formats and encodings
19 *
20 * Depending on the Hardware configuration of the Controller IP, it supports
21 * a subset of the following input formats and encodings on its internal
22 * 48bit bus.
23 *
24 * +----------------------+----------------------------------+------------------------------+
38cb266a 25 * | Format Name | Format Code | Encodings |
def23aa7 26 * +----------------------+----------------------------------+------------------------------+
38cb266a 27 * | RGB 4:4:4 8bit | ``MEDIA_BUS_FMT_RGB888_1X24`` | ``V4L2_YCBCR_ENC_DEFAULT`` |
def23aa7 28 * +----------------------+----------------------------------+------------------------------+
38cb266a 29 * | RGB 4:4:4 10bits | ``MEDIA_BUS_FMT_RGB101010_1X30`` | ``V4L2_YCBCR_ENC_DEFAULT`` |
def23aa7 30 * +----------------------+----------------------------------+------------------------------+
38cb266a 31 * | RGB 4:4:4 12bits | ``MEDIA_BUS_FMT_RGB121212_1X36`` | ``V4L2_YCBCR_ENC_DEFAULT`` |
def23aa7 32 * +----------------------+----------------------------------+------------------------------+
38cb266a 33 * | RGB 4:4:4 16bits | ``MEDIA_BUS_FMT_RGB161616_1X48`` | ``V4L2_YCBCR_ENC_DEFAULT`` |
def23aa7 34 * +----------------------+----------------------------------+------------------------------+
38cb266a
JC		 35 * | YCbCr 4:4:4 8bit | ``MEDIA_BUS_FMT_YUV8_1X24`` | ``V4L2_YCBCR_ENC_601`` |
36 * | | | or ``V4L2_YCBCR_ENC_709`` |
37 * | | | or ``V4L2_YCBCR_ENC_XV601`` |
38 * | | | or ``V4L2_YCBCR_ENC_XV709`` |
def23aa7 39 * +----------------------+----------------------------------+------------------------------+
38cb266a
JC		 40 * | YCbCr 4:4:4 10bits | ``MEDIA_BUS_FMT_YUV10_1X30`` | ``V4L2_YCBCR_ENC_601`` |
41 * | | | or ``V4L2_YCBCR_ENC_709`` |
42 * | | | or ``V4L2_YCBCR_ENC_XV601`` |
43 * | | | or ``V4L2_YCBCR_ENC_XV709`` |
def23aa7 44 * +----------------------+----------------------------------+------------------------------+
38cb266a
JC		 45 * | YCbCr 4:4:4 12bits | ``MEDIA_BUS_FMT_YUV12_1X36`` | ``V4L2_YCBCR_ENC_601`` |
46 * | | | or ``V4L2_YCBCR_ENC_709`` |
47 * | | | or ``V4L2_YCBCR_ENC_XV601`` |
48 * | | | or ``V4L2_YCBCR_ENC_XV709`` |
def23aa7 49 * +----------------------+----------------------------------+------------------------------+
38cb266a
JC		 50 * | YCbCr 4:4:4 16bits | ``MEDIA_BUS_FMT_YUV16_1X48`` | ``V4L2_YCBCR_ENC_601`` |
51 * | | | or ``V4L2_YCBCR_ENC_709`` |
52 * | | | or ``V4L2_YCBCR_ENC_XV601`` |
53 * | | | or ``V4L2_YCBCR_ENC_XV709`` |
def23aa7 54 * +----------------------+----------------------------------+------------------------------+
38cb266a
JC		 55 * | YCbCr 4:2:2 8bit | ``MEDIA_BUS_FMT_UYVY8_1X16`` | ``V4L2_YCBCR_ENC_601`` |
56 * | | | or ``V4L2_YCBCR_ENC_709`` |
def23aa7 57 * +----------------------+----------------------------------+------------------------------+
38cb266a
JC		 58 * | YCbCr 4:2:2 10bits | ``MEDIA_BUS_FMT_UYVY10_1X20`` | ``V4L2_YCBCR_ENC_601`` |
59 * | | | or ``V4L2_YCBCR_ENC_709`` |
def23aa7 60 * +----------------------+----------------------------------+------------------------------+
38cb266a
JC		 61 * | YCbCr 4:2:2 12bits | ``MEDIA_BUS_FMT_UYVY12_1X24`` | ``V4L2_YCBCR_ENC_601`` |
62 * | | | or ``V4L2_YCBCR_ENC_709`` |
def23aa7 63 * +----------------------+----------------------------------+------------------------------+
38cb266a
JC		 64 * | YCbCr 4:2:0 8bit | ``MEDIA_BUS_FMT_UYYVYY8_0_5X24`` | ``V4L2_YCBCR_ENC_601`` |
65 * | | | or ``V4L2_YCBCR_ENC_709`` |
def23aa7 66 * +----------------------+----------------------------------+------------------------------+
38cb266a
JC		 67 * | YCbCr 4:2:0 10bits | ``MEDIA_BUS_FMT_UYYVYY10_0_5X30``| ``V4L2_YCBCR_ENC_601`` |
68 * | | | or ``V4L2_YCBCR_ENC_709`` |
def23aa7 69 * +----------------------+----------------------------------+------------------------------+
38cb266a
JC		 70 * | YCbCr 4:2:0 12bits | ``MEDIA_BUS_FMT_UYYVYY12_0_5X36``| ``V4L2_YCBCR_ENC_601`` |
71 * | | | or ``V4L2_YCBCR_ENC_709`` |
def23aa7 72 * +----------------------+----------------------------------+------------------------------+
38cb266a
JC		 73 * | YCbCr 4:2:0 16bits | ``MEDIA_BUS_FMT_UYYVYY16_0_5X48``| ``V4L2_YCBCR_ENC_601`` |
74 * | | | or ``V4L2_YCBCR_ENC_709`` |
def23aa7
NA		 75 * +----------------------+----------------------------------+------------------------------+
76 */
77
b21f4b65
AY		 78enum {
79 DW_HDMI_RES_8,
80 DW_HDMI_RES_10,
81 DW_HDMI_RES_12,
82 DW_HDMI_RES_MAX,
83};
84
faba6c3c
LP		 85enum dw_hdmi_phy_type {
86 DW_HDMI_PHY_DWC_HDMI_TX_PHY = 0x00,
87 DW_HDMI_PHY_DWC_MHL_PHY_HEAC = 0xb2,
88 DW_HDMI_PHY_DWC_MHL_PHY = 0xc2,
89 DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC = 0xe2,
90 DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY = 0xf2,
91 DW_HDMI_PHY_DWC_HDMI20_TX_PHY = 0xf3,
92 DW_HDMI_PHY_VENDOR_PHY = 0xfe,
93};
94
b21f4b65
AY		 95struct dw_hdmi_mpll_config {
96 unsigned long mpixelclock;
97 struct {
98 u16 cpce;
99 u16 gmp;
100 } res[DW_HDMI_RES_MAX];
101};
102
103struct dw_hdmi_curr_ctrl {
104 unsigned long mpixelclock;
105 u16 curr[DW_HDMI_RES_MAX];
106};
107
034705a4 108struct dw_hdmi_phy_config {
b21f4b65
AY		 109 unsigned long mpixelclock;
110 u16 sym_ctr; /*clock symbol and transmitter control*/
111 u16 term; /*transmission termination value*/
034705a4 112 u16 vlev_ctr; /* voltage level control */
b21f4b65
AY		 113};
114
f1585f6e
LP		 115struct dw_hdmi_phy_ops {
116 int (*init)(struct dw_hdmi *hdmi, void *data,
117 struct drm_display_mode *mode);
118 void (*disable)(struct dw_hdmi *hdmi, void *data);
119 enum drm_connector_status (*read_hpd)(struct dw_hdmi *hdmi, void *data);
386d3299
NA		 120 void (*update_hpd)(struct dw_hdmi *hdmi, void *data,
121 bool force, bool disabled, bool rxsense);
122 void (*setup_hpd)(struct dw_hdmi *hdmi, void *data);
f1585f6e
LP		 123};
124
b21f4b65 125struct dw_hdmi_plat_data {
80e2f979 126 struct regmap *regm;
f1585f6e 127 enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
b0febde7 128 const struct drm_display_mode *mode);
def23aa7
NA		 129 unsigned long input_bus_format;
130 unsigned long input_bus_encoding;
f1585f6e
LP		 131
132 /* Vendor PHY support */
133 const struct dw_hdmi_phy_ops *phy_ops;
134 const char *phy_name;
135 void *phy_data;
8faff374 136 unsigned int phy_force_vendor;
f1585f6e
LP		 137
138 /* Synopsys PHY support */
b21f4b65
AY		 139 const struct dw_hdmi_mpll_config *mpll_cfg;
140 const struct dw_hdmi_curr_ctrl *cur_ctr;
034705a4 141 const struct dw_hdmi_phy_config *phy_config;
2ef9dfed
KB		 142 int (*configure_phy)(struct dw_hdmi *hdmi,
143 const struct dw_hdmi_plat_data *pdata,
144 unsigned long mpixelclock);
b21f4b65
AY		 145};
146
eea034af
JS		 147struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
148 const struct dw_hdmi_plat_data *plat_data);
149void dw_hdmi_remove(struct dw_hdmi *hdmi);
150void dw_hdmi_unbind(struct dw_hdmi *hdmi);
151struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev,
152 struct drm_encoder *encoder,
153 const struct dw_hdmi_plat_data *plat_data);
b5814fff 154
99d02ed5
DA		 155void dw_hdmi_resume(struct dw_hdmi *hdmi);
156
c32048d9 157void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense);
386d3299 158
a9c82d63
CYC		 159int dw_hdmi_set_plugged_cb(struct dw_hdmi *hdmi, hdmi_codec_plugged_cb fn,
160 struct device *codec_dev);
b5814fff 161void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate);
2a2a3d2f
JB		 162void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt);
163void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca);
b90120a9
RK		 164void dw_hdmi_audio_enable(struct dw_hdmi *hdmi);
165void dw_hdmi_audio_disable(struct dw_hdmi *hdmi);
264fce6c 166void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi);
b5814fff 167
2ef9dfed 168/* PHY configuration */
5765916a 169void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address);
2ef9dfed
KB		 170void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
171 unsigned char addr);
172
5765916a
JS		 173void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable);
174void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable);
175void dw_hdmi_phy_reset(struct dw_hdmi *hdmi);
176
177enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi,
178 void *data);
179void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data,
180 bool force, bool disabled, bool rxsense);
181void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data);
182
b21f4b65 183#endif /* __IMX_HDMI_H__ */
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