[linux-2.6-block.git] / include / drm / bridge / dw_hdmi.h

/*
 * Copyright (C) 2011 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#ifndef __DW_HDMI__
#define __DW_HDMI__

#include <drm/drmP.h>

enum {
	DW_HDMI_RES_8,
	DW_HDMI_RES_10,
	DW_HDMI_RES_12,
	DW_HDMI_RES_MAX,
};

enum dw_hdmi_devtype {
	IMX6Q_HDMI,
	IMX6DL_HDMI,
	RK3288_HDMI,
};

struct dw_hdmi_mpll_config {
	unsigned long mpixelclock;
	struct {
		u16 cpce;
		u16 gmp;
	} res[DW_HDMI_RES_MAX];
};

struct dw_hdmi_curr_ctrl {
	unsigned long mpixelclock;
	u16 curr[DW_HDMI_RES_MAX];
};

struct dw_hdmi_phy_config {
	unsigned long mpixelclock;
	u16 sym_ctr;    /*clock symbol and transmitter control*/
	u16 term;       /*transmission termination value*/
	u16 vlev_ctr;   /* voltage level control */
};

struct dw_hdmi_plat_data {
	enum dw_hdmi_devtype dev_type;
	const struct dw_hdmi_mpll_config *mpll_cfg;
	const struct dw_hdmi_curr_ctrl *cur_ctr;
	const struct dw_hdmi_phy_config *phy_config;
	enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
					   struct drm_display_mode *mode);
};

void dw_hdmi_unbind(struct device *dev, struct device *master, void *data);
int dw_hdmi_bind(struct device *dev, struct device *master,
		 void *data, struct drm_encoder *encoder,
		 struct resource *iores, int irq,
		 const struct dw_hdmi_plat_data *plat_data);
#endif /* __IMX_HDMI_H__ */
Commit	Line	Data
b21f4b65 AY	1	/*
	2	* Copyright (C) 2011 Freescale Semiconductor, Inc.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*/
	9
	10	#ifndef __DW_HDMI__
	11	#define __DW_HDMI__
	12
	13	#include <drm/drmP.h>
	14
	15	enum {
	16	DW_HDMI_RES_8,
	17	DW_HDMI_RES_10,
	18	DW_HDMI_RES_12,
	19	DW_HDMI_RES_MAX,
	20	};
	21
	22	enum dw_hdmi_devtype {
	23	IMX6Q_HDMI,
	24	IMX6DL_HDMI,
12b9f204	25	RK3288_HDMI,
b21f4b65 AY	26	};
	27
	28	struct dw_hdmi_mpll_config {
	29	unsigned long mpixelclock;
	30	struct {
	31	u16 cpce;
	32	u16 gmp;
	33	} res[DW_HDMI_RES_MAX];
	34	};
	35
	36	struct dw_hdmi_curr_ctrl {
	37	unsigned long mpixelclock;
	38	u16 curr[DW_HDMI_RES_MAX];
	39	};
	40
034705a4	41	struct dw_hdmi_phy_config {
b21f4b65 AY	42	unsigned long mpixelclock;
	43	u16 sym_ctr; /clock symbol and transmitter control/
	44	u16 term; /transmission termination value/
034705a4	45	u16 vlev_ctr; /* voltage level control */
b21f4b65 AY	46	};
	47
	48	struct dw_hdmi_plat_data {
	49	enum dw_hdmi_devtype dev_type;
	50	const struct dw_hdmi_mpll_config *mpll_cfg;
	51	const struct dw_hdmi_curr_ctrl *cur_ctr;
034705a4	52	const struct dw_hdmi_phy_config *phy_config;
b21f4b65 AY	53	enum drm_mode_status (mode_valid)(struct drm_connector connector,
	54	struct drm_display_mode *mode);
	55	};
	56
	57	void dw_hdmi_unbind(struct device dev, struct device master, void *data);
	58	int dw_hdmi_bind(struct device dev, struct device master,
	59	void data, struct drm_encoder encoder,
	60	struct resource *iores, int irq,
	61	const struct dw_hdmi_plat_data *plat_data);
	62	#endif /* __IMX_HDMI_H__ */