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9839c6b8 | 1 | /* |
9839c6b8 TL |
2 | * OMAP Dual-Mode Timers |
3 | * | |
7f317d34 | 4 | * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/ |
eddb1262 TG |
5 | * Tarun Kanti DebBarma <tarun.kanti@ti.com> |
6 | * Thara Gopinath <thara@ti.com> | |
7 | * | |
8 | * Platform device conversion and hwmod support. | |
9 | * | |
9839c6b8 TL |
10 | * Copyright (C) 2005 Nokia Corporation |
11 | * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com> | |
77900a2f | 12 | * PWM and clock framwork support by Timo Teras. |
9839c6b8 TL |
13 | * |
14 | * This program is free software; you can redistribute it and/or modify it | |
15 | * under the terms of the GNU General Public License as published by the | |
16 | * Free Software Foundation; either version 2 of the License, or (at your | |
17 | * option) any later version. | |
18 | * | |
19 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
20 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
21 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
22 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |
23 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
24 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
27 | * | |
28 | * You should have received a copy of the GNU General Public License along | |
29 | * with this program; if not, write to the Free Software Foundation, Inc., | |
30 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
31 | */ | |
32 | ||
caf64f2f | 33 | #include <linux/delay.h> |
a7cd4b08 | 34 | #include <linux/io.h> |
97933d6c | 35 | #include <linux/platform_device.h> |
caf64f2f | 36 | |
f7bda9ee K |
37 | #ifndef __CLOCKSOURCE_DMTIMER_H |
38 | #define __CLOCKSOURCE_DMTIMER_H | |
9839c6b8 | 39 | |
77900a2f TT |
40 | /* clock sources */ |
41 | #define OMAP_TIMER_SRC_SYS_CLK 0x00 | |
42 | #define OMAP_TIMER_SRC_32_KHZ 0x01 | |
43 | #define OMAP_TIMER_SRC_EXT_CLK 0x02 | |
9839c6b8 | 44 | |
77900a2f TT |
45 | /* timer interrupt enable bits */ |
46 | #define OMAP_TIMER_INT_CAPTURE (1 << 2) | |
47 | #define OMAP_TIMER_INT_OVERFLOW (1 << 1) | |
48 | #define OMAP_TIMER_INT_MATCH (1 << 0) | |
9839c6b8 | 49 | |
77900a2f TT |
50 | /* trigger types */ |
51 | #define OMAP_TIMER_TRIGGER_NONE 0x00 | |
52 | #define OMAP_TIMER_TRIGGER_OVERFLOW 0x01 | |
53 | #define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02 | |
9839c6b8 | 54 | |
971d0254 JH |
55 | /* posted mode types */ |
56 | #define OMAP_TIMER_NONPOSTED 0x00 | |
57 | #define OMAP_TIMER_POSTED 0x01 | |
58 | ||
c345c8b0 TKD |
59 | /* timer capabilities used in hwmod database */ |
60 | #define OMAP_TIMER_SECURE 0x80000000 | |
61 | #define OMAP_TIMER_ALWON 0x40000000 | |
62 | #define OMAP_TIMER_HAS_PWM 0x20000000 | |
6615975b | 63 | #define OMAP_TIMER_NEEDS_RESET 0x10000000 |
5c3e4ec4 | 64 | #define OMAP_TIMER_HAS_DSP_IRQ 0x08000000 |
c345c8b0 | 65 | |
bfd6d021 JH |
66 | /* |
67 | * timer errata flags | |
68 | * | |
69 | * Errata i103/i767 impacts all OMAP3/4/5 devices including AM33xx. This | |
70 | * errata prevents us from using posted mode on these devices, unless the | |
71 | * timer counter register is never read. For more details please refer to | |
72 | * the OMAP3/4/5 errata documents. | |
73 | */ | |
74 | #define OMAP_TIMER_ERRATA_I103_I767 0x80000000 | |
75 | ||
b481113a | 76 | struct timer_regs { |
9517c577 | 77 | u32 ocp_cfg; |
b481113a | 78 | u32 tidr; |
b481113a TKD |
79 | u32 tier; |
80 | u32 twer; | |
81 | u32 tclr; | |
82 | u32 tcrr; | |
83 | u32 tldr; | |
84 | u32 ttrg; | |
85 | u32 twps; | |
86 | u32 tmar; | |
87 | u32 tcar1; | |
88 | u32 tsicr; | |
89 | u32 tcar2; | |
90 | u32 tpir; | |
91 | u32 tnir; | |
92 | u32 tcvr; | |
93 | u32 tocr; | |
94 | u32 towr; | |
95 | }; | |
96 | ||
755ae860 JH |
97 | struct omap_dm_timer { |
98 | int id; | |
99 | int irq; | |
100 | struct clk *fclk; | |
101 | ||
102 | void __iomem *io_base; | |
f32bdac1 TL |
103 | int irq_stat; /* TISR/IRQSTATUS interrupt status */ |
104 | int irq_ena; /* irq enable */ | |
105 | int irq_dis; /* irq disable, only on v2 ip */ | |
755ae860 JH |
106 | void __iomem *pend; /* write pending */ |
107 | void __iomem *func_base; /* function register base */ | |
108 | ||
5e20931c | 109 | atomic_t enabled; |
755ae860 JH |
110 | unsigned long rate; |
111 | unsigned reserved:1; | |
112 | unsigned posted:1; | |
113 | struct timer_regs context; | |
755ae860 JH |
114 | int revision; |
115 | u32 capability; | |
116 | u32 errata; | |
117 | struct platform_device *pdev; | |
118 | struct list_head node; | |
b34677b0 | 119 | struct notifier_block nb; |
755ae860 JH |
120 | }; |
121 | ||
77900a2f TT |
122 | int omap_dm_timer_get_irq(struct omap_dm_timer *timer); |
123 | ||
124 | u32 omap_dm_timer_modify_idlect_mask(u32 inputmask); | |
b65d1248 | 125 | |
ec97489d TL |
126 | /* |
127 | * Do not use the defines below, they are not needed. They should be only | |
128 | * used by dmtimer.c and sys_timer related code. | |
129 | */ | |
130 | ||
ee17f114 TL |
131 | /* |
132 | * The interrupt registers are different between v1 and v2 ip. | |
133 | * These registers are offsets from timer->iobase. | |
134 | */ | |
135 | #define OMAP_TIMER_ID_OFFSET 0x00 | |
136 | #define OMAP_TIMER_OCP_CFG_OFFSET 0x10 | |
137 | ||
138 | #define OMAP_TIMER_V1_SYS_STAT_OFFSET 0x14 | |
139 | #define OMAP_TIMER_V1_STAT_OFFSET 0x18 | |
140 | #define OMAP_TIMER_V1_INT_EN_OFFSET 0x1c | |
141 | ||
142 | #define OMAP_TIMER_V2_IRQSTATUS_RAW 0x24 | |
143 | #define OMAP_TIMER_V2_IRQSTATUS 0x28 | |
144 | #define OMAP_TIMER_V2_IRQENABLE_SET 0x2c | |
145 | #define OMAP_TIMER_V2_IRQENABLE_CLR 0x30 | |
146 | ||
147 | /* | |
148 | * The functional registers have a different base on v1 and v2 ip. | |
149 | * These registers are offsets from timer->func_base. The func_base | |
150 | * is samae as io_base for v1 and io_base + 0x14 for v2 ip. | |
151 | * | |
152 | */ | |
153 | #define OMAP_TIMER_V2_FUNC_OFFSET 0x14 | |
154 | ||
ec97489d TL |
155 | #define _OMAP_TIMER_WAKEUP_EN_OFFSET 0x20 |
156 | #define _OMAP_TIMER_CTRL_OFFSET 0x24 | |
157 | #define OMAP_TIMER_CTRL_GPOCFG (1 << 14) | |
158 | #define OMAP_TIMER_CTRL_CAPTMODE (1 << 13) | |
159 | #define OMAP_TIMER_CTRL_PT (1 << 12) | |
160 | #define OMAP_TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8) | |
161 | #define OMAP_TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8) | |
162 | #define OMAP_TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8) | |
163 | #define OMAP_TIMER_CTRL_SCPWM (1 << 7) | |
164 | #define OMAP_TIMER_CTRL_CE (1 << 6) /* compare enable */ | |
165 | #define OMAP_TIMER_CTRL_PRE (1 << 5) /* prescaler enable */ | |
166 | #define OMAP_TIMER_CTRL_PTV_SHIFT 2 /* prescaler value shift */ | |
167 | #define OMAP_TIMER_CTRL_POSTED (1 << 2) | |
168 | #define OMAP_TIMER_CTRL_AR (1 << 1) /* auto-reload enable */ | |
169 | #define OMAP_TIMER_CTRL_ST (1 << 0) /* start timer */ | |
170 | #define _OMAP_TIMER_COUNTER_OFFSET 0x28 | |
171 | #define _OMAP_TIMER_LOAD_OFFSET 0x2c | |
172 | #define _OMAP_TIMER_TRIGGER_OFFSET 0x30 | |
173 | #define _OMAP_TIMER_WRITE_PEND_OFFSET 0x34 | |
174 | #define WP_NONE 0 /* no write pending bit */ | |
175 | #define WP_TCLR (1 << 0) | |
176 | #define WP_TCRR (1 << 1) | |
177 | #define WP_TLDR (1 << 2) | |
178 | #define WP_TTGR (1 << 3) | |
179 | #define WP_TMAR (1 << 4) | |
180 | #define WP_TPIR (1 << 5) | |
181 | #define WP_TNIR (1 << 6) | |
182 | #define WP_TCVR (1 << 7) | |
183 | #define WP_TOCR (1 << 8) | |
184 | #define WP_TOWR (1 << 9) | |
185 | #define _OMAP_TIMER_MATCH_OFFSET 0x38 | |
186 | #define _OMAP_TIMER_CAPTURE_OFFSET 0x3c | |
187 | #define _OMAP_TIMER_IF_CTRL_OFFSET 0x40 | |
188 | #define _OMAP_TIMER_CAPTURE2_OFFSET 0x44 /* TCAR2, 34xx only */ | |
189 | #define _OMAP_TIMER_TICK_POS_OFFSET 0x48 /* TPIR, 34xx only */ | |
190 | #define _OMAP_TIMER_TICK_NEG_OFFSET 0x4c /* TNIR, 34xx only */ | |
191 | #define _OMAP_TIMER_TICK_COUNT_OFFSET 0x50 /* TCVR, 34xx only */ | |
192 | #define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET 0x54 /* TOCR, 34xx only */ | |
193 | #define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET 0x58 /* TOWR, 34xx only */ | |
194 | ||
195 | /* register offsets with the write pending bit encoded */ | |
196 | #define WPSHIFT 16 | |
197 | ||
ec97489d TL |
198 | #define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \ |
199 | | (WP_NONE << WPSHIFT)) | |
200 | ||
201 | #define OMAP_TIMER_CTRL_REG (_OMAP_TIMER_CTRL_OFFSET \ | |
202 | | (WP_TCLR << WPSHIFT)) | |
203 | ||
204 | #define OMAP_TIMER_COUNTER_REG (_OMAP_TIMER_COUNTER_OFFSET \ | |
205 | | (WP_TCRR << WPSHIFT)) | |
206 | ||
207 | #define OMAP_TIMER_LOAD_REG (_OMAP_TIMER_LOAD_OFFSET \ | |
208 | | (WP_TLDR << WPSHIFT)) | |
209 | ||
210 | #define OMAP_TIMER_TRIGGER_REG (_OMAP_TIMER_TRIGGER_OFFSET \ | |
211 | | (WP_TTGR << WPSHIFT)) | |
212 | ||
213 | #define OMAP_TIMER_WRITE_PEND_REG (_OMAP_TIMER_WRITE_PEND_OFFSET \ | |
214 | | (WP_NONE << WPSHIFT)) | |
215 | ||
216 | #define OMAP_TIMER_MATCH_REG (_OMAP_TIMER_MATCH_OFFSET \ | |
217 | | (WP_TMAR << WPSHIFT)) | |
218 | ||
219 | #define OMAP_TIMER_CAPTURE_REG (_OMAP_TIMER_CAPTURE_OFFSET \ | |
220 | | (WP_NONE << WPSHIFT)) | |
221 | ||
222 | #define OMAP_TIMER_IF_CTRL_REG (_OMAP_TIMER_IF_CTRL_OFFSET \ | |
223 | | (WP_NONE << WPSHIFT)) | |
224 | ||
225 | #define OMAP_TIMER_CAPTURE2_REG (_OMAP_TIMER_CAPTURE2_OFFSET \ | |
226 | | (WP_NONE << WPSHIFT)) | |
227 | ||
228 | #define OMAP_TIMER_TICK_POS_REG (_OMAP_TIMER_TICK_POS_OFFSET \ | |
229 | | (WP_TPIR << WPSHIFT)) | |
230 | ||
231 | #define OMAP_TIMER_TICK_NEG_REG (_OMAP_TIMER_TICK_NEG_OFFSET \ | |
232 | | (WP_TNIR << WPSHIFT)) | |
233 | ||
234 | #define OMAP_TIMER_TICK_COUNT_REG (_OMAP_TIMER_TICK_COUNT_OFFSET \ | |
235 | | (WP_TCVR << WPSHIFT)) | |
236 | ||
237 | #define OMAP_TIMER_TICK_INT_MASK_SET_REG \ | |
238 | (_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT)) | |
239 | ||
240 | #define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \ | |
241 | (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT)) | |
242 | ||
f7bda9ee | 243 | #endif /* __CLOCKSOURCE_DMTIMER_H */ |