[linux-2.6-block.git] / include / clocksource / timer-ti-dm.h

/*
 * OMAP Dual-Mode Timers
 *
 * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
 * Tarun Kanti DebBarma <tarun.kanti@ti.com>
 * Thara Gopinath <thara@ti.com>
 *
 * Platform device conversion and hwmod support.
 *
 * Copyright (C) 2005 Nokia Corporation
 * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com>
 * PWM and clock framwork support by Timo Teras.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 *
 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * You should have received a copy of the  GNU General Public License along
 * with this program; if not, write  to the Free Software Foundation, Inc.,
 * 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/delay.h>
#include <linux/io.h>
#include <linux/platform_device.h>

#ifndef __CLOCKSOURCE_DMTIMER_H
#define __CLOCKSOURCE_DMTIMER_H

/* clock sources */
#define OMAP_TIMER_SRC_SYS_CLK			0x00
#define OMAP_TIMER_SRC_32_KHZ			0x01
#define OMAP_TIMER_SRC_EXT_CLK			0x02

/* timer interrupt enable bits */
#define OMAP_TIMER_INT_CAPTURE			(1 << 2)
#define OMAP_TIMER_INT_OVERFLOW			(1 << 1)
#define OMAP_TIMER_INT_MATCH			(1 << 0)

/* trigger types */
#define OMAP_TIMER_TRIGGER_NONE			0x00
#define OMAP_TIMER_TRIGGER_OVERFLOW		0x01
#define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE	0x02

/* posted mode types */
#define OMAP_TIMER_NONPOSTED			0x00
#define OMAP_TIMER_POSTED			0x01

/* timer capabilities used in hwmod database */
#define OMAP_TIMER_SECURE				0x80000000
#define OMAP_TIMER_ALWON				0x40000000
#define OMAP_TIMER_HAS_PWM				0x20000000
#define OMAP_TIMER_NEEDS_RESET				0x10000000
#define OMAP_TIMER_HAS_DSP_IRQ				0x08000000

/*
 * timer errata flags
 *
 * Errata i103/i767 impacts all OMAP3/4/5 devices including AM33xx. This
 * errata prevents us from using posted mode on these devices, unless the
 * timer counter register is never read. For more details please refer to
 * the OMAP3/4/5 errata documents.
 */
#define OMAP_TIMER_ERRATA_I103_I767			0x80000000

struct timer_regs {
	u32 ocp_cfg;
	u32 tidr;
	u32 tier;
	u32 twer;
	u32 tclr;
	u32 tcrr;
	u32 tldr;
	u32 ttrg;
	u32 twps;
	u32 tmar;
	u32 tcar1;
	u32 tsicr;
	u32 tcar2;
	u32 tpir;
	u32 tnir;
	u32 tcvr;
	u32 tocr;
	u32 towr;
};

struct omap_dm_timer {
	int id;
	int irq;
	struct clk *fclk;

	void __iomem	*io_base;
	void __iomem	*irq_stat;	/* TISR/IRQSTATUS interrupt status */
	void __iomem	*irq_ena;	/* irq enable */
	void __iomem	*irq_dis;	/* irq disable, only on v2 ip */
	void __iomem	*pend;		/* write pending */
	void __iomem	*func_base;	/* function register base */

	atomic_t enabled;
	unsigned long rate;
	unsigned reserved:1;
	unsigned posted:1;
	struct timer_regs context;
	int revision;
	u32 capability;
	u32 errata;
	struct platform_device *pdev;
	struct list_head node;
	struct notifier_block nb;
};

int omap_dm_timer_reserve_systimer(int id);
struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap);

int omap_dm_timer_get_irq(struct omap_dm_timer *timer);

u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);

int omap_dm_timer_trigger(struct omap_dm_timer *timer);

int omap_dm_timers_active(void);

/*
 * Do not use the defines below, they are not needed. They should be only
 * used by dmtimer.c and sys_timer related code.
 */

/*
 * The interrupt registers are different between v1 and v2 ip.
 * These registers are offsets from timer->iobase.
 */
#define OMAP_TIMER_ID_OFFSET		0x00
#define OMAP_TIMER_OCP_CFG_OFFSET	0x10

#define OMAP_TIMER_V1_SYS_STAT_OFFSET	0x14
#define OMAP_TIMER_V1_STAT_OFFSET	0x18
#define OMAP_TIMER_V1_INT_EN_OFFSET	0x1c

#define OMAP_TIMER_V2_IRQSTATUS_RAW	0x24
#define OMAP_TIMER_V2_IRQSTATUS		0x28
#define OMAP_TIMER_V2_IRQENABLE_SET	0x2c
#define OMAP_TIMER_V2_IRQENABLE_CLR	0x30

/*
 * The functional registers have a different base on v1 and v2 ip.
 * These registers are offsets from timer->func_base. The func_base
 * is samae as io_base for v1 and io_base + 0x14 for v2 ip.
 *
 */
#define OMAP_TIMER_V2_FUNC_OFFSET		0x14

#define _OMAP_TIMER_WAKEUP_EN_OFFSET	0x20
#define _OMAP_TIMER_CTRL_OFFSET		0x24
#define		OMAP_TIMER_CTRL_GPOCFG		(1 << 14)
#define		OMAP_TIMER_CTRL_CAPTMODE	(1 << 13)
#define		OMAP_TIMER_CTRL_PT		(1 << 12)
#define		OMAP_TIMER_CTRL_TCM_LOWTOHIGH	(0x1 << 8)
#define		OMAP_TIMER_CTRL_TCM_HIGHTOLOW	(0x2 << 8)
#define		OMAP_TIMER_CTRL_TCM_BOTHEDGES	(0x3 << 8)
#define		OMAP_TIMER_CTRL_SCPWM		(1 << 7)
#define		OMAP_TIMER_CTRL_CE		(1 << 6) /* compare enable */
#define		OMAP_TIMER_CTRL_PRE		(1 << 5) /* prescaler enable */
#define		OMAP_TIMER_CTRL_PTV_SHIFT	2 /* prescaler value shift */
#define		OMAP_TIMER_CTRL_POSTED		(1 << 2)
#define		OMAP_TIMER_CTRL_AR		(1 << 1) /* auto-reload enable */
#define		OMAP_TIMER_CTRL_ST		(1 << 0) /* start timer */
#define _OMAP_TIMER_COUNTER_OFFSET	0x28
#define _OMAP_TIMER_LOAD_OFFSET		0x2c
#define _OMAP_TIMER_TRIGGER_OFFSET	0x30
#define _OMAP_TIMER_WRITE_PEND_OFFSET	0x34
#define		WP_NONE			0	/* no write pending bit */
#define		WP_TCLR			(1 << 0)
#define		WP_TCRR			(1 << 1)
#define		WP_TLDR			(1 << 2)
#define		WP_TTGR			(1 << 3)
#define		WP_TMAR			(1 << 4)
#define		WP_TPIR			(1 << 5)
#define		WP_TNIR			(1 << 6)
#define		WP_TCVR			(1 << 7)
#define		WP_TOCR			(1 << 8)
#define		WP_TOWR			(1 << 9)
#define _OMAP_TIMER_MATCH_OFFSET	0x38
#define _OMAP_TIMER_CAPTURE_OFFSET	0x3c
#define _OMAP_TIMER_IF_CTRL_OFFSET	0x40
#define _OMAP_TIMER_CAPTURE2_OFFSET		0x44	/* TCAR2, 34xx only */
#define _OMAP_TIMER_TICK_POS_OFFSET		0x48	/* TPIR, 34xx only */
#define _OMAP_TIMER_TICK_NEG_OFFSET		0x4c	/* TNIR, 34xx only */
#define _OMAP_TIMER_TICK_COUNT_OFFSET		0x50	/* TCVR, 34xx only */
#define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET	0x54	/* TOCR, 34xx only */
#define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET	0x58	/* TOWR, 34xx only */

/* register offsets with the write pending bit encoded */
#define	WPSHIFT					16

#define OMAP_TIMER_WAKEUP_EN_REG		(_OMAP_TIMER_WAKEUP_EN_OFFSET \
							| (WP_NONE << WPSHIFT))

#define OMAP_TIMER_CTRL_REG			(_OMAP_TIMER_CTRL_OFFSET \
							| (WP_TCLR << WPSHIFT))

#define OMAP_TIMER_COUNTER_REG			(_OMAP_TIMER_COUNTER_OFFSET \
							| (WP_TCRR << WPSHIFT))

#define OMAP_TIMER_LOAD_REG			(_OMAP_TIMER_LOAD_OFFSET \
							| (WP_TLDR << WPSHIFT))

#define OMAP_TIMER_TRIGGER_REG			(_OMAP_TIMER_TRIGGER_OFFSET \
							| (WP_TTGR << WPSHIFT))

#define OMAP_TIMER_WRITE_PEND_REG		(_OMAP_TIMER_WRITE_PEND_OFFSET \
							| (WP_NONE << WPSHIFT))

#define OMAP_TIMER_MATCH_REG			(_OMAP_TIMER_MATCH_OFFSET \
							| (WP_TMAR << WPSHIFT))

#define OMAP_TIMER_CAPTURE_REG			(_OMAP_TIMER_CAPTURE_OFFSET \
							| (WP_NONE << WPSHIFT))

#define OMAP_TIMER_IF_CTRL_REG			(_OMAP_TIMER_IF_CTRL_OFFSET \
							| (WP_NONE << WPSHIFT))

#define OMAP_TIMER_CAPTURE2_REG			(_OMAP_TIMER_CAPTURE2_OFFSET \
							| (WP_NONE << WPSHIFT))

#define OMAP_TIMER_TICK_POS_REG			(_OMAP_TIMER_TICK_POS_OFFSET \
							| (WP_TPIR << WPSHIFT))

#define OMAP_TIMER_TICK_NEG_REG			(_OMAP_TIMER_TICK_NEG_OFFSET \
							| (WP_TNIR << WPSHIFT))

#define OMAP_TIMER_TICK_COUNT_REG		(_OMAP_TIMER_TICK_COUNT_OFFSET \
							| (WP_TCVR << WPSHIFT))

#define OMAP_TIMER_TICK_INT_MASK_SET_REG				\
		(_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))

#define OMAP_TIMER_TICK_INT_MASK_COUNT_REG				\
		(_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))

#endif /* __CLOCKSOURCE_DMTIMER_H */
Commit	Line	Data
9839c6b8	1	/*
9839c6b8 TL	2	* OMAP Dual-Mode Timers
9839c6b8 TL	3	*
7f317d34	4	* Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
eddb1262 TG	5	* Tarun Kanti DebBarma <tarun.kanti@ti.com>
	6	* Thara Gopinath <thara@ti.com>
	7	*
	8	* Platform device conversion and hwmod support.
	9	*
9839c6b8 TL	10	* Copyright (C) 2005 Nokia Corporation
9839c6b8 TL	11	* Author: Lauri Leukkunen <lauri.leukkunen@nokia.com>
77900a2f	12	* PWM and clock framwork support by Timo Teras.
9839c6b8 TL	13	*
	14	* This program is free software; you can redistribute it and/or modify it
	15	* under the terms of the GNU General Public License as published by the
	16	* Free Software Foundation; either version 2 of the License, or (at your
	17	* option) any later version.
	18	*
	19	* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
	20	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
	21	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
	22	* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
	23	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
	24	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	27	*
	28	* You should have received a copy of the GNU General Public License along
	29	* with this program; if not, write to the Free Software Foundation, Inc.,
	30	* 675 Mass Ave, Cambridge, MA 02139, USA.
	31	*/
	32
caf64f2f	33	#include <linux/delay.h>
a7cd4b08	34	#include <linux/io.h>
97933d6c	35	#include <linux/platform_device.h>
caf64f2f	36
f7bda9ee K	37	#ifndef __CLOCKSOURCE_DMTIMER_H
f7bda9ee K	38	#define __CLOCKSOURCE_DMTIMER_H
9839c6b8	39
77900a2f TT	40	/* clock sources */
	41	#define OMAP_TIMER_SRC_SYS_CLK 0x00
	42	#define OMAP_TIMER_SRC_32_KHZ 0x01
	43	#define OMAP_TIMER_SRC_EXT_CLK 0x02
9839c6b8	44
77900a2f TT	45	/* timer interrupt enable bits */
	46	#define OMAP_TIMER_INT_CAPTURE (1 << 2)
	47	#define OMAP_TIMER_INT_OVERFLOW (1 << 1)
	48	#define OMAP_TIMER_INT_MATCH (1 << 0)
9839c6b8	49
77900a2f TT	50	/* trigger types */
	51	#define OMAP_TIMER_TRIGGER_NONE 0x00
	52	#define OMAP_TIMER_TRIGGER_OVERFLOW 0x01
	53	#define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
9839c6b8	54
971d0254 JH	55	/* posted mode types */
	56	#define OMAP_TIMER_NONPOSTED 0x00
	57	#define OMAP_TIMER_POSTED 0x01
	58
c345c8b0 TKD	59	/* timer capabilities used in hwmod database */
	60	#define OMAP_TIMER_SECURE 0x80000000
	61	#define OMAP_TIMER_ALWON 0x40000000
	62	#define OMAP_TIMER_HAS_PWM 0x20000000
6615975b	63	#define OMAP_TIMER_NEEDS_RESET 0x10000000
5c3e4ec4	64	#define OMAP_TIMER_HAS_DSP_IRQ 0x08000000
c345c8b0	65
bfd6d021 JH	66	/*
	67	* timer errata flags
	68	*
	69	* Errata i103/i767 impacts all OMAP3/4/5 devices including AM33xx. This
	70	* errata prevents us from using posted mode on these devices, unless the
	71	* timer counter register is never read. For more details please refer to
	72	* the OMAP3/4/5 errata documents.
	73	*/
	74	#define OMAP_TIMER_ERRATA_I103_I767 0x80000000
	75
b481113a	76	struct timer_regs {
9517c577	77	u32 ocp_cfg;
b481113a	78	u32 tidr;
b481113a TKD	79	u32 tier;
	80	u32 twer;
	81	u32 tclr;
	82	u32 tcrr;
	83	u32 tldr;
	84	u32 ttrg;
	85	u32 twps;
	86	u32 tmar;
	87	u32 tcar1;
	88	u32 tsicr;
	89	u32 tcar2;
	90	u32 tpir;
	91	u32 tnir;
	92	u32 tcvr;
	93	u32 tocr;
	94	u32 towr;
	95	};
	96
755ae860 JH	97	struct omap_dm_timer {
	98	int id;
	99	int irq;
	100	struct clk *fclk;
	101
	102	void __iomem *io_base;
	103	void __iomem irq_stat; / TISR/IRQSTATUS interrupt status */
	104	void __iomem irq_ena; / irq enable */
	105	void __iomem irq_dis; / irq disable, only on v2 ip */
	106	void __iomem pend; / write pending */
	107	void __iomem func_base; / function register base */
	108
5e20931c	109	atomic_t enabled;
755ae860 JH	110	unsigned long rate;
	111	unsigned reserved:1;
	112	unsigned posted:1;
	113	struct timer_regs context;
755ae860 JH	114	int revision;
	115	u32 capability;
	116	u32 errata;
	117	struct platform_device *pdev;
	118	struct list_head node;
b34677b0	119	struct notifier_block nb;
755ae860 JH	120	};
755ae860 JH	121
b7b4ff76	122	int omap_dm_timer_reserve_systimer(int id);
373fe0bd	123	struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap);
9839c6b8	124
77900a2f TT	125	int omap_dm_timer_get_irq(struct omap_dm_timer *timer);
	126
	127	u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
b65d1248	128
ab4eb8b0	129	int omap_dm_timer_trigger(struct omap_dm_timer *timer);
9839c6b8 TL	130
	131	int omap_dm_timers_active(void);
	132
ec97489d TL	133	/*
	134	* Do not use the defines below, they are not needed. They should be only
	135	* used by dmtimer.c and sys_timer related code.
	136	*/
	137
ee17f114 TL	138	/*
	139	* The interrupt registers are different between v1 and v2 ip.
	140	* These registers are offsets from timer->iobase.
	141	*/
	142	#define OMAP_TIMER_ID_OFFSET 0x00
	143	#define OMAP_TIMER_OCP_CFG_OFFSET 0x10
	144
	145	#define OMAP_TIMER_V1_SYS_STAT_OFFSET 0x14
	146	#define OMAP_TIMER_V1_STAT_OFFSET 0x18
	147	#define OMAP_TIMER_V1_INT_EN_OFFSET 0x1c
	148
	149	#define OMAP_TIMER_V2_IRQSTATUS_RAW 0x24
	150	#define OMAP_TIMER_V2_IRQSTATUS 0x28
	151	#define OMAP_TIMER_V2_IRQENABLE_SET 0x2c
	152	#define OMAP_TIMER_V2_IRQENABLE_CLR 0x30
	153
	154	/*
	155	* The functional registers have a different base on v1 and v2 ip.
	156	* These registers are offsets from timer->func_base. The func_base
	157	* is samae as io_base for v1 and io_base + 0x14 for v2 ip.
	158	*
	159	*/
	160	#define OMAP_TIMER_V2_FUNC_OFFSET 0x14
	161
ec97489d TL	162	#define _OMAP_TIMER_WAKEUP_EN_OFFSET 0x20
	163	#define _OMAP_TIMER_CTRL_OFFSET 0x24
	164	#define OMAP_TIMER_CTRL_GPOCFG (1 << 14)
	165	#define OMAP_TIMER_CTRL_CAPTMODE (1 << 13)
	166	#define OMAP_TIMER_CTRL_PT (1 << 12)
	167	#define OMAP_TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8)
	168	#define OMAP_TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8)
	169	#define OMAP_TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8)
	170	#define OMAP_TIMER_CTRL_SCPWM (1 << 7)
	171	#define OMAP_TIMER_CTRL_CE (1 << 6) /* compare enable */
	172	#define OMAP_TIMER_CTRL_PRE (1 << 5) /* prescaler enable */
	173	#define OMAP_TIMER_CTRL_PTV_SHIFT 2 /* prescaler value shift */
	174	#define OMAP_TIMER_CTRL_POSTED (1 << 2)
	175	#define OMAP_TIMER_CTRL_AR (1 << 1) /* auto-reload enable */
	176	#define OMAP_TIMER_CTRL_ST (1 << 0) /* start timer */
	177	#define _OMAP_TIMER_COUNTER_OFFSET 0x28
	178	#define _OMAP_TIMER_LOAD_OFFSET 0x2c
	179	#define _OMAP_TIMER_TRIGGER_OFFSET 0x30
	180	#define _OMAP_TIMER_WRITE_PEND_OFFSET 0x34
	181	#define WP_NONE 0 /* no write pending bit */
	182	#define WP_TCLR (1 << 0)
	183	#define WP_TCRR (1 << 1)
	184	#define WP_TLDR (1 << 2)
	185	#define WP_TTGR (1 << 3)
	186	#define WP_TMAR (1 << 4)
	187	#define WP_TPIR (1 << 5)
	188	#define WP_TNIR (1 << 6)
	189	#define WP_TCVR (1 << 7)
	190	#define WP_TOCR (1 << 8)
	191	#define WP_TOWR (1 << 9)
	192	#define _OMAP_TIMER_MATCH_OFFSET 0x38
	193	#define _OMAP_TIMER_CAPTURE_OFFSET 0x3c
	194	#define _OMAP_TIMER_IF_CTRL_OFFSET 0x40
	195	#define _OMAP_TIMER_CAPTURE2_OFFSET 0x44 /* TCAR2, 34xx only */
	196	#define _OMAP_TIMER_TICK_POS_OFFSET 0x48 /* TPIR, 34xx only */
	197	#define _OMAP_TIMER_TICK_NEG_OFFSET 0x4c /* TNIR, 34xx only */
	198	#define _OMAP_TIMER_TICK_COUNT_OFFSET 0x50 /* TCVR, 34xx only */
	199	#define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET 0x54 /* TOCR, 34xx only */
	200	#define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET 0x58 /* TOWR, 34xx only */
	201
	202	/* register offsets with the write pending bit encoded */
	203	#define WPSHIFT 16
	204
ec97489d TL	205	#define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \
	206	\| (WP_NONE << WPSHIFT))
	207
	208	#define OMAP_TIMER_CTRL_REG (_OMAP_TIMER_CTRL_OFFSET \
	209	\| (WP_TCLR << WPSHIFT))
	210
	211	#define OMAP_TIMER_COUNTER_REG (_OMAP_TIMER_COUNTER_OFFSET \
	212	\| (WP_TCRR << WPSHIFT))
	213
	214	#define OMAP_TIMER_LOAD_REG (_OMAP_TIMER_LOAD_OFFSET \
	215	\| (WP_TLDR << WPSHIFT))
	216
	217	#define OMAP_TIMER_TRIGGER_REG (_OMAP_TIMER_TRIGGER_OFFSET \
	218	\| (WP_TTGR << WPSHIFT))
	219
	220	#define OMAP_TIMER_WRITE_PEND_REG (_OMAP_TIMER_WRITE_PEND_OFFSET \
	221	\| (WP_NONE << WPSHIFT))
	222
	223	#define OMAP_TIMER_MATCH_REG (_OMAP_TIMER_MATCH_OFFSET \
	224	\| (WP_TMAR << WPSHIFT))
	225
	226	#define OMAP_TIMER_CAPTURE_REG (_OMAP_TIMER_CAPTURE_OFFSET \
	227	\| (WP_NONE << WPSHIFT))
	228
	229	#define OMAP_TIMER_IF_CTRL_REG (_OMAP_TIMER_IF_CTRL_OFFSET \
	230	\| (WP_NONE << WPSHIFT))
	231
	232	#define OMAP_TIMER_CAPTURE2_REG (_OMAP_TIMER_CAPTURE2_OFFSET \
	233	\| (WP_NONE << WPSHIFT))
	234
	235	#define OMAP_TIMER_TICK_POS_REG (_OMAP_TIMER_TICK_POS_OFFSET \
	236	\| (WP_TPIR << WPSHIFT))
	237
	238	#define OMAP_TIMER_TICK_NEG_REG (_OMAP_TIMER_TICK_NEG_OFFSET \
	239	\| (WP_TNIR << WPSHIFT))
	240
	241	#define OMAP_TIMER_TICK_COUNT_REG (_OMAP_TIMER_TICK_COUNT_OFFSET \
	242	\| (WP_TCVR << WPSHIFT))
	243
	244	#define OMAP_TIMER_TICK_INT_MASK_SET_REG \
	245	(_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET \| (WP_TOCR << WPSHIFT))
	246
	247	#define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \
	248	(_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET \| (WP_TOWR << WPSHIFT))
	249
f7bda9ee	250	#endif /* __CLOCKSOURCE_DMTIMER_H */