[linux-2.6-block.git] / include / clocksource / arm_arch_timer.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (C) 2012 ARM Ltd.
 */
#ifndef __CLKSOURCE_ARM_ARCH_TIMER_H
#define __CLKSOURCE_ARM_ARCH_TIMER_H

#include <linux/bitops.h>
#include <linux/timecounter.h>
#include <linux/types.h>

#define ARCH_TIMER_TYPE_CP15		BIT(0)
#define ARCH_TIMER_TYPE_MEM		BIT(1)

#define ARCH_TIMER_CTRL_ENABLE		(1 << 0)
#define ARCH_TIMER_CTRL_IT_MASK		(1 << 1)
#define ARCH_TIMER_CTRL_IT_STAT		(1 << 2)

#define CNTHCTL_EL1PCTEN		(1 << 0)
#define CNTHCTL_EL1PCEN			(1 << 1)
#define CNTHCTL_EVNTEN			(1 << 2)
#define CNTHCTL_EVNTDIR			(1 << 3)
#define CNTHCTL_EVNTI			(0xF << 4)

enum arch_timer_reg {
	ARCH_TIMER_REG_CTRL,
	ARCH_TIMER_REG_CVAL,
};

enum arch_timer_ppi_nr {
	ARCH_TIMER_PHYS_SECURE_PPI,
	ARCH_TIMER_PHYS_NONSECURE_PPI,
	ARCH_TIMER_VIRT_PPI,
	ARCH_TIMER_HYP_PPI,
	ARCH_TIMER_HYP_VIRT_PPI,
	ARCH_TIMER_MAX_TIMER_PPI
};

enum arch_timer_spi_nr {
	ARCH_TIMER_PHYS_SPI,
	ARCH_TIMER_VIRT_SPI,
	ARCH_TIMER_MAX_TIMER_SPI
};

#define ARCH_TIMER_PHYS_ACCESS		0
#define ARCH_TIMER_VIRT_ACCESS		1
#define ARCH_TIMER_MEM_PHYS_ACCESS	2
#define ARCH_TIMER_MEM_VIRT_ACCESS	3

#define ARCH_TIMER_MEM_MAX_FRAMES	8

#define ARCH_TIMER_USR_PCT_ACCESS_EN	(1 << 0) /* physical counter */
#define ARCH_TIMER_USR_VCT_ACCESS_EN	(1 << 1) /* virtual counter */
#define ARCH_TIMER_VIRT_EVT_EN		(1 << 2)
#define ARCH_TIMER_EVT_TRIGGER_SHIFT	(4)
#define ARCH_TIMER_EVT_TRIGGER_MASK	(0xF << ARCH_TIMER_EVT_TRIGGER_SHIFT)
#define ARCH_TIMER_USR_VT_ACCESS_EN	(1 << 8) /* virtual timer registers */
#define ARCH_TIMER_USR_PT_ACCESS_EN	(1 << 9) /* physical timer registers */

#define ARCH_TIMER_EVT_STREAM_PERIOD_US	100
#define ARCH_TIMER_EVT_STREAM_FREQ				\
	(USEC_PER_SEC / ARCH_TIMER_EVT_STREAM_PERIOD_US)

struct arch_timer_kvm_info {
	struct timecounter timecounter;
	int virtual_irq;
	int physical_irq;
};

struct arch_timer_mem_frame {
	bool valid;
	phys_addr_t cntbase;
	size_t size;
	int phys_irq;
	int virt_irq;
};

struct arch_timer_mem {
	phys_addr_t cntctlbase;
	size_t size;
	struct arch_timer_mem_frame frame[ARCH_TIMER_MEM_MAX_FRAMES];
};

#ifdef CONFIG_ARM_ARCH_TIMER

extern u32 arch_timer_get_rate(void);
extern u64 (*arch_timer_read_counter)(void);
extern struct arch_timer_kvm_info *arch_timer_get_kvm_info(void);
extern bool arch_timer_evtstrm_available(void);

#else

static inline u32 arch_timer_get_rate(void)
{
	return 0;
}

static inline u64 arch_timer_read_counter(void)
{
	return 0;
}

static inline bool arch_timer_evtstrm_available(void)
{
	return false;
}

#endif

#endif
Commit	Line	Data
caab277b	1	/* SPDX-License-Identifier: GPL-2.0-only */
8a4da6e3 MR	2	/*
8a4da6e3 MR	3	* Copyright (C) 2012 ARM Ltd.
8a4da6e3 MR	4	*/
	5	#ifndef __CLKSOURCE_ARM_ARCH_TIMER_H
	6	#define __CLKSOURCE_ARM_ARCH_TIMER_H
	7
831610c0	8	#include <linux/bitops.h>
74d23cc7	9	#include <linux/timecounter.h>
8a4da6e3 MR	10	#include <linux/types.h>
8a4da6e3 MR	11
831610c0 FW	12	#define ARCH_TIMER_TYPE_CP15 BIT(0)
	13	#define ARCH_TIMER_TYPE_MEM BIT(1)
	14
8a4da6e3 MR	15	#define ARCH_TIMER_CTRL_ENABLE (1 << 0)
	16	#define ARCH_TIMER_CTRL_IT_MASK (1 << 1)
	17	#define ARCH_TIMER_CTRL_IT_STAT (1 << 2)
	18
1431af36 MZ	19	#define CNTHCTL_EL1PCTEN (1 << 0)
	20	#define CNTHCTL_EL1PCEN (1 << 1)
	21	#define CNTHCTL_EVNTEN (1 << 2)
	22	#define CNTHCTL_EVNTDIR (1 << 3)
	23	#define CNTHCTL_EVNTI (0xF << 4)
	24
e09f3cc0 SB	25	enum arch_timer_reg {
e09f3cc0 SB	26	ARCH_TIMER_REG_CTRL,
a38b71b0	27	ARCH_TIMER_REG_CVAL,
e09f3cc0	28	};
8a4da6e3	29
831610c0 FW	30	enum arch_timer_ppi_nr {
	31	ARCH_TIMER_PHYS_SECURE_PPI,
	32	ARCH_TIMER_PHYS_NONSECURE_PPI,
	33	ARCH_TIMER_VIRT_PPI,
	34	ARCH_TIMER_HYP_PPI,
86332e9e	35	ARCH_TIMER_HYP_VIRT_PPI,
831610c0 FW	36	ARCH_TIMER_MAX_TIMER_PPI
	37	};
	38
097cd143 FW	39	enum arch_timer_spi_nr {
	40	ARCH_TIMER_PHYS_SPI,
	41	ARCH_TIMER_VIRT_SPI,
	42	ARCH_TIMER_MAX_TIMER_SPI
	43	};
	44
8a4da6e3 MR	45	#define ARCH_TIMER_PHYS_ACCESS 0
8a4da6e3 MR	46	#define ARCH_TIMER_VIRT_ACCESS 1
22006994 SB	47	#define ARCH_TIMER_MEM_PHYS_ACCESS 2
22006994 SB	48	#define ARCH_TIMER_MEM_VIRT_ACCESS 3
8a4da6e3	49
b3251b8f FW	50	#define ARCH_TIMER_MEM_MAX_FRAMES 8
b3251b8f FW	51
28061758 SK	52	#define ARCH_TIMER_USR_PCT_ACCESS_EN (1 << 0) /* physical counter */
	53	#define ARCH_TIMER_USR_VCT_ACCESS_EN (1 << 1) /* virtual counter */
	54	#define ARCH_TIMER_VIRT_EVT_EN (1 << 2)
	55	#define ARCH_TIMER_EVT_TRIGGER_SHIFT (4)
	56	#define ARCH_TIMER_EVT_TRIGGER_MASK (0xF << ARCH_TIMER_EVT_TRIGGER_SHIFT)
	57	#define ARCH_TIMER_USR_VT_ACCESS_EN (1 << 8) /* virtual timer registers */
	58	#define ARCH_TIMER_USR_PT_ACCESS_EN (1 << 9) /* physical timer registers */
	59
7b77452e JT	60	#define ARCH_TIMER_EVT_STREAM_PERIOD_US 100
	61	#define ARCH_TIMER_EVT_STREAM_FREQ \
	62	(USEC_PER_SEC / ARCH_TIMER_EVT_STREAM_PERIOD_US)
037f6377	63
b4d6ce97 JG	64	struct arch_timer_kvm_info {
b4d6ce97 JG	65	struct timecounter timecounter;
d9b5e415	66	int virtual_irq;
ee793049	67	int physical_irq;
b4d6ce97 JG	68	};
b4d6ce97 JG	69
b3251b8f FW	70	struct arch_timer_mem_frame {
	71	bool valid;
	72	phys_addr_t cntbase;
	73	size_t size;
	74	int phys_irq;
	75	int virt_irq;
	76	};
	77
	78	struct arch_timer_mem {
	79	phys_addr_t cntctlbase;
	80	size_t size;
	81	struct arch_timer_mem_frame frame[ARCH_TIMER_MEM_MAX_FRAMES];
	82	};
	83
8a4da6e3 MR	84	#ifdef CONFIG_ARM_ARCH_TIMER
8a4da6e3 MR	85
8a4da6e3	86	extern u32 arch_timer_get_rate(void);
22006994	87	extern u64 (*arch_timer_read_counter)(void);
b4d6ce97	88	extern struct arch_timer_kvm_info *arch_timer_get_kvm_info(void);
ec5c8e42	89	extern bool arch_timer_evtstrm_available(void);
8a4da6e3 MR	90
	91	#else
	92
8a4da6e3 MR	93	static inline u32 arch_timer_get_rate(void)
	94	{
	95	return 0;
	96	}
	97
	98	static inline u64 arch_timer_read_counter(void)
	99	{
	100	return 0;
	101	}
	102
ec5c8e42 JT	103	static inline bool arch_timer_evtstrm_available(void)
	104	{
	105	return false;
	106	}
	107
8a4da6e3 MR	108	#endif
	109
	110	#endif