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9a8fd558 CZ |
1 | /* |
2 | * include/asm-xtensa/elf.h | |
3 | * | |
4 | * ELF register definitions | |
5 | * | |
6 | * This file is subject to the terms and conditions of the GNU General Public | |
7 | * License. See the file "COPYING" in the main directory of this archive | |
8 | * for more details. | |
9 | * | |
10 | * Copyright (C) 2001 - 2005 Tensilica Inc. | |
11 | */ | |
12 | ||
13 | #ifndef _XTENSA_ELF_H | |
14 | #define _XTENSA_ELF_H | |
15 | ||
173d6681 | 16 | #include <asm/variant/core.h> |
9a8fd558 | 17 | #include <asm/ptrace.h> |
9a8fd558 CZ |
18 | |
19 | /* Xtensa processor ELF architecture-magic number */ | |
20 | ||
21 | #define EM_XTENSA 94 | |
22 | #define EM_XTENSA_OLD 0xABC7 | |
23 | ||
24 | /* ELF register definitions. This is needed for core dump support. */ | |
25 | ||
26 | /* | |
27 | * elf_gregset_t contains the application-level state in the following order: | |
28 | * Processor info: config_version, cpuxy | |
29 | * Processor state: pc, ps, exccause, excvaddr, wb, ws, | |
30 | * lbeg, lend, lcount, sar | |
31 | * GP regs: ar0 - arXX | |
32 | */ | |
33 | ||
34 | typedef unsigned long elf_greg_t; | |
35 | ||
36 | typedef struct { | |
37 | elf_greg_t xchal_config_id0; | |
38 | elf_greg_t xchal_config_id1; | |
39 | elf_greg_t cpux; | |
40 | elf_greg_t cpuy; | |
41 | elf_greg_t pc; | |
42 | elf_greg_t ps; | |
43 | elf_greg_t exccause; | |
44 | elf_greg_t excvaddr; | |
45 | elf_greg_t windowbase; | |
46 | elf_greg_t windowstart; | |
47 | elf_greg_t lbeg; | |
48 | elf_greg_t lend; | |
49 | elf_greg_t lcount; | |
50 | elf_greg_t sar; | |
51 | elf_greg_t syscall; | |
52 | elf_greg_t ar[XCHAL_NUM_AREGS]; | |
53 | } xtensa_gregset_t; | |
54 | ||
55 | #define ELF_NGREG (sizeof(xtensa_gregset_t) / sizeof(elf_greg_t)) | |
56 | ||
57 | typedef elf_greg_t elf_gregset_t[ELF_NGREG]; | |
58 | ||
59 | /* | |
60 | * Compute the size of the coprocessor and extra state layout (register info) | |
61 | * table (in bytes). | |
62 | * This is actually the maximum size of the table, as opposed to the size, | |
63 | * which is available from the _xtensa_reginfo_table_size global variable. | |
64 | * | |
65 | * (See also arch/xtensa/kernel/coprocessor.S) | |
66 | * | |
67 | */ | |
68 | ||
69 | #ifndef XCHAL_EXTRA_SA_CONTENTS_LIBDB_NUM | |
70 | # define XTENSA_CPE_LTABLE_SIZE 0 | |
71 | #else | |
72 | # define XTENSA_CPE_SEGMENT(num) (num ? (1+num) : 0) | |
73 | # define XTENSA_CPE_LTABLE_ENTRIES \ | |
74 | ( XTENSA_CPE_SEGMENT(XCHAL_EXTRA_SA_CONTENTS_LIBDB_NUM) \ | |
75 | + XTENSA_CPE_SEGMENT(XCHAL_CP0_SA_CONTENTS_LIBDB_NUM) \ | |
76 | + XTENSA_CPE_SEGMENT(XCHAL_CP1_SA_CONTENTS_LIBDB_NUM) \ | |
77 | + XTENSA_CPE_SEGMENT(XCHAL_CP2_SA_CONTENTS_LIBDB_NUM) \ | |
78 | + XTENSA_CPE_SEGMENT(XCHAL_CP3_SA_CONTENTS_LIBDB_NUM) \ | |
79 | + XTENSA_CPE_SEGMENT(XCHAL_CP4_SA_CONTENTS_LIBDB_NUM) \ | |
80 | + XTENSA_CPE_SEGMENT(XCHAL_CP5_SA_CONTENTS_LIBDB_NUM) \ | |
81 | + XTENSA_CPE_SEGMENT(XCHAL_CP6_SA_CONTENTS_LIBDB_NUM) \ | |
82 | + XTENSA_CPE_SEGMENT(XCHAL_CP7_SA_CONTENTS_LIBDB_NUM) \ | |
83 | + 1 /* final entry */ \ | |
84 | ) | |
85 | # define XTENSA_CPE_LTABLE_SIZE (XTENSA_CPE_LTABLE_ENTRIES * 8) | |
86 | #endif | |
87 | ||
88 | ||
89 | /* | |
90 | * Instantiations of the elf_fpregset_t type contain, in most | |
91 | * architectures, the floating point (FPU) register set. | |
92 | * For Xtensa, this type is extended to contain all custom state, | |
93 | * ie. coprocessor and "extra" (non-coprocessor) state (including, | |
94 | * for example, TIE-defined states and register files; as well | |
95 | * as other optional processor state). | |
96 | * This includes FPU state if a floating-point coprocessor happens | |
97 | * to have been configured within the Xtensa processor. | |
98 | * | |
99 | * TOTAL_FPREGS_SIZE is the required size (without rounding) | |
100 | * of elf_fpregset_t. It provides space for the following: | |
101 | * | |
102 | * a) 32-bit mask of active coprocessors for this task (similar | |
103 | * to CPENABLE in single-threaded Xtensa processor systems) | |
104 | * | |
105 | * b) table describing the layout of custom states (ie. of | |
106 | * individual registers, etc) within the save areas | |
107 | * | |
108 | * c) save areas for each coprocessor and for non-coprocessor | |
109 | * ("extra") state | |
110 | * | |
111 | * Note that save areas may require up to 16-byte alignment when | |
112 | * accessed by save/restore sequences. We do not need to ensure | |
113 | * such alignment in an elf_fpregset_t structure because custom | |
114 | * state is not directly loaded/stored into it; rather, save area | |
115 | * contents are copied to elf_fpregset_t from the active save areas | |
116 | * (see 'struct task_struct' definition in processor.h for that) | |
117 | * using memcpy(). But we do allow space for such alignment, | |
118 | * to allow optimizations of layout and copying. | |
119 | */ | |
173d6681 | 120 | #if 0 |
9a8fd558 CZ |
121 | #define TOTAL_FPREGS_SIZE \ |
122 | (4 + XTENSA_CPE_LTABLE_SIZE + XTENSA_CP_EXTRA_SIZE) | |
123 | #define ELF_NFPREG \ | |
124 | ((TOTAL_FPREGS_SIZE + sizeof(elf_fpreg_t) - 1) / sizeof(elf_fpreg_t)) | |
173d6681 CZ |
125 | #else |
126 | #define TOTAL_FPREGS_SIZE 0 | |
127 | #define ELF_NFPREG 0 | |
128 | #endif | |
9a8fd558 CZ |
129 | |
130 | typedef unsigned int elf_fpreg_t; | |
131 | typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; | |
132 | ||
133 | #define ELF_CORE_COPY_REGS(_eregs, _pregs) \ | |
134 | xtensa_elf_core_copy_regs (&_eregs, _pregs); | |
135 | ||
136 | extern void xtensa_elf_core_copy_regs (xtensa_gregset_t *, struct pt_regs *); | |
137 | ||
138 | /* | |
139 | * This is used to ensure we don't load something for the wrong architecture. | |
140 | */ | |
141 | ||
142 | #define elf_check_arch(x) ( ( (x)->e_machine == EM_XTENSA ) || \ | |
143 | ( (x)->e_machine == EM_XTENSA_OLD ) ) | |
144 | ||
145 | /* | |
146 | * These are used to set parameters in the core dumps. | |
147 | */ | |
148 | ||
149 | #ifdef __XTENSA_EL__ | |
150 | # define ELF_DATA ELFDATA2LSB | |
151 | #elif defined(__XTENSA_EB__) | |
152 | # define ELF_DATA ELFDATA2MSB | |
153 | #else | |
154 | # error processor byte order undefined! | |
155 | #endif | |
156 | ||
157 | #define ELF_CLASS ELFCLASS32 | |
158 | #define ELF_ARCH EM_XTENSA | |
159 | ||
160 | #define USE_ELF_CORE_DUMP | |
161 | #define ELF_EXEC_PAGESIZE PAGE_SIZE | |
162 | ||
163 | /* | |
164 | * This is the location that an ET_DYN program is loaded if exec'ed. Typical | |
165 | * use of this is to invoke "./ld.so someprog" to test out a new version of | |
166 | * the loader. We need to make sure that it is out of the way of the program | |
167 | * that it will "exec", and that there is sufficient room for the brk. | |
168 | */ | |
169 | ||
170 | #define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3) | |
171 | ||
172 | /* | |
173 | * This yields a mask that user programs can use to figure out what | |
174 | * instruction set this CPU supports. This could be done in user space, | |
175 | * but it's not easy, and we've already done it here. | |
176 | */ | |
177 | ||
178 | #define ELF_HWCAP (0) | |
179 | ||
180 | /* | |
181 | * This yields a string that ld.so will use to load implementation | |
182 | * specific libraries for optimization. This is more specific in | |
183 | * intent than poking at uname or /proc/cpuinfo. | |
184 | * For the moment, we have only optimizations for the Intel generations, | |
185 | * but that could change... | |
186 | */ | |
187 | ||
188 | #define ELF_PLATFORM (NULL) | |
189 | ||
190 | /* | |
191 | * The Xtensa processor ABI says that when the program starts, a2 | |
192 | * contains a pointer to a function which might be registered using | |
193 | * `atexit'. This provides a mean for the dynamic linker to call | |
194 | * DT_FINI functions for shared libraries that have been loaded before | |
195 | * the code runs. | |
196 | * | |
197 | * A value of 0 tells we have no such handler. | |
198 | * | |
199 | * We might as well make sure everything else is cleared too (except | |
200 | * for the stack pointer in a1), just to make things more | |
201 | * deterministic. Also, clearing a0 terminates debugger backtraces. | |
202 | */ | |
203 | ||
204 | #define ELF_PLAT_INIT(_r, load_addr) \ | |
205 | do { _r->areg[0]=0; /*_r->areg[1]=0;*/ _r->areg[2]=0; _r->areg[3]=0; \ | |
206 | _r->areg[4]=0; _r->areg[5]=0; _r->areg[6]=0; _r->areg[7]=0; \ | |
207 | _r->areg[8]=0; _r->areg[9]=0; _r->areg[10]=0; _r->areg[11]=0; \ | |
208 | _r->areg[12]=0; _r->areg[13]=0; _r->areg[14]=0; _r->areg[15]=0; \ | |
209 | } while (0) | |
210 | ||
211 | #ifdef __KERNEL__ | |
212 | ||
213 | #define SET_PERSONALITY(ex, ibcs2) set_personality(PER_LINUX_32BIT) | |
214 | ||
8c65b4a6 TS |
215 | struct task_struct; |
216 | ||
9a8fd558 CZ |
217 | extern void do_copy_regs (xtensa_gregset_t*, struct pt_regs*, |
218 | struct task_struct*); | |
219 | extern void do_restore_regs (xtensa_gregset_t*, struct pt_regs*, | |
220 | struct task_struct*); | |
221 | extern void do_save_fpregs (elf_fpregset_t*, struct pt_regs*, | |
222 | struct task_struct*); | |
223 | extern int do_restore_fpregs (elf_fpregset_t*, struct pt_regs*, | |
224 | struct task_struct*); | |
225 | ||
226 | #endif /* __KERNEL__ */ | |
227 | #endif /* _XTENSA_ELF_H */ |