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9a8fd558 | 1 | /* |
f30c2269 | 2 | * include/asm-xtensa/coprocessor.h |
9a8fd558 CZ |
3 | * |
4 | * This file is subject to the terms and conditions of the GNU General Public | |
5 | * License. See the file "COPYING" in the main directory of this archive | |
6 | * for more details. | |
7 | * | |
c658eac6 | 8 | * Copyright (C) 2003 - 2007 Tensilica Inc. |
9a8fd558 CZ |
9 | */ |
10 | ||
c658eac6 | 11 | |
9a8fd558 CZ |
12 | #ifndef _XTENSA_COPROCESSOR_H |
13 | #define _XTENSA_COPROCESSOR_H | |
14 | ||
c658eac6 | 15 | #include <linux/stringify.h> |
173d6681 | 16 | #include <asm/variant/tie.h> |
c658eac6 CZ |
17 | #include <asm/types.h> |
18 | ||
19 | #ifdef __ASSEMBLY__ | |
20 | # include <asm/variant/tie-asm.h> | |
21 | ||
22 | .macro xchal_sa_start a b | |
23 | .set .Lxchal_pofs_, 0 | |
24 | .set .Lxchal_ofs_, 0 | |
25 | .endm | |
26 | ||
27 | .macro xchal_sa_align ptr minofs maxofs ofsalign totalign | |
28 | .set .Lxchal_ofs_, .Lxchal_ofs_ + .Lxchal_pofs_ + \totalign - 1 | |
29 | .set .Lxchal_ofs_, (.Lxchal_ofs_ & -\totalign) - .Lxchal_pofs_ | |
30 | .endm | |
31 | ||
32 | #define _SELECT ( XTHAL_SAS_TIE | XTHAL_SAS_OPT \ | |
33 | | XTHAL_SAS_CC \ | |
34 | | XTHAL_SAS_CALR | XTHAL_SAS_CALE | XTHAL_SAS_GLOB ) | |
35 | ||
36 | .macro save_xtregs_opt ptr clb at1 at2 at3 at4 offset | |
37 | .if XTREGS_OPT_SIZE > 0 | |
38 | addi \clb, \ptr, \offset | |
39 | xchal_ncp_store \clb \at1 \at2 \at3 \at4 select=_SELECT | |
40 | .endif | |
41 | .endm | |
42 | ||
43 | .macro load_xtregs_opt ptr clb at1 at2 at3 at4 offset | |
44 | .if XTREGS_OPT_SIZE > 0 | |
45 | addi \clb, \ptr, \offset | |
46 | xchal_ncp_load \clb \at1 \at2 \at3 \at4 select=_SELECT | |
47 | .endif | |
48 | .endm | |
49 | #undef _SELECT | |
50 | ||
51 | #define _SELECT ( XTHAL_SAS_TIE | XTHAL_SAS_OPT \ | |
52 | | XTHAL_SAS_NOCC \ | |
53 | | XTHAL_SAS_CALR | XTHAL_SAS_CALE | XTHAL_SAS_GLOB ) | |
54 | ||
55 | .macro save_xtregs_user ptr clb at1 at2 at3 at4 offset | |
56 | .if XTREGS_USER_SIZE > 0 | |
57 | addi \clb, \ptr, \offset | |
58 | xchal_ncp_store \clb \at1 \at2 \at3 \at4 select=_SELECT | |
59 | .endif | |
60 | .endm | |
61 | ||
62 | .macro load_xtregs_user ptr clb at1 at2 at3 at4 offset | |
63 | .if XTREGS_USER_SIZE > 0 | |
64 | addi \clb, \ptr, \offset | |
65 | xchal_ncp_load \clb \at1 \at2 \at3 \at4 select=_SELECT | |
66 | .endif | |
67 | .endm | |
68 | #undef _SELECT | |
69 | ||
70 | ||
71 | ||
72 | #endif /* __ASSEMBLY__ */ | |
173d6681 | 73 | |
9a8fd558 | 74 | /* |
c658eac6 CZ |
75 | * XTENSA_HAVE_COPROCESSOR(x) returns 1 if coprocessor x is configured. |
76 | * | |
77 | * XTENSA_HAVE_IO_PORT(x) returns 1 if io-port x is configured. | |
78 | * | |
9a8fd558 | 79 | */ |
9a8fd558 | 80 | |
c658eac6 CZ |
81 | #define XTENSA_HAVE_COPROCESSOR(x) \ |
82 | ((XCHAL_CP_MASK ^ XCHAL_CP_PORT_MASK) & (1 << (x))) | |
83 | #define XTENSA_HAVE_COPROCESSORS \ | |
84 | (XCHAL_CP_MASK ^ XCHAL_CP_PORT_MASK) | |
85 | #define XTENSA_HAVE_IO_PORT(x) \ | |
86 | (XCHAL_CP_PORT_MASK & (1 << (x))) | |
87 | #define XTENSA_HAVE_IO_PORTS \ | |
88 | XCHAL_CP_PORT_MASK | |
9a8fd558 CZ |
89 | |
90 | #ifndef __ASSEMBLY__ | |
9a8fd558 | 91 | |
29c4dfd9 | 92 | |
c658eac6 | 93 | #if XCHAL_HAVE_CP |
29c4dfd9 | 94 | |
c658eac6 CZ |
95 | #define RSR_CPENABLE(x) do { \ |
96 | __asm__ __volatile__("rsr %0," __stringify(CPENABLE) : "=a" (x)); \ | |
97 | } while(0); | |
98 | #define WSR_CPENABLE(x) do { \ | |
99 | __asm__ __volatile__("wsr %0," __stringify(CPENABLE) "; rsync" \ | |
100 | :: "a" (x)); \ | |
101 | } while(0); | |
173d6681 | 102 | |
c658eac6 CZ |
103 | #endif /* XCHAL_HAVE_CP */ |
104 | ||
105 | ||
106 | /* | |
107 | * Additional registers. | |
108 | * We define three types of additional registers: | |
109 | * ext: extra registers that are used by the compiler | |
110 | * cpn: optional registers that can be used by a user application | |
111 | * cpX: coprocessor registers that can only be used if the corresponding | |
112 | * CPENABLE bit is set. | |
113 | */ | |
114 | ||
115 | #define XCHAL_SA_REG(list,compiler,x,type,y,name,z,align,size,...) \ | |
116 | __REG ## list (compiler, type, name, size, align) | |
117 | ||
118 | #define __REG0(compiler,t,name,s,a) __REG0_ ## compiler (name) | |
119 | #define __REG1(compiler,t,name,s,a) __REG1_ ## compiler (name) | |
120 | #define __REG2(c,type,...) __REG2_ ## type (__VA_ARGS__) | |
121 | ||
122 | #define __REG0_0(name) | |
123 | #define __REG0_1(name) __u32 name; | |
124 | #define __REG1_0(name) __u32 name; | |
125 | #define __REG1_1(name) | |
126 | #define __REG2_0(n,s,a) __u32 name; | |
127 | #define __REG2_1(n,s,a) unsigned char n[s] __attribute__ ((aligned(a))); | |
128 | #define __REG2_2(n,s,a) unsigned char n[s] __attribute__ ((aligned(a))); | |
129 | ||
130 | typedef struct { XCHAL_NCP_SA_LIST(0) } xtregs_opt_t | |
131 | __attribute__ ((aligned (XCHAL_NCP_SA_ALIGN))); | |
132 | typedef struct { XCHAL_NCP_SA_LIST(1) } xtregs_user_t | |
133 | __attribute__ ((aligned (XCHAL_NCP_SA_ALIGN))); | |
134 | ||
135 | #if XTENSA_HAVE_COPROCESSORS | |
136 | ||
137 | typedef struct { XCHAL_CP0_SA_LIST(2) } xtregs_cp0_t | |
138 | __attribute__ ((aligned (XCHAL_CP0_SA_ALIGN))); | |
139 | typedef struct { XCHAL_CP1_SA_LIST(2) } xtregs_cp1_t | |
140 | __attribute__ ((aligned (XCHAL_CP1_SA_ALIGN))); | |
141 | typedef struct { XCHAL_CP2_SA_LIST(2) } xtregs_cp2_t | |
142 | __attribute__ ((aligned (XCHAL_CP2_SA_ALIGN))); | |
143 | typedef struct { XCHAL_CP3_SA_LIST(2) } xtregs_cp3_t | |
144 | __attribute__ ((aligned (XCHAL_CP3_SA_ALIGN))); | |
145 | typedef struct { XCHAL_CP4_SA_LIST(2) } xtregs_cp4_t | |
146 | __attribute__ ((aligned (XCHAL_CP4_SA_ALIGN))); | |
147 | typedef struct { XCHAL_CP5_SA_LIST(2) } xtregs_cp5_t | |
148 | __attribute__ ((aligned (XCHAL_CP5_SA_ALIGN))); | |
149 | typedef struct { XCHAL_CP6_SA_LIST(2) } xtregs_cp6_t | |
150 | __attribute__ ((aligned (XCHAL_CP6_SA_ALIGN))); | |
151 | typedef struct { XCHAL_CP7_SA_LIST(2) } xtregs_cp7_t | |
152 | __attribute__ ((aligned (XCHAL_CP7_SA_ALIGN))); | |
153 | ||
154 | extern struct thread_info* coprocessor_owner[XCHAL_CP_MAX]; | |
155 | extern void coprocessor_save(void*, int); | |
156 | extern void coprocessor_load(void*, int); | |
157 | extern void coprocessor_flush(struct thread_info*, int); | |
158 | extern void coprocessor_restore(struct thread_info*, int); | |
159 | ||
160 | extern void coprocessor_release_all(struct thread_info*); | |
161 | extern void coprocessor_flush_all(struct thread_info*); | |
162 | ||
163 | static inline void coprocessor_clear_cpenable(void) | |
164 | { | |
165 | unsigned long i = 0; | |
166 | WSR_CPENABLE(i); | |
167 | } | |
168 | ||
169 | #endif /* XTENSA_HAVE_COPROCESSORS */ | |
170 | ||
171 | #endif /* !__ASSEMBLY__ */ | |
9a8fd558 | 172 | #endif /* _XTENSA_COPROCESSOR_H */ |