[linux-2.6-block.git] / include / asm-x86_64 / msr.h

#ifndef X86_64_MSR_H
#define X86_64_MSR_H 1

#ifndef __ASSEMBLY__
/*
 * Access to machine-specific registers (available on 586 and better only)
 * Note: the rd* operations modify the parameters directly (without using
 * pointer indirection), this allows gcc to optimize better
 */

#define rdmsr(msr,val1,val2) \
       __asm__ __volatile__("rdmsr" \
			    : "=a" (val1), "=d" (val2) \
			    : "c" (msr))


#define rdmsrl(msr,val) do { unsigned long a__,b__; \
       __asm__ __volatile__("rdmsr" \
			    : "=a" (a__), "=d" (b__) \
			    : "c" (msr)); \
       val = a__ | (b__<<32); \
} while(0)

#define wrmsr(msr,val1,val2) \
     __asm__ __volatile__("wrmsr" \
			  : /* no outputs */ \
			  : "c" (msr), "a" (val1), "d" (val2))

#define wrmsrl(msr,val) wrmsr(msr,(__u32)((__u64)(val)),((__u64)(val))>>32) 

/* wrmsr with exception handling */
#define wrmsr_safe(msr,a,b) ({ int ret__;			\
	asm volatile("2: wrmsr ; xorl %0,%0\n"			\
		     "1:\n\t"					\
		     ".section .fixup,\"ax\"\n\t"		\
		     "3:  movl %4,%0 ; jmp 1b\n\t"		\
		     ".previous\n\t"				\
 		     ".section __ex_table,\"a\"\n"		\
		     "   .align 8\n\t"				\
		     "   .quad 	2b,3b\n\t"			\
		     ".previous"				\
		     : "=a" (ret__)				\
		     : "c" (msr), "0" (a), "d" (b), "i" (-EFAULT)); \
	ret__; })

#define checking_wrmsrl(msr,val) wrmsr_safe(msr,(u32)(val),(u32)((val)>>32))

#define rdmsr_safe(msr,a,b) \
	({ int ret__;						\
	  asm volatile ("1:       rdmsr\n"			\
                      "2:\n"					\
                      ".section .fixup,\"ax\"\n"		\
                      "3:       movl %4,%0\n"			\
                      " jmp 2b\n"				\
                      ".previous\n"				\
                      ".section __ex_table,\"a\"\n"		\
                      " .align 8\n"				\
                      " .quad 1b,3b\n"				\
                      ".previous":"=&bDS" (ret__), "=a"(*(a)), "=d"(*(b))\
                      :"c"(msr), "i"(-EIO), "0"(0));		\
	  ret__; })		

#define rdtsc(low,high) \
     __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))

#define rdtscl(low) \
     __asm__ __volatile__ ("rdtsc" : "=a" (low) : : "edx")

#define rdtscp(low,high,aux) \
     asm volatile (".byte 0x0f,0x01,0xf9" : "=a" (low), "=d" (high), "=c" (aux))

#define rdtscll(val) do { \
     unsigned int __a,__d; \
     asm volatile("rdtsc" : "=a" (__a), "=d" (__d)); \
     (val) = ((unsigned long)__a) | (((unsigned long)__d)<<32); \
} while(0)

#define rdtscpll(val, aux) do { \
     unsigned long __a, __d; \
     asm volatile (".byte 0x0f,0x01,0xf9" : "=a" (__a), "=d" (__d), "=c" (aux)); \
     (val) = (__d << 32) | __a; \
} while (0)

#define write_tsc(val1,val2) wrmsr(0x10, val1, val2)

#define write_rdtscp_aux(val) wrmsr(0xc0000103, val, 0)

#define rdpmc(counter,low,high) \
     __asm__ __volatile__("rdpmc" \
			  : "=a" (low), "=d" (high) \
			  : "c" (counter))

static inline void cpuid(int op, unsigned int *eax, unsigned int *ebx,
			 unsigned int *ecx, unsigned int *edx)
{
	__asm__("cpuid"
		: "=a" (*eax),
		  "=b" (*ebx),
		  "=c" (*ecx),
		  "=d" (*edx)
		: "0" (op));
}

/* Some CPUID calls want 'count' to be placed in ecx */
static inline void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx,
	       	int *edx)
{
	__asm__("cpuid"
		: "=a" (*eax),
		  "=b" (*ebx),
		  "=c" (*ecx),
		  "=d" (*edx)
		: "0" (op), "c" (count));
}

/*
 * CPUID functions returning a single datum
 */
static inline unsigned int cpuid_eax(unsigned int op)
{
	unsigned int eax;

	__asm__("cpuid"
		: "=a" (eax)
		: "0" (op)
		: "bx", "cx", "dx");
	return eax;
}
static inline unsigned int cpuid_ebx(unsigned int op)
{
	unsigned int eax, ebx;

	__asm__("cpuid"
		: "=a" (eax), "=b" (ebx)
		: "0" (op)
		: "cx", "dx" );
	return ebx;
}
static inline unsigned int cpuid_ecx(unsigned int op)
{
	unsigned int eax, ecx;

	__asm__("cpuid"
		: "=a" (eax), "=c" (ecx)
		: "0" (op)
		: "bx", "dx" );
	return ecx;
}
static inline unsigned int cpuid_edx(unsigned int op)
{
	unsigned int eax, edx;

	__asm__("cpuid"
		: "=a" (eax), "=d" (edx)
		: "0" (op)
		: "bx", "cx");
	return edx;
}

#define MSR_IA32_UCODE_WRITE		0x79
#define MSR_IA32_UCODE_REV		0x8b


#endif

/* AMD/K8 specific MSRs */ 
#define MSR_EFER 0xc0000080		/* extended feature register */
#define MSR_STAR 0xc0000081		/* legacy mode SYSCALL target */
#define MSR_LSTAR 0xc0000082 		/* long mode SYSCALL target */
#define MSR_CSTAR 0xc0000083		/* compatibility mode SYSCALL target */
#define MSR_SYSCALL_MASK 0xc0000084	/* EFLAGS mask for syscall */
#define MSR_FS_BASE 0xc0000100		/* 64bit FS base */
#define MSR_GS_BASE 0xc0000101		/* 64bit GS base */
#define MSR_KERNEL_GS_BASE  0xc0000102	/* SwapGS GS shadow (or USER_GS from kernel) */ 
/* EFER bits: */ 
#define _EFER_SCE 0  /* SYSCALL/SYSRET */
#define _EFER_LME 8  /* Long mode enable */
#define _EFER_LMA 10 /* Long mode active (read-only) */
#define _EFER_NX 11  /* No execute enable */

#define EFER_SCE (1<<_EFER_SCE)
#define EFER_LME (1<<_EFER_LME)
#define EFER_LMA (1<<_EFER_LMA)
#define EFER_NX (1<<_EFER_NX)

/* Intel MSRs. Some also available on other CPUs */
#define MSR_IA32_TSC		0x10
#define MSR_IA32_PLATFORM_ID	0x17

#define MSR_IA32_PERFCTR0      0xc1
#define MSR_IA32_PERFCTR1      0xc2
#define MSR_FSB_FREQ		0xcd

#define MSR_MTRRcap		0x0fe
#define MSR_IA32_BBL_CR_CTL        0x119

#define MSR_IA32_SYSENTER_CS	0x174
#define MSR_IA32_SYSENTER_ESP	0x175
#define MSR_IA32_SYSENTER_EIP	0x176

#define MSR_IA32_MCG_CAP       0x179
#define MSR_IA32_MCG_STATUS        0x17a
#define MSR_IA32_MCG_CTL       0x17b

#define MSR_IA32_EVNTSEL0      0x186
#define MSR_IA32_EVNTSEL1      0x187

#define MSR_IA32_DEBUGCTLMSR       0x1d9
#define MSR_IA32_LASTBRANCHFROMIP  0x1db
#define MSR_IA32_LASTBRANCHTOIP        0x1dc
#define MSR_IA32_LASTINTFROMIP     0x1dd
#define MSR_IA32_LASTINTTOIP       0x1de

#define MSR_IA32_PEBS_ENABLE		0x3f1
#define MSR_IA32_DS_AREA		0x600
#define MSR_IA32_PERF_CAPABILITIES	0x345

#define MSR_MTRRfix64K_00000	0x250
#define MSR_MTRRfix16K_80000	0x258
#define MSR_MTRRfix16K_A0000	0x259
#define MSR_MTRRfix4K_C0000	0x268
#define MSR_MTRRfix4K_C8000	0x269
#define MSR_MTRRfix4K_D0000	0x26a
#define MSR_MTRRfix4K_D8000	0x26b
#define MSR_MTRRfix4K_E0000	0x26c
#define MSR_MTRRfix4K_E8000	0x26d
#define MSR_MTRRfix4K_F0000	0x26e
#define MSR_MTRRfix4K_F8000	0x26f
#define MSR_MTRRdefType		0x2ff

#define MSR_IA32_MC0_CTL       0x400
#define MSR_IA32_MC0_STATUS        0x401
#define MSR_IA32_MC0_ADDR      0x402
#define MSR_IA32_MC0_MISC      0x403

#define MSR_P6_PERFCTR0			0xc1
#define MSR_P6_PERFCTR1			0xc2
#define MSR_P6_EVNTSEL0			0x186
#define MSR_P6_EVNTSEL1			0x187

/* K7/K8 MSRs. Not complete. See the architecture manual for a more complete list. */
#define MSR_K7_EVNTSEL0            0xC0010000
#define MSR_K7_PERFCTR0            0xC0010004
#define MSR_K7_EVNTSEL1            0xC0010001
#define MSR_K7_PERFCTR1            0xC0010005
#define MSR_K7_EVNTSEL2            0xC0010002
#define MSR_K7_PERFCTR2            0xC0010006
#define MSR_K7_EVNTSEL3            0xC0010003
#define MSR_K7_PERFCTR3            0xC0010007
#define MSR_K8_TOP_MEM1		   0xC001001A
#define MSR_K8_TOP_MEM2		   0xC001001D
#define MSR_K8_SYSCFG		   0xC0010010
#define MSR_K8_HWCR		   0xC0010015

/* K6 MSRs */
#define MSR_K6_EFER			0xC0000080
#define MSR_K6_STAR			0xC0000081
#define MSR_K6_WHCR			0xC0000082
#define MSR_K6_UWCCR			0xC0000085
#define MSR_K6_PSOR			0xC0000087
#define MSR_K6_PFIR			0xC0000088

/* Centaur-Hauls/IDT defined MSRs. */
#define MSR_IDT_FCR1			0x107
#define MSR_IDT_FCR2			0x108
#define MSR_IDT_FCR3			0x109
#define MSR_IDT_FCR4			0x10a

#define MSR_IDT_MCR0			0x110
#define MSR_IDT_MCR1			0x111
#define MSR_IDT_MCR2			0x112
#define MSR_IDT_MCR3			0x113
#define MSR_IDT_MCR4			0x114
#define MSR_IDT_MCR5			0x115
#define MSR_IDT_MCR6			0x116
#define MSR_IDT_MCR7			0x117
#define MSR_IDT_MCR_CTRL		0x120

/* VIA Cyrix defined MSRs*/
#define MSR_VIA_FCR			0x1107
#define MSR_VIA_LONGHAUL		0x110a
#define MSR_VIA_RNG			0x110b
#define MSR_VIA_BCR2			0x1147

/* Intel defined MSRs. */
#define MSR_IA32_P5_MC_ADDR		0
#define MSR_IA32_P5_MC_TYPE		1
#define MSR_IA32_PLATFORM_ID		0x17
#define MSR_IA32_EBL_CR_POWERON		0x2a

#define MSR_IA32_APICBASE               0x1b
#define MSR_IA32_APICBASE_BSP           (1<<8)
#define MSR_IA32_APICBASE_ENABLE        (1<<11)
#define MSR_IA32_APICBASE_BASE          (0xfffff<<12)

/* P4/Xeon+ specific */
#define MSR_IA32_MCG_EAX		0x180
#define MSR_IA32_MCG_EBX		0x181
#define MSR_IA32_MCG_ECX		0x182
#define MSR_IA32_MCG_EDX		0x183
#define MSR_IA32_MCG_ESI		0x184
#define MSR_IA32_MCG_EDI		0x185
#define MSR_IA32_MCG_EBP		0x186
#define MSR_IA32_MCG_ESP		0x187
#define MSR_IA32_MCG_EFLAGS		0x188
#define MSR_IA32_MCG_EIP		0x189
#define MSR_IA32_MCG_RESERVED		0x18A

#define MSR_P6_EVNTSEL0			0x186
#define MSR_P6_EVNTSEL1			0x187

#define MSR_IA32_PERF_STATUS		0x198
#define MSR_IA32_PERF_CTL		0x199

#define MSR_IA32_MPERF			0xE7
#define MSR_IA32_APERF			0xE8

#define MSR_IA32_THERM_CONTROL		0x19a
#define MSR_IA32_THERM_INTERRUPT	0x19b
#define MSR_IA32_THERM_STATUS		0x19c
#define MSR_IA32_MISC_ENABLE		0x1a0

#define MSR_IA32_DEBUGCTLMSR		0x1d9
#define MSR_IA32_LASTBRANCHFROMIP	0x1db
#define MSR_IA32_LASTBRANCHTOIP		0x1dc
#define MSR_IA32_LASTINTFROMIP		0x1dd
#define MSR_IA32_LASTINTTOIP		0x1de

#define MSR_IA32_MC0_CTL		0x400
#define MSR_IA32_MC0_STATUS		0x401
#define MSR_IA32_MC0_ADDR		0x402
#define MSR_IA32_MC0_MISC		0x403

/* Pentium IV performance counter MSRs */
#define MSR_P4_BPU_PERFCTR0 		0x300
#define MSR_P4_BPU_PERFCTR1 		0x301
#define MSR_P4_BPU_PERFCTR2 		0x302
#define MSR_P4_BPU_PERFCTR3 		0x303
#define MSR_P4_MS_PERFCTR0 		0x304
#define MSR_P4_MS_PERFCTR1 		0x305
#define MSR_P4_MS_PERFCTR2 		0x306
#define MSR_P4_MS_PERFCTR3 		0x307
#define MSR_P4_FLAME_PERFCTR0 		0x308
#define MSR_P4_FLAME_PERFCTR1 		0x309
#define MSR_P4_FLAME_PERFCTR2 		0x30a
#define MSR_P4_FLAME_PERFCTR3 		0x30b
#define MSR_P4_IQ_PERFCTR0 		0x30c
#define MSR_P4_IQ_PERFCTR1 		0x30d
#define MSR_P4_IQ_PERFCTR2 		0x30e
#define MSR_P4_IQ_PERFCTR3 		0x30f
#define MSR_P4_IQ_PERFCTR4 		0x310
#define MSR_P4_IQ_PERFCTR5 		0x311
#define MSR_P4_BPU_CCCR0 		0x360
#define MSR_P4_BPU_CCCR1 		0x361
#define MSR_P4_BPU_CCCR2 		0x362
#define MSR_P4_BPU_CCCR3 		0x363
#define MSR_P4_MS_CCCR0 		0x364
#define MSR_P4_MS_CCCR1 		0x365
#define MSR_P4_MS_CCCR2 		0x366
#define MSR_P4_MS_CCCR3 		0x367
#define MSR_P4_FLAME_CCCR0 		0x368
#define MSR_P4_FLAME_CCCR1 		0x369
#define MSR_P4_FLAME_CCCR2 		0x36a
#define MSR_P4_FLAME_CCCR3 		0x36b
#define MSR_P4_IQ_CCCR0 		0x36c
#define MSR_P4_IQ_CCCR1 		0x36d
#define MSR_P4_IQ_CCCR2 		0x36e
#define MSR_P4_IQ_CCCR3 		0x36f
#define MSR_P4_IQ_CCCR4 		0x370
#define MSR_P4_IQ_CCCR5 		0x371
#define MSR_P4_ALF_ESCR0 		0x3ca
#define MSR_P4_ALF_ESCR1 		0x3cb
#define MSR_P4_BPU_ESCR0 		0x3b2
#define MSR_P4_BPU_ESCR1 		0x3b3
#define MSR_P4_BSU_ESCR0 		0x3a0
#define MSR_P4_BSU_ESCR1 		0x3a1
#define MSR_P4_CRU_ESCR0 		0x3b8
#define MSR_P4_CRU_ESCR1 		0x3b9
#define MSR_P4_CRU_ESCR2 		0x3cc
#define MSR_P4_CRU_ESCR3 		0x3cd
#define MSR_P4_CRU_ESCR4 		0x3e0
#define MSR_P4_CRU_ESCR5 		0x3e1
#define MSR_P4_DAC_ESCR0 		0x3a8
#define MSR_P4_DAC_ESCR1 		0x3a9
#define MSR_P4_FIRM_ESCR0 		0x3a4
#define MSR_P4_FIRM_ESCR1 		0x3a5
#define MSR_P4_FLAME_ESCR0 		0x3a6
#define MSR_P4_FLAME_ESCR1 		0x3a7
#define MSR_P4_FSB_ESCR0 		0x3a2
#define MSR_P4_FSB_ESCR1 		0x3a3
#define MSR_P4_IQ_ESCR0 		0x3ba
#define MSR_P4_IQ_ESCR1 		0x3bb
#define MSR_P4_IS_ESCR0 		0x3b4
#define MSR_P4_IS_ESCR1 		0x3b5
#define MSR_P4_ITLB_ESCR0 		0x3b6
#define MSR_P4_ITLB_ESCR1 		0x3b7
#define MSR_P4_IX_ESCR0 		0x3c8
#define MSR_P4_IX_ESCR1 		0x3c9
#define MSR_P4_MOB_ESCR0 		0x3aa
#define MSR_P4_MOB_ESCR1 		0x3ab
#define MSR_P4_MS_ESCR0 		0x3c0
#define MSR_P4_MS_ESCR1 		0x3c1
#define MSR_P4_PMH_ESCR0 		0x3ac
#define MSR_P4_PMH_ESCR1 		0x3ad
#define MSR_P4_RAT_ESCR0 		0x3bc
#define MSR_P4_RAT_ESCR1 		0x3bd
#define MSR_P4_SAAT_ESCR0 		0x3ae
#define MSR_P4_SAAT_ESCR1 		0x3af
#define MSR_P4_SSU_ESCR0 		0x3be
#define MSR_P4_SSU_ESCR1 		0x3bf    /* guess: not defined in manual */
#define MSR_P4_TBPU_ESCR0 		0x3c2
#define MSR_P4_TBPU_ESCR1 		0x3c3
#define MSR_P4_TC_ESCR0 		0x3c4
#define MSR_P4_TC_ESCR1 		0x3c5
#define MSR_P4_U2L_ESCR0 		0x3b0
#define MSR_P4_U2L_ESCR1 		0x3b1

/* Intel Core-based CPU performance counters */
#define MSR_CORE_PERF_FIXED_CTR0	0x309
#define MSR_CORE_PERF_FIXED_CTR1	0x30a
#define MSR_CORE_PERF_FIXED_CTR2	0x30b
#define MSR_CORE_PERF_FIXED_CTR_CTRL	0x38d
#define MSR_CORE_PERF_GLOBAL_STATUS	0x38e
#define MSR_CORE_PERF_GLOBAL_CTRL	0x38f
#define MSR_CORE_PERF_GLOBAL_OVF_CTRL	0x390

#endif
Commit	Line	Data
1da177e4 LT	1	#ifndef X86_64_MSR_H
	2	#define X86_64_MSR_H 1
	3
	4	#ifndef __ASSEMBLY__
	5	/*
	6	* Access to machine-specific registers (available on 586 and better only)
	7	* Note: the rd* operations modify the parameters directly (without using
	8	* pointer indirection), this allows gcc to optimize better
	9	*/
	10
	11	#define rdmsr(msr,val1,val2) \
	12	__asm__ __volatile__("rdmsr" \
	13	: "=a" (val1), "=d" (val2) \
	14	: "c" (msr))
	15
	16
	17	#define rdmsrl(msr,val) do { unsigned long a__,b__; \
	18	__asm__ __volatile__("rdmsr" \
	19	: "=a" (a__), "=d" (b__) \
	20	: "c" (msr)); \
	21	val = a__ \| (b__<<32); \
a88cde13	22	} while(0)
1da177e4 LT	23
	24	#define wrmsr(msr,val1,val2) \
	25	__asm__ __volatile__("wrmsr" \
	26	: /* no outputs */ \
	27	: "c" (msr), "a" (val1), "d" (val2))
	28
	29	#define wrmsrl(msr,val) wrmsr(msr,(__u32)((__u64)(val)),((__u64)(val))>>32)
	30
	31	/* wrmsr with exception handling */
059bf0f6 AK	32	#define wrmsr_safe(msr,a,b) ({ int ret__; \
	33	asm volatile("2: wrmsr ; xorl %0,%0\n" \
	34	"1:\n\t" \
	35	".section .fixup,\"ax\"\n\t" \
	36	"3: movl %4,%0 ; jmp 1b\n\t" \
	37	".previous\n\t" \
	38	".section __ex_table,\"a\"\n" \
	39	" .align 8\n\t" \
	40	" .quad 2b,3b\n\t" \
	41	".previous" \
	42	: "=a" (ret__) \
	43	: "c" (msr), "0" (a), "d" (b), "i" (-EFAULT)); \
1da177e4 LT	44	ret__; })
	45
	46	#define checking_wrmsrl(msr,val) wrmsr_safe(msr,(u32)(val),(u32)((val)>>32))
	47
059bf0f6 AK	48	#define rdmsr_safe(msr,a,b) \
	49	({ int ret__; \
	50	asm volatile ("1: rdmsr\n" \
	51	"2:\n" \
	52	".section .fixup,\"ax\"\n" \
	53	"3: movl %4,%0\n" \
	54	" jmp 2b\n" \
	55	".previous\n" \
	56	".section __ex_table,\"a\"\n" \
	57	" .align 8\n" \
	58	" .quad 1b,3b\n" \
e6c66759	59	".previous":"=&bDS" (ret__), "=a"((a)), "=d"((b))\
059bf0f6 AK	60	:"c"(msr), "i"(-EIO), "0"(0)); \
	61	ret__; })
	62
1da177e4 LT	63	#define rdtsc(low,high) \
	64	__asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))
	65
	66	#define rdtscl(low) \
	67	__asm__ __volatile__ ("rdtsc" : "=a" (low) : : "edx")
	68
81af4449 VP	69	#define rdtscp(low,high,aux) \
	70	asm volatile (".byte 0x0f,0x01,0xf9" : "=a" (low), "=d" (high), "=c" (aux))
	71
1da177e4 LT	72	#define rdtscll(val) do { \
	73	unsigned int __a,__d; \
	74	asm volatile("rdtsc" : "=a" (__a), "=d" (__d)); \
	75	(val) = ((unsigned long)__a) \| (((unsigned long)__d)<<32); \
	76	} while(0)
	77
81af4449 VP	78	#define rdtscpll(val, aux) do { \
	79	unsigned long __a, __d; \
	80	asm volatile (".byte 0x0f,0x01,0xf9" : "=a" (__a), "=d" (__d), "=c" (aux)); \
	81	(val) = (__d << 32) \| __a; \
	82	} while (0)
	83
1da177e4 LT	84	#define write_tsc(val1,val2) wrmsr(0x10, val1, val2)
1da177e4 LT	85
81af4449 VP	86	#define write_rdtscp_aux(val) wrmsr(0xc0000103, val, 0)
81af4449 VP	87
1da177e4 LT	88	#define rdpmc(counter,low,high) \
	89	__asm__ __volatile__("rdpmc" \
	90	: "=a" (low), "=d" (high) \
	91	: "c" (counter))
	92
9c0aa0f9	93	static inline void cpuid(int op, unsigned int eax, unsigned int ebx,
1da177e4 LT	94	unsigned int ecx, unsigned int edx)
	95	{
	96	__asm__("cpuid"
	97	: "=a" (*eax),
	98	"=b" (*ebx),
	99	"=c" (*ecx),
	100	"=d" (*edx)
	101	: "0" (op));
	102	}
	103
	104	/* Some CPUID calls want 'count' to be placed in ecx */
	105	static inline void cpuid_count(int op, int count, int eax, int ebx, int *ecx,
	106	int *edx)
	107	{
	108	__asm__("cpuid"
	109	: "=a" (*eax),
	110	"=b" (*ebx),
	111	"=c" (*ecx),
	112	"=d" (*edx)
	113	: "0" (op), "c" (count));
	114	}
	115
	116	/*
	117	* CPUID functions returning a single datum
	118	*/
9c0aa0f9	119	static inline unsigned int cpuid_eax(unsigned int op)
1da177e4 LT	120	{
	121	unsigned int eax;
	122
	123	__asm__("cpuid"
	124	: "=a" (eax)
	125	: "0" (op)
	126	: "bx", "cx", "dx");
	127	return eax;
	128	}
9c0aa0f9	129	static inline unsigned int cpuid_ebx(unsigned int op)
1da177e4 LT	130	{
	131	unsigned int eax, ebx;
	132
	133	__asm__("cpuid"
	134	: "=a" (eax), "=b" (ebx)
	135	: "0" (op)
	136	: "cx", "dx" );
	137	return ebx;
	138	}
9c0aa0f9	139	static inline unsigned int cpuid_ecx(unsigned int op)
1da177e4 LT	140	{
	141	unsigned int eax, ecx;
	142
	143	__asm__("cpuid"
	144	: "=a" (eax), "=c" (ecx)
	145	: "0" (op)
	146	: "bx", "dx" );
	147	return ecx;
	148	}
9c0aa0f9	149	static inline unsigned int cpuid_edx(unsigned int op)
1da177e4 LT	150	{
	151	unsigned int eax, edx;
	152
	153	__asm__("cpuid"
	154	: "=a" (eax), "=d" (edx)
	155	: "0" (op)
	156	: "bx", "cx");
	157	return edx;
	158	}
	159
	160	#define MSR_IA32_UCODE_WRITE 0x79
	161	#define MSR_IA32_UCODE_REV 0x8b
	162
	163
	164	#endif
	165
	166	/* AMD/K8 specific MSRs */
	167	#define MSR_EFER 0xc0000080 /* extended feature register */
	168	#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
	169	#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
	170	#define MSR_CSTAR 0xc0000083 /* compatibility mode SYSCALL target */
	171	#define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
c7a3392e WS	172	#define MSR_FS_BASE 0xc0000100 /* 64bit FS base */
c7a3392e WS	173	#define MSR_GS_BASE 0xc0000101 /* 64bit GS base */
1da177e4 LT	174	#define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow (or USER_GS from kernel) */
	175	/* EFER bits: */
	176	#define _EFER_SCE 0 /* SYSCALL/SYSRET */
	177	#define _EFER_LME 8 /* Long mode enable */
	178	#define _EFER_LMA 10 /* Long mode active (read-only) */
	179	#define _EFER_NX 11 /* No execute enable */
	180
	181	#define EFER_SCE (1<<_EFER_SCE)
	182	#define EFER_LME (1<<_EFER_LME)
	183	#define EFER_LMA (1<<_EFER_LMA)
	184	#define EFER_NX (1<<_EFER_NX)
	185
	186	/* Intel MSRs. Some also available on other CPUs */
a8ab26fe	187	#define MSR_IA32_TSC 0x10
1da177e4 LT	188	#define MSR_IA32_PLATFORM_ID 0x17
	189
	190	#define MSR_IA32_PERFCTR0 0xc1
	191	#define MSR_IA32_PERFCTR1 0xc2
e11952b9	192	#define MSR_FSB_FREQ 0xcd
1da177e4 LT	193
	194	#define MSR_MTRRcap 0x0fe
	195	#define MSR_IA32_BBL_CR_CTL 0x119
	196
	197	#define MSR_IA32_SYSENTER_CS 0x174
	198	#define MSR_IA32_SYSENTER_ESP 0x175
	199	#define MSR_IA32_SYSENTER_EIP 0x176
	200
	201	#define MSR_IA32_MCG_CAP 0x179
	202	#define MSR_IA32_MCG_STATUS 0x17a
	203	#define MSR_IA32_MCG_CTL 0x17b
	204
	205	#define MSR_IA32_EVNTSEL0 0x186
	206	#define MSR_IA32_EVNTSEL1 0x187
	207
	208	#define MSR_IA32_DEBUGCTLMSR 0x1d9
	209	#define MSR_IA32_LASTBRANCHFROMIP 0x1db
	210	#define MSR_IA32_LASTBRANCHTOIP 0x1dc
	211	#define MSR_IA32_LASTINTFROMIP 0x1dd
	212	#define MSR_IA32_LASTINTTOIP 0x1de
	213
86efef50 SE	214	#define MSR_IA32_PEBS_ENABLE 0x3f1
	215	#define MSR_IA32_DS_AREA 0x600
	216	#define MSR_IA32_PERF_CAPABILITIES 0x345
	217
1da177e4 LT	218	#define MSR_MTRRfix64K_00000 0x250
	219	#define MSR_MTRRfix16K_80000 0x258
	220	#define MSR_MTRRfix16K_A0000 0x259
	221	#define MSR_MTRRfix4K_C0000 0x268
	222	#define MSR_MTRRfix4K_C8000 0x269
	223	#define MSR_MTRRfix4K_D0000 0x26a
	224	#define MSR_MTRRfix4K_D8000 0x26b
	225	#define MSR_MTRRfix4K_E0000 0x26c
	226	#define MSR_MTRRfix4K_E8000 0x26d
	227	#define MSR_MTRRfix4K_F0000 0x26e
	228	#define MSR_MTRRfix4K_F8000 0x26f
	229	#define MSR_MTRRdefType 0x2ff
	230
	231	#define MSR_IA32_MC0_CTL 0x400
	232	#define MSR_IA32_MC0_STATUS 0x401
	233	#define MSR_IA32_MC0_ADDR 0x402
	234	#define MSR_IA32_MC0_MISC 0x403
	235
	236	#define MSR_P6_PERFCTR0 0xc1
	237	#define MSR_P6_PERFCTR1 0xc2
	238	#define MSR_P6_EVNTSEL0 0x186
	239	#define MSR_P6_EVNTSEL1 0x187
	240
	241	/* K7/K8 MSRs. Not complete. See the architecture manual for a more complete list. */
	242	#define MSR_K7_EVNTSEL0 0xC0010000
	243	#define MSR_K7_PERFCTR0 0xC0010004
	244	#define MSR_K7_EVNTSEL1 0xC0010001
	245	#define MSR_K7_PERFCTR1 0xC0010005
	246	#define MSR_K7_EVNTSEL2 0xC0010002
	247	#define MSR_K7_PERFCTR2 0xC0010006
	248	#define MSR_K7_EVNTSEL3 0xC0010003
	249	#define MSR_K7_PERFCTR3 0xC0010007
	250	#define MSR_K8_TOP_MEM1 0xC001001A
	251	#define MSR_K8_TOP_MEM2 0xC001001D
17158d17	252	#define MSR_K8_SYSCFG 0xC0010010
7d318d77	253	#define MSR_K8_HWCR 0xC0010015
1da177e4 LT	254
	255	/* K6 MSRs */
	256	#define MSR_K6_EFER 0xC0000080
	257	#define MSR_K6_STAR 0xC0000081
	258	#define MSR_K6_WHCR 0xC0000082
	259	#define MSR_K6_UWCCR 0xC0000085
	260	#define MSR_K6_PSOR 0xC0000087
	261	#define MSR_K6_PFIR 0xC0000088
	262
	263	/* Centaur-Hauls/IDT defined MSRs. */
	264	#define MSR_IDT_FCR1 0x107
	265	#define MSR_IDT_FCR2 0x108
	266	#define MSR_IDT_FCR3 0x109
	267	#define MSR_IDT_FCR4 0x10a
	268
	269	#define MSR_IDT_MCR0 0x110
	270	#define MSR_IDT_MCR1 0x111
	271	#define MSR_IDT_MCR2 0x112
	272	#define MSR_IDT_MCR3 0x113
	273	#define MSR_IDT_MCR4 0x114
	274	#define MSR_IDT_MCR5 0x115
	275	#define MSR_IDT_MCR6 0x116
	276	#define MSR_IDT_MCR7 0x117
	277	#define MSR_IDT_MCR_CTRL 0x120
	278
	279	/* VIA Cyrix defined MSRs*/
	280	#define MSR_VIA_FCR 0x1107
	281	#define MSR_VIA_LONGHAUL 0x110a
	282	#define MSR_VIA_RNG 0x110b
	283	#define MSR_VIA_BCR2 0x1147
	284
	285	/* Intel defined MSRs. */
	286	#define MSR_IA32_P5_MC_ADDR 0
	287	#define MSR_IA32_P5_MC_TYPE 1
	288	#define MSR_IA32_PLATFORM_ID 0x17
	289	#define MSR_IA32_EBL_CR_POWERON 0x2a
	290
	291	#define MSR_IA32_APICBASE 0x1b
	292	#define MSR_IA32_APICBASE_BSP (1<<8)
	293	#define MSR_IA32_APICBASE_ENABLE (1<<11)
	294	#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
	295
	296	/* P4/Xeon+ specific */
	297	#define MSR_IA32_MCG_EAX 0x180
	298	#define MSR_IA32_MCG_EBX 0x181
	299	#define MSR_IA32_MCG_ECX 0x182
	300	#define MSR_IA32_MCG_EDX 0x183
	301	#define MSR_IA32_MCG_ESI 0x184
	302	#define MSR_IA32_MCG_EDI 0x185
	303	#define MSR_IA32_MCG_EBP 0x186
	304	#define MSR_IA32_MCG_ESP 0x187
	305	#define MSR_IA32_MCG_EFLAGS 0x188
	306	#define MSR_IA32_MCG_EIP 0x189
	307	#define MSR_IA32_MCG_RESERVED 0x18A
	308
	309	#define MSR_P6_EVNTSEL0 0x186
	310	#define MSR_P6_EVNTSEL1 0x187
	311
	312	#define MSR_IA32_PERF_STATUS 0x198
	313	#define MSR_IA32_PERF_CTL 0x199
	314
dfde5d62 VP	315	#define MSR_IA32_MPERF 0xE7
	316	#define MSR_IA32_APERF 0xE8
	317
1da177e4 LT	318	#define MSR_IA32_THERM_CONTROL 0x19a
	319	#define MSR_IA32_THERM_INTERRUPT 0x19b
	320	#define MSR_IA32_THERM_STATUS 0x19c
	321	#define MSR_IA32_MISC_ENABLE 0x1a0
	322
	323	#define MSR_IA32_DEBUGCTLMSR 0x1d9
	324	#define MSR_IA32_LASTBRANCHFROMIP 0x1db
	325	#define MSR_IA32_LASTBRANCHTOIP 0x1dc
	326	#define MSR_IA32_LASTINTFROMIP 0x1dd
	327	#define MSR_IA32_LASTINTTOIP 0x1de
	328
	329	#define MSR_IA32_MC0_CTL 0x400
	330	#define MSR_IA32_MC0_STATUS 0x401
	331	#define MSR_IA32_MC0_ADDR 0x402
	332	#define MSR_IA32_MC0_MISC 0x403
	333
	334	/* Pentium IV performance counter MSRs */
	335	#define MSR_P4_BPU_PERFCTR0 0x300
	336	#define MSR_P4_BPU_PERFCTR1 0x301
	337	#define MSR_P4_BPU_PERFCTR2 0x302
	338	#define MSR_P4_BPU_PERFCTR3 0x303
	339	#define MSR_P4_MS_PERFCTR0 0x304
	340	#define MSR_P4_MS_PERFCTR1 0x305
	341	#define MSR_P4_MS_PERFCTR2 0x306
	342	#define MSR_P4_MS_PERFCTR3 0x307
	343	#define MSR_P4_FLAME_PERFCTR0 0x308
	344	#define MSR_P4_FLAME_PERFCTR1 0x309
	345	#define MSR_P4_FLAME_PERFCTR2 0x30a
	346	#define MSR_P4_FLAME_PERFCTR3 0x30b
	347	#define MSR_P4_IQ_PERFCTR0 0x30c
	348	#define MSR_P4_IQ_PERFCTR1 0x30d
	349	#define MSR_P4_IQ_PERFCTR2 0x30e
	350	#define MSR_P4_IQ_PERFCTR3 0x30f
	351	#define MSR_P4_IQ_PERFCTR4 0x310
	352	#define MSR_P4_IQ_PERFCTR5 0x311
	353	#define MSR_P4_BPU_CCCR0 0x360
	354	#define MSR_P4_BPU_CCCR1 0x361
	355	#define MSR_P4_BPU_CCCR2 0x362
	356	#define MSR_P4_BPU_CCCR3 0x363
	357	#define MSR_P4_MS_CCCR0 0x364
	358	#define MSR_P4_MS_CCCR1 0x365
	359	#define MSR_P4_MS_CCCR2 0x366
	360	#define MSR_P4_MS_CCCR3 0x367
	361	#define MSR_P4_FLAME_CCCR0 0x368
	362	#define MSR_P4_FLAME_CCCR1 0x369
	363	#define MSR_P4_FLAME_CCCR2 0x36a
	364	#define MSR_P4_FLAME_CCCR3 0x36b
	365	#define MSR_P4_IQ_CCCR0 0x36c
	366	#define MSR_P4_IQ_CCCR1 0x36d
	367	#define MSR_P4_IQ_CCCR2 0x36e
	368	#define MSR_P4_IQ_CCCR3 0x36f
	369	#define MSR_P4_IQ_CCCR4 0x370
	370	#define MSR_P4_IQ_CCCR5 0x371
	371	#define MSR_P4_ALF_ESCR0 0x3ca
	372	#define MSR_P4_ALF_ESCR1 0x3cb
	373	#define MSR_P4_BPU_ESCR0 0x3b2
	374	#define MSR_P4_BPU_ESCR1 0x3b3
	375	#define MSR_P4_BSU_ESCR0 0x3a0
	376	#define MSR_P4_BSU_ESCR1 0x3a1
	377	#define MSR_P4_CRU_ESCR0 0x3b8
	378	#define MSR_P4_CRU_ESCR1 0x3b9
	379	#define MSR_P4_CRU_ESCR2 0x3cc
	380	#define MSR_P4_CRU_ESCR3 0x3cd
	381	#define MSR_P4_CRU_ESCR4 0x3e0
382	#define MSR_P4_CRU_ESCR5 0x3e1
383	#define MSR_P4_DAC_ESCR0 0x3a8
384	#define MSR_P4_DAC_ESCR1 0x3a9
385	#define MSR_P4_FIRM_ESCR0 0x3a4
386	#define MSR_P4_FIRM_ESCR1 0x3a5
387	#define MSR_P4_FLAME_ESCR0 0x3a6
388	#define MSR_P4_FLAME_ESCR1 0x3a7
389	#define MSR_P4_FSB_ESCR0 0x3a2
390	#define MSR_P4_FSB_ESCR1 0x3a3
391	#define MSR_P4_IQ_ESCR0 0x3ba
392	#define MSR_P4_IQ_ESCR1 0x3bb
393	#define MSR_P4_IS_ESCR0 0x3b4
394	#define MSR_P4_IS_ESCR1 0x3b5
395	#define MSR_P4_ITLB_ESCR0 0x3b6
396	#define MSR_P4_ITLB_ESCR1 0x3b7
397	#define MSR_P4_IX_ESCR0 0x3c8
398	#define MSR_P4_IX_ESCR1 0x3c9
399	#define MSR_P4_MOB_ESCR0 0x3aa
400	#define MSR_P4_MOB_ESCR1 0x3ab
401	#define MSR_P4_MS_ESCR0 0x3c0
402	#define MSR_P4_MS_ESCR1 0x3c1
403	#define MSR_P4_PMH_ESCR0 0x3ac
404	#define MSR_P4_PMH_ESCR1 0x3ad
405	#define MSR_P4_RAT_ESCR0 0x3bc
406	#define MSR_P4_RAT_ESCR1 0x3bd
407	#define MSR_P4_SAAT_ESCR0 0x3ae
408	#define MSR_P4_SAAT_ESCR1 0x3af
409	#define MSR_P4_SSU_ESCR0 0x3be
410	#define MSR_P4_SSU_ESCR1 0x3bf /* guess: not defined in manual */
411	#define MSR_P4_TBPU_ESCR0 0x3c2
412	#define MSR_P4_TBPU_ESCR1 0x3c3
413	#define MSR_P4_TC_ESCR0 0x3c4
414	#define MSR_P4_TC_ESCR1 0x3c5
415	#define MSR_P4_U2L_ESCR0 0x3b0
416	#define MSR_P4_U2L_ESCR1 0x3b1
417
86efef50 SE	418	/* Intel Core-based CPU performance counters */
	419	#define MSR_CORE_PERF_FIXED_CTR0 0x309
	420	#define MSR_CORE_PERF_FIXED_CTR1 0x30a
	421	#define MSR_CORE_PERF_FIXED_CTR2 0x30b
	422	#define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d
	423	#define MSR_CORE_PERF_GLOBAL_STATUS 0x38e
	424	#define MSR_CORE_PERF_GLOBAL_CTRL 0x38f
	425	#define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390
	426
1da177e4	427	#endif