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dc1e35c6 SS |
1 | #ifndef __ASM_X86_XSAVE_H |
2 | #define __ASM_X86_XSAVE_H | |
3 | ||
4 | #include <asm/processor.h> | |
5 | #include <asm/i387.h> | |
6 | ||
7 | #define XSTATE_FP 0x1 | |
8 | #define XSTATE_SSE 0x2 | |
9 | ||
10 | #define XSTATE_FPSSE (XSTATE_FP | XSTATE_SSE) | |
11 | ||
12 | #define FXSAVE_SIZE 512 | |
13 | ||
14 | /* | |
15 | * These are the features that the OS can handle currently. | |
16 | */ | |
17 | #define XCNTXT_LMASK (XSTATE_FP | XSTATE_SSE) | |
18 | #define XCNTXT_HMASK 0x0 | |
19 | ||
b359e8a4 SS |
20 | #ifdef CONFIG_X86_64 |
21 | #define REX_PREFIX "0x48, " | |
22 | #else | |
23 | #define REX_PREFIX | |
24 | #endif | |
25 | ||
dc1e35c6 SS |
26 | extern unsigned int xstate_size, pcntxt_hmask, pcntxt_lmask; |
27 | extern struct xsave_struct *init_xstate_buf; | |
28 | ||
29 | extern void xsave_cntxt_init(void); | |
30 | extern void xsave_init(void); | |
b359e8a4 SS |
31 | extern int init_fpu(struct task_struct *child); |
32 | ||
33 | static inline int xrstor_checking(struct xsave_struct *fx) | |
34 | { | |
35 | int err; | |
36 | ||
37 | asm volatile("1: .byte " REX_PREFIX "0x0f,0xae,0x2f\n\t" | |
38 | "2:\n" | |
39 | ".section .fixup,\"ax\"\n" | |
40 | "3: movl $-1,%[err]\n" | |
41 | " jmp 2b\n" | |
42 | ".previous\n" | |
43 | _ASM_EXTABLE(1b, 3b) | |
44 | : [err] "=r" (err) | |
45 | : "D" (fx), "m" (*fx), "a" (-1), "d" (-1), "0" (0) | |
46 | : "memory"); | |
47 | ||
48 | return err; | |
49 | } | |
50 | ||
51 | static inline void xsave(struct task_struct *tsk) | |
52 | { | |
53 | /* This, however, we can work around by forcing the compiler to select | |
54 | an addressing mode that doesn't require extended registers. */ | |
55 | __asm__ __volatile__(".byte " REX_PREFIX "0x0f,0xae,0x27" | |
56 | : : "D" (&(tsk->thread.xstate->xsave)), | |
57 | "a" (-1), "d"(-1) : "memory"); | |
58 | } | |
dc1e35c6 | 59 | #endif |